exec: Restrict 'cpu_ldst.h' to TCG accelerator
[qemu/armbru.git] / cpu-target.c
blobf88649c29954d7311a338e79c6a8a8376da4444c
1 /*
2 * Target-specific parts of the CPU object
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qapi/error.h"
23 #include "exec/target_page.h"
24 #include "hw/qdev-core.h"
25 #include "hw/qdev-properties.h"
26 #include "qemu/error-report.h"
27 #include "qemu/qemu-print.h"
28 #include "migration/vmstate.h"
29 #ifdef CONFIG_USER_ONLY
30 #include "qemu.h"
31 #else
32 #include "hw/core/sysemu-cpu-ops.h"
33 #include "exec/address-spaces.h"
34 #include "exec/memory.h"
35 #endif
36 #include "sysemu/cpus.h"
37 #include "sysemu/tcg.h"
38 #include "exec/tswap.h"
39 #include "exec/replay-core.h"
40 #include "exec/cpu-common.h"
41 #include "exec/exec-all.h"
42 #include "exec/tb-flush.h"
43 #include "exec/translate-all.h"
44 #include "exec/log.h"
45 #include "hw/core/accel-cpu.h"
46 #include "trace/trace-root.h"
47 #include "qemu/accel.h"
49 #ifndef CONFIG_USER_ONLY
50 static int cpu_common_post_load(void *opaque, int version_id)
52 CPUState *cpu = opaque;
54 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
55 version_id is increased. */
56 cpu->interrupt_request &= ~0x01;
57 tlb_flush(cpu);
59 /* loadvm has just updated the content of RAM, bypassing the
60 * usual mechanisms that ensure we flush TBs for writes to
61 * memory we've translated code from. So we must flush all TBs,
62 * which will now be stale.
64 tb_flush(cpu);
66 return 0;
69 static int cpu_common_pre_load(void *opaque)
71 CPUState *cpu = opaque;
73 cpu->exception_index = -1;
75 return 0;
78 static bool cpu_common_exception_index_needed(void *opaque)
80 CPUState *cpu = opaque;
82 return tcg_enabled() && cpu->exception_index != -1;
85 static const VMStateDescription vmstate_cpu_common_exception_index = {
86 .name = "cpu_common/exception_index",
87 .version_id = 1,
88 .minimum_version_id = 1,
89 .needed = cpu_common_exception_index_needed,
90 .fields = (const VMStateField[]) {
91 VMSTATE_INT32(exception_index, CPUState),
92 VMSTATE_END_OF_LIST()
96 static bool cpu_common_crash_occurred_needed(void *opaque)
98 CPUState *cpu = opaque;
100 return cpu->crash_occurred;
103 static const VMStateDescription vmstate_cpu_common_crash_occurred = {
104 .name = "cpu_common/crash_occurred",
105 .version_id = 1,
106 .minimum_version_id = 1,
107 .needed = cpu_common_crash_occurred_needed,
108 .fields = (const VMStateField[]) {
109 VMSTATE_BOOL(crash_occurred, CPUState),
110 VMSTATE_END_OF_LIST()
114 const VMStateDescription vmstate_cpu_common = {
115 .name = "cpu_common",
116 .version_id = 1,
117 .minimum_version_id = 1,
118 .pre_load = cpu_common_pre_load,
119 .post_load = cpu_common_post_load,
120 .fields = (const VMStateField[]) {
121 VMSTATE_UINT32(halted, CPUState),
122 VMSTATE_UINT32(interrupt_request, CPUState),
123 VMSTATE_END_OF_LIST()
125 .subsections = (const VMStateDescription * const []) {
126 &vmstate_cpu_common_exception_index,
127 &vmstate_cpu_common_crash_occurred,
128 NULL
131 #endif
133 bool cpu_exec_realizefn(CPUState *cpu, Error **errp)
135 /* cache the cpu class for the hotpath */
136 cpu->cc = CPU_GET_CLASS(cpu);
138 if (!accel_cpu_common_realize(cpu, errp)) {
139 return false;
142 /* Wait until cpu initialization complete before exposing cpu. */
143 cpu_list_add(cpu);
145 #ifdef CONFIG_USER_ONLY
146 assert(qdev_get_vmsd(DEVICE(cpu)) == NULL ||
147 qdev_get_vmsd(DEVICE(cpu))->unmigratable);
148 #else
149 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
150 vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
152 if (cpu->cc->sysemu_ops->legacy_vmsd != NULL) {
153 vmstate_register(NULL, cpu->cpu_index, cpu->cc->sysemu_ops->legacy_vmsd, cpu);
155 #endif /* CONFIG_USER_ONLY */
157 return true;
160 void cpu_exec_unrealizefn(CPUState *cpu)
162 #ifndef CONFIG_USER_ONLY
163 CPUClass *cc = CPU_GET_CLASS(cpu);
165 if (cc->sysemu_ops->legacy_vmsd != NULL) {
166 vmstate_unregister(NULL, cc->sysemu_ops->legacy_vmsd, cpu);
168 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
169 vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
171 #endif
173 cpu_list_remove(cpu);
175 * Now that the vCPU has been removed from the RCU list, we can call
176 * accel_cpu_common_unrealize, which may free fields using call_rcu.
178 accel_cpu_common_unrealize(cpu);
182 * This can't go in hw/core/cpu.c because that file is compiled only
183 * once for both user-mode and system builds.
185 static Property cpu_common_props[] = {
186 #ifdef CONFIG_USER_ONLY
188 * Create a property for the user-only object, so users can
189 * adjust prctl(PR_SET_UNALIGN) from the command-line.
190 * Has no effect if the target does not support the feature.
192 DEFINE_PROP_BOOL("prctl-unalign-sigbus", CPUState,
193 prctl_unalign_sigbus, false),
194 #else
196 * Create a memory property for system CPU object, so users can
197 * wire up its memory. The default if no link is set up is to use
198 * the system address space.
200 DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
201 MemoryRegion *),
202 #endif
203 DEFINE_PROP_END_OF_LIST(),
206 #ifndef CONFIG_USER_ONLY
207 static bool cpu_get_start_powered_off(Object *obj, Error **errp)
209 CPUState *cpu = CPU(obj);
210 return cpu->start_powered_off;
213 static void cpu_set_start_powered_off(Object *obj, bool value, Error **errp)
215 CPUState *cpu = CPU(obj);
216 cpu->start_powered_off = value;
218 #endif
220 void cpu_class_init_props(DeviceClass *dc)
222 #ifndef CONFIG_USER_ONLY
223 ObjectClass *oc = OBJECT_CLASS(dc);
226 * We can't use DEFINE_PROP_BOOL in the Property array for this
227 * property, because we want this to be settable after realize.
229 object_class_property_add_bool(oc, "start-powered-off",
230 cpu_get_start_powered_off,
231 cpu_set_start_powered_off);
232 #endif
234 device_class_set_props(dc, cpu_common_props);
237 void cpu_exec_initfn(CPUState *cpu)
239 cpu->as = NULL;
240 cpu->num_ases = 0;
242 #ifndef CONFIG_USER_ONLY
243 cpu->thread_id = qemu_get_thread_id();
244 cpu->memory = get_system_memory();
245 object_ref(OBJECT(cpu->memory));
246 #endif
249 char *cpu_model_from_type(const char *typename)
251 const char *suffix = "-" CPU_RESOLVING_TYPE;
253 if (!object_class_by_name(typename)) {
254 return NULL;
257 if (g_str_has_suffix(typename, suffix)) {
258 return g_strndup(typename, strlen(typename) - strlen(suffix));
261 return g_strdup(typename);
264 const char *parse_cpu_option(const char *cpu_option)
266 ObjectClass *oc;
267 CPUClass *cc;
268 gchar **model_pieces;
269 const char *cpu_type;
271 model_pieces = g_strsplit(cpu_option, ",", 2);
272 if (!model_pieces[0]) {
273 error_report("-cpu option cannot be empty");
274 exit(1);
277 oc = cpu_class_by_name(CPU_RESOLVING_TYPE, model_pieces[0]);
278 if (oc == NULL) {
279 error_report("unable to find CPU model '%s'", model_pieces[0]);
280 g_strfreev(model_pieces);
281 exit(EXIT_FAILURE);
284 cpu_type = object_class_get_name(oc);
285 cc = CPU_CLASS(oc);
286 cc->parse_features(cpu_type, model_pieces[1], &error_fatal);
287 g_strfreev(model_pieces);
288 return cpu_type;
291 #ifndef cpu_list
292 static void cpu_list_entry(gpointer data, gpointer user_data)
294 CPUClass *cc = CPU_CLASS(OBJECT_CLASS(data));
295 const char *typename = object_class_get_name(OBJECT_CLASS(data));
296 g_autofree char *model = cpu_model_from_type(typename);
298 if (cc->deprecation_note) {
299 qemu_printf(" %s (deprecated)\n", model);
300 } else {
301 qemu_printf(" %s\n", model);
305 static void cpu_list(void)
307 GSList *list;
309 list = object_class_get_list_sorted(TYPE_CPU, false);
310 qemu_printf("Available CPUs:\n");
311 g_slist_foreach(list, cpu_list_entry, NULL);
312 g_slist_free(list);
314 #endif
316 void list_cpus(void)
318 cpu_list();
321 /* enable or disable single step mode. EXCP_DEBUG is returned by the
322 CPU loop after each instruction */
323 void cpu_single_step(CPUState *cpu, int enabled)
325 if (cpu->singlestep_enabled != enabled) {
326 cpu->singlestep_enabled = enabled;
328 #if !defined(CONFIG_USER_ONLY)
329 const AccelOpsClass *ops = cpus_get_accel();
330 if (ops->update_guest_debug) {
331 ops->update_guest_debug(cpu);
333 #endif
335 trace_breakpoint_singlestep(cpu->cpu_index, enabled);
339 void cpu_abort(CPUState *cpu, const char *fmt, ...)
341 va_list ap;
342 va_list ap2;
344 va_start(ap, fmt);
345 va_copy(ap2, ap);
346 fprintf(stderr, "qemu: fatal: ");
347 vfprintf(stderr, fmt, ap);
348 fprintf(stderr, "\n");
349 cpu_dump_state(cpu, stderr, CPU_DUMP_FPU | CPU_DUMP_CCOP);
350 if (qemu_log_separate()) {
351 FILE *logfile = qemu_log_trylock();
352 if (logfile) {
353 fprintf(logfile, "qemu: fatal: ");
354 vfprintf(logfile, fmt, ap2);
355 fprintf(logfile, "\n");
356 cpu_dump_state(cpu, logfile, CPU_DUMP_FPU | CPU_DUMP_CCOP);
357 qemu_log_unlock(logfile);
360 va_end(ap2);
361 va_end(ap);
362 replay_finish();
363 #if defined(CONFIG_USER_ONLY)
365 struct sigaction act;
366 sigfillset(&act.sa_mask);
367 act.sa_handler = SIG_DFL;
368 act.sa_flags = 0;
369 sigaction(SIGABRT, &act, NULL);
371 #endif
372 abort();
375 /* physical memory access (slow version, mainly for debug) */
376 #if defined(CONFIG_USER_ONLY)
377 int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
378 void *ptr, size_t len, bool is_write)
380 int flags;
381 vaddr l, page;
382 void * p;
383 uint8_t *buf = ptr;
384 ssize_t written;
385 int ret = -1;
386 int fd = -1;
388 while (len > 0) {
389 page = addr & TARGET_PAGE_MASK;
390 l = (page + TARGET_PAGE_SIZE) - addr;
391 if (l > len)
392 l = len;
393 flags = page_get_flags(page);
394 if (!(flags & PAGE_VALID)) {
395 goto out_close;
397 if (is_write) {
398 if (flags & PAGE_WRITE) {
399 /* XXX: this code should not depend on lock_user */
400 p = lock_user(VERIFY_WRITE, addr, l, 0);
401 if (!p) {
402 goto out_close;
404 memcpy(p, buf, l);
405 unlock_user(p, addr, l);
406 } else {
407 /* Bypass the host page protection using ptrace. */
408 if (fd == -1) {
409 fd = open("/proc/self/mem", O_WRONLY);
410 if (fd == -1) {
411 goto out;
415 * If there is a TranslationBlock and we weren't bypassing the
416 * host page protection, the memcpy() above would SEGV,
417 * ultimately leading to page_unprotect(). So invalidate the
418 * translations manually. Both invalidation and pwrite() must
419 * be under mmap_lock() in order to prevent the creation of
420 * another TranslationBlock in between.
422 mmap_lock();
423 tb_invalidate_phys_range(addr, addr + l - 1);
424 written = pwrite(fd, buf, l,
425 (off_t)(uintptr_t)g2h_untagged(addr));
426 mmap_unlock();
427 if (written != l) {
428 goto out_close;
431 } else if (flags & PAGE_READ) {
432 /* XXX: this code should not depend on lock_user */
433 p = lock_user(VERIFY_READ, addr, l, 1);
434 if (!p) {
435 goto out_close;
437 memcpy(buf, p, l);
438 unlock_user(p, addr, 0);
439 } else {
440 /* Bypass the host page protection using ptrace. */
441 if (fd == -1) {
442 fd = open("/proc/self/mem", O_RDONLY);
443 if (fd == -1) {
444 goto out;
447 if (pread(fd, buf, l,
448 (off_t)(uintptr_t)g2h_untagged(addr)) != l) {
449 goto out_close;
452 len -= l;
453 buf += l;
454 addr += l;
456 ret = 0;
457 out_close:
458 if (fd != -1) {
459 close(fd);
461 out:
462 return ret;
464 #endif
466 bool target_words_bigendian(void)
468 return TARGET_BIG_ENDIAN;
471 const char *target_name(void)
473 return TARGET_NAME;