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vmxnet3: Reset packet state after emptying Tx queue
[qemu/armbru.git] / hw / net / igb_core.c
blob162ef2678941b5223499835aa9cfc46219cf0b47
1 /*
2 * Core code for QEMU igb emulation
3 *
4 * Datasheet:
5 * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/82576eg-gbe-datasheet.pdf
6 *
7 * Copyright (c) 2020-2023 Red Hat, Inc.
8 * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com)
9 * Developed by Daynix Computing LTD (http://www.daynix.com)
10 *
11 * Authors:
12 * Akihiko Odaki <akihiko.odaki@daynix.com>
13 * Gal Hammmer <gal.hammer@sap.com>
14 * Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
15 * Dmitry Fleytman <dmitry@daynix.com>
16 * Leonid Bloch <leonid@daynix.com>
17 * Yan Vugenfirer <yan@daynix.com>
18 *
19 * Based on work done by:
20 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
21 * Copyright (c) 2008 Qumranet
22 * Based on work done by:
23 * Copyright (c) 2007 Dan Aloni
24 * Copyright (c) 2004 Antony T Curtis
25 *
26 * This library is free software; you can redistribute it and/or
27 * modify it under the terms of the GNU Lesser General Public
28 * License as published by the Free Software Foundation; either
29 * version 2.1 of the License, or (at your option) any later version.
30 *
31 * This library is distributed in the hope that it will be useful,
32 * but WITHOUT ANY WARRANTY; without even the implied warranty of
33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
34 * Lesser General Public License for more details.
35 *
36 * You should have received a copy of the GNU Lesser General Public
37 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
38 */
39
40 #include "qemu/osdep.h"
41 #include "qemu/log.h"
42 #include "net/net.h"
43 #include "net/tap.h"
44 #include "hw/net/mii.h"
45 #include "hw/pci/msi.h"
46 #include "hw/pci/msix.h"
47 #include "sysemu/runstate.h"
48
49 #include "net_tx_pkt.h"
50 #include "net_rx_pkt.h"
51
52 #include "igb_common.h"
53 #include "e1000x_common.h"
54 #include "igb_core.h"
55
56 #include "trace.h"
57
58 #define E1000E_MAX_TX_FRAGS (64)
59
60 union e1000_rx_desc_union {
61 struct e1000_rx_desc legacy;
62 union e1000_adv_rx_desc adv;
63 };
64
65 typedef struct IGBTxPktVmdqCallbackContext {
66 IGBCore *core;
67 NetClientState *nc;
68 } IGBTxPktVmdqCallbackContext;
69
70 typedef struct L2Header {
71 struct eth_header eth;
72 struct vlan_header vlan;
73 } L2Header;
74
75 static ssize_t
76 igb_receive_internal(IGBCore *core, const struct iovec *iov, int iovcnt,
77 bool has_vnet, bool *external_tx);
78
79 static inline void
80 igb_set_interrupt_cause(IGBCore *core, uint32_t val);
81
82 static void igb_update_interrupt_state(IGBCore *core);
83 static void igb_reset(IGBCore *core, bool sw);
84
85 static inline void
86 igb_raise_legacy_irq(IGBCore *core)
87 {
88 trace_e1000e_irq_legacy_notify(true);
89 e1000x_inc_reg_if_not_full(core->mac, IAC);
90 pci_set_irq(core->owner, 1);
91 }
92
93 static inline void
94 igb_lower_legacy_irq(IGBCore *core)
95 {
96 trace_e1000e_irq_legacy_notify(false);
97 pci_set_irq(core->owner, 0);
98 }
99
100 static void igb_msix_notify(IGBCore *core, unsigned int vector)
101 {
102 PCIDevice *dev = core->owner;
103 uint16_t vfn;
104
105 vfn = 8 - (vector + 2) / IGBVF_MSIX_VEC_NUM;
106 if (vfn < pcie_sriov_num_vfs(core->owner)) {
107 dev = pcie_sriov_get_vf_at_index(core->owner, vfn);
108 assert(dev);
109 vector = (vector + 2) % IGBVF_MSIX_VEC_NUM;
110 } else if (vector >= IGB_MSIX_VEC_NUM) {
111 qemu_log_mask(LOG_GUEST_ERROR,
112 "igb: Tried to use vector unavailable for PF");
113 return;
114 }
115
116 msix_notify(dev, vector);
117 }
118
119 static inline void
120 igb_intrmgr_rearm_timer(IGBIntrDelayTimer *timer)
121 {
122 int64_t delay_ns = (int64_t) timer->core->mac[timer->delay_reg] *
123 timer->delay_resolution_ns;
124
125 trace_e1000e_irq_rearm_timer(timer->delay_reg << 2, delay_ns);
126
127 timer_mod(timer->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + delay_ns);
128
129 timer->running = true;
130 }
131
132 static void
133 igb_intmgr_timer_resume(IGBIntrDelayTimer *timer)
134 {
135 if (timer->running) {
136 igb_intrmgr_rearm_timer(timer);
137 }
138 }
139
140 static void
141 igb_intmgr_timer_pause(IGBIntrDelayTimer *timer)
142 {
143 if (timer->running) {
144 timer_del(timer->timer);
145 }
146 }
147
148 static void
149 igb_intrmgr_on_msix_throttling_timer(void *opaque)
150 {
151 IGBIntrDelayTimer *timer = opaque;
152 int idx = timer - &timer->core->eitr[0];
153
154 timer->running = false;
155
156 trace_e1000e_irq_msix_notify_postponed_vec(idx);
157 igb_msix_notify(timer->core, idx);
158 }
159
160 static void
161 igb_intrmgr_initialize_all_timers(IGBCore *core, bool create)
162 {
163 int i;
164
165 for (i = 0; i < IGB_INTR_NUM; i++) {
166 core->eitr[i].core = core;
167 core->eitr[i].delay_reg = EITR0 + i;
168 core->eitr[i].delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
169 }
170
171 if (!create) {
172 return;
173 }
174
175 for (i = 0; i < IGB_INTR_NUM; i++) {
176 core->eitr[i].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
177 igb_intrmgr_on_msix_throttling_timer,
178 &core->eitr[i]);
179 }
180 }
181
182 static void
183 igb_intrmgr_resume(IGBCore *core)
184 {
185 int i;
186
187 for (i = 0; i < IGB_INTR_NUM; i++) {
188 igb_intmgr_timer_resume(&core->eitr[i]);
189 }
190 }
191
192 static void
193 igb_intrmgr_pause(IGBCore *core)
194 {
195 int i;
196
197 for (i = 0; i < IGB_INTR_NUM; i++) {
198 igb_intmgr_timer_pause(&core->eitr[i]);
199 }
200 }
201
202 static void
203 igb_intrmgr_reset(IGBCore *core)
204 {
205 int i;
206
207 for (i = 0; i < IGB_INTR_NUM; i++) {
208 if (core->eitr[i].running) {
209 timer_del(core->eitr[i].timer);
210 igb_intrmgr_on_msix_throttling_timer(&core->eitr[i]);
211 }
212 }
213 }
214
215 static void
216 igb_intrmgr_pci_unint(IGBCore *core)
217 {
218 int i;
219
220 for (i = 0; i < IGB_INTR_NUM; i++) {
221 timer_free(core->eitr[i].timer);
222 }
223 }
224
225 static void
226 igb_intrmgr_pci_realize(IGBCore *core)
227 {
228 igb_intrmgr_initialize_all_timers(core, true);
229 }
230
231 static inline bool
232 igb_rx_csum_enabled(IGBCore *core)
233 {
234 return (core->mac[RXCSUM] & E1000_RXCSUM_PCSD) ? false : true;
235 }
236
237 static inline bool
238 igb_rx_use_legacy_descriptor(IGBCore *core)
239 {
240 /*
241 * TODO: If SRRCTL[n],DESCTYPE = 000b, the 82576 uses the legacy Rx
242 * descriptor.
243 */
244 return false;
245 }
246
247 static inline bool
248 igb_rss_enabled(IGBCore *core)
249 {
250 return (core->mac[MRQC] & 3) == E1000_MRQC_ENABLE_RSS_MQ &&
251 !igb_rx_csum_enabled(core) &&
252 !igb_rx_use_legacy_descriptor(core);
253 }
254
255 typedef struct E1000E_RSSInfo_st {
256 bool enabled;
257 uint32_t hash;
258 uint32_t queue;
259 uint32_t type;
260 } E1000E_RSSInfo;
261
262 static uint32_t
263 igb_rss_get_hash_type(IGBCore *core, struct NetRxPkt *pkt)
264 {
265 bool hasip4, hasip6;
266 EthL4HdrProto l4hdr_proto;
267
268 assert(igb_rss_enabled(core));
269
270 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto);
271
272 if (hasip4) {
273 trace_e1000e_rx_rss_ip4(l4hdr_proto, core->mac[MRQC],
274 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC]),
275 E1000_MRQC_EN_IPV4(core->mac[MRQC]));
276
277 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP &&
278 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC])) {
279 return E1000_MRQ_RSS_TYPE_IPV4TCP;
280 }
281
282 if (E1000_MRQC_EN_IPV4(core->mac[MRQC])) {
283 return E1000_MRQ_RSS_TYPE_IPV4;
284 }
285 } else if (hasip6) {
286 eth_ip6_hdr_info *ip6info = net_rx_pkt_get_ip6_info(pkt);
287
288 bool ex_dis = core->mac[RFCTL] & E1000_RFCTL_IPV6_EX_DIS;
289 bool new_ex_dis = core->mac[RFCTL] & E1000_RFCTL_NEW_IPV6_EXT_DIS;
290
291 /*
292 * Following two traces must not be combined because resulting
293 * event will have 11 arguments totally and some trace backends
294 * (at least "ust") have limitation of maximum 10 arguments per
295 * event. Events with more arguments fail to compile for
296 * backends like these.
297 */
298 trace_e1000e_rx_rss_ip6_rfctl(core->mac[RFCTL]);
299 trace_e1000e_rx_rss_ip6(ex_dis, new_ex_dis, l4hdr_proto,
300 ip6info->has_ext_hdrs,
301 ip6info->rss_ex_dst_valid,
302 ip6info->rss_ex_src_valid,
303 core->mac[MRQC],
304 E1000_MRQC_EN_TCPIPV6EX(core->mac[MRQC]),
305 E1000_MRQC_EN_IPV6EX(core->mac[MRQC]),
306 E1000_MRQC_EN_IPV6(core->mac[MRQC]));
307
308 if ((!ex_dis || !ip6info->has_ext_hdrs) &&
309 (!new_ex_dis || !(ip6info->rss_ex_dst_valid ||
310 ip6info->rss_ex_src_valid))) {
311
312 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP &&
313 E1000_MRQC_EN_TCPIPV6EX(core->mac[MRQC])) {
314 return E1000_MRQ_RSS_TYPE_IPV6TCPEX;
315 }
316
317 if (E1000_MRQC_EN_IPV6EX(core->mac[MRQC])) {
318 return E1000_MRQ_RSS_TYPE_IPV6EX;
319 }
320
321 }
322
323 if (E1000_MRQC_EN_IPV6(core->mac[MRQC])) {
324 return E1000_MRQ_RSS_TYPE_IPV6;
325 }
326
327 }
328
329 return E1000_MRQ_RSS_TYPE_NONE;
330 }
331
332 static uint32_t
333 igb_rss_calc_hash(IGBCore *core, struct NetRxPkt *pkt, E1000E_RSSInfo *info)
334 {
335 NetRxPktRssType type;
336
337 assert(igb_rss_enabled(core));
338
339 switch (info->type) {
340 case E1000_MRQ_RSS_TYPE_IPV4:
341 type = NetPktRssIpV4;
342 break;
343 case E1000_MRQ_RSS_TYPE_IPV4TCP:
344 type = NetPktRssIpV4Tcp;
345 break;
346 case E1000_MRQ_RSS_TYPE_IPV6TCPEX:
347 type = NetPktRssIpV6TcpEx;
348 break;
349 case E1000_MRQ_RSS_TYPE_IPV6:
350 type = NetPktRssIpV6;
351 break;
352 case E1000_MRQ_RSS_TYPE_IPV6EX:
353 type = NetPktRssIpV6Ex;
354 break;
355 default:
356 assert(false);
357 return 0;
358 }
359
360 return net_rx_pkt_calc_rss_hash(pkt, type, (uint8_t *) &core->mac[RSSRK]);
361 }
362
363 static void
364 igb_rss_parse_packet(IGBCore *core, struct NetRxPkt *pkt, bool tx,
365 E1000E_RSSInfo *info)
366 {
367 trace_e1000e_rx_rss_started();
368
369 if (tx || !igb_rss_enabled(core)) {
370 info->enabled = false;
371 info->hash = 0;
372 info->queue = 0;
373 info->type = 0;
374 trace_e1000e_rx_rss_disabled();
375 return;
376 }
377
378 info->enabled = true;
379
380 info->type = igb_rss_get_hash_type(core, pkt);
381
382 trace_e1000e_rx_rss_type(info->type);
383
384 if (info->type == E1000_MRQ_RSS_TYPE_NONE) {
385 info->hash = 0;
386 info->queue = 0;
387 return;
388 }
389
390 info->hash = igb_rss_calc_hash(core, pkt, info);
391 info->queue = E1000_RSS_QUEUE(&core->mac[RETA], info->hash);
392 }
393
394 static void
395 igb_tx_insert_vlan(IGBCore *core, uint16_t qn, struct igb_tx *tx,
396 uint16_t vlan, bool insert_vlan)
397 {
398 if (core->mac[MRQC] & 1) {
399 uint16_t pool = qn % IGB_NUM_VM_POOLS;
400
401 if (core->mac[VMVIR0 + pool] & E1000_VMVIR_VLANA_DEFAULT) {
402 /* always insert default VLAN */
403 insert_vlan = true;
404 vlan = core->mac[VMVIR0 + pool] & 0xffff;
405 } else if (core->mac[VMVIR0 + pool] & E1000_VMVIR_VLANA_NEVER) {
406 insert_vlan = false;
407 }
408 }
409
410 if (insert_vlan) {
411 net_tx_pkt_setup_vlan_header_ex(tx->tx_pkt, vlan,
412 core->mac[VET] & 0xffff);
413 }
414 }
415
416 static bool
417 igb_setup_tx_offloads(IGBCore *core, struct igb_tx *tx)
418 {
419 if (tx->first_cmd_type_len & E1000_ADVTXD_DCMD_TSE) {
420 uint32_t idx = (tx->first_olinfo_status >> 4) & 1;
421 uint32_t mss = tx->ctx[idx].mss_l4len_idx >> 16;
422 if (!net_tx_pkt_build_vheader(tx->tx_pkt, true, true, mss)) {
423 return false;
424 }
425
426 net_tx_pkt_update_ip_checksums(tx->tx_pkt);
427 e1000x_inc_reg_if_not_full(core->mac, TSCTC);
428 return true;
429 }
430
431 if (tx->first_olinfo_status & E1000_ADVTXD_POTS_TXSM) {
432 if (!net_tx_pkt_build_vheader(tx->tx_pkt, false, true, 0)) {
433 return false;
434 }
435 }
436
437 if (tx->first_olinfo_status & E1000_ADVTXD_POTS_IXSM) {
438 net_tx_pkt_update_ip_hdr_checksum(tx->tx_pkt);
439 }
440
441 return true;
442 }
443
444 static void igb_tx_pkt_mac_callback(void *core,
445 const struct iovec *iov,
446 int iovcnt,
447 const struct iovec *virt_iov,
448 int virt_iovcnt)
449 {
450 igb_receive_internal(core, virt_iov, virt_iovcnt, true, NULL);
451 }
452
453 static void igb_tx_pkt_vmdq_callback(void *opaque,
454 const struct iovec *iov,
455 int iovcnt,
456 const struct iovec *virt_iov,
457 int virt_iovcnt)
458 {
459 IGBTxPktVmdqCallbackContext *context = opaque;
460 bool external_tx;
461
462 igb_receive_internal(context->core, virt_iov, virt_iovcnt, true,
463 &external_tx);
464
465 if (external_tx) {
466 if (context->core->has_vnet) {
467 qemu_sendv_packet(context->nc, virt_iov, virt_iovcnt);
468 } else {
469 qemu_sendv_packet(context->nc, iov, iovcnt);
470 }
471 }
472 }
473
474 /* TX Packets Switching (7.10.3.6) */
475 static bool igb_tx_pkt_switch(IGBCore *core, struct igb_tx *tx,
476 NetClientState *nc)
477 {
478 IGBTxPktVmdqCallbackContext context;
479
480 /* TX switching is only used to serve VM to VM traffic. */
481 if (!(core->mac[MRQC] & 1)) {
482 goto send_out;
483 }
484
485 /* TX switching requires DTXSWC.Loopback_en bit enabled. */
486 if (!(core->mac[DTXSWC] & E1000_DTXSWC_VMDQ_LOOPBACK_EN)) {
487 goto send_out;
488 }
489
490 context.core = core;
491 context.nc = nc;
492
493 return net_tx_pkt_send_custom(tx->tx_pkt, false,
494 igb_tx_pkt_vmdq_callback, &context);
495
496 send_out:
497 return net_tx_pkt_send(tx->tx_pkt, nc);
498 }
499
500 static bool
501 igb_tx_pkt_send(IGBCore *core, struct igb_tx *tx, int queue_index)
502 {
503 int target_queue = MIN(core->max_queue_num, queue_index);
504 NetClientState *queue = qemu_get_subqueue(core->owner_nic, target_queue);
505
506 if (!igb_setup_tx_offloads(core, tx)) {
507 return false;
508 }
509
510 net_tx_pkt_dump(tx->tx_pkt);
511
512 if ((core->phy[MII_BMCR] & MII_BMCR_LOOPBACK) ||
513 ((core->mac[RCTL] & E1000_RCTL_LBM_MAC) == E1000_RCTL_LBM_MAC)) {
514 return net_tx_pkt_send_custom(tx->tx_pkt, false,
515 igb_tx_pkt_mac_callback, core);
516 } else {
517 return igb_tx_pkt_switch(core, tx, queue);
518 }
519 }
520
521 static void
522 igb_on_tx_done_update_stats(IGBCore *core, struct NetTxPkt *tx_pkt, int qn)
523 {
524 static const int PTCregs[6] = { PTC64, PTC127, PTC255, PTC511,
525 PTC1023, PTC1522 };
526
527 size_t tot_len = net_tx_pkt_get_total_len(tx_pkt) + 4;
528
529 e1000x_increase_size_stats(core->mac, PTCregs, tot_len);
530 e1000x_inc_reg_if_not_full(core->mac, TPT);
531 e1000x_grow_8reg_if_not_full(core->mac, TOTL, tot_len);
532
533 switch (net_tx_pkt_get_packet_type(tx_pkt)) {
534 case ETH_PKT_BCAST:
535 e1000x_inc_reg_if_not_full(core->mac, BPTC);
536 break;
537 case ETH_PKT_MCAST:
538 e1000x_inc_reg_if_not_full(core->mac, MPTC);
539 break;
540 case ETH_PKT_UCAST:
541 break;
542 default:
543 g_assert_not_reached();
544 }
545
546 e1000x_inc_reg_if_not_full(core->mac, GPTC);
547 e1000x_grow_8reg_if_not_full(core->mac, GOTCL, tot_len);
548
549 if (core->mac[MRQC] & 1) {
550 uint16_t pool = qn % IGB_NUM_VM_POOLS;
551
552 core->mac[PVFGOTC0 + (pool * 64)] += tot_len;
553 core->mac[PVFGPTC0 + (pool * 64)]++;
554 }
555 }
556
557 static void
558 igb_process_tx_desc(IGBCore *core,
559 PCIDevice *dev,
560 struct igb_tx *tx,
561 union e1000_adv_tx_desc *tx_desc,
562 int queue_index)
563 {
564 struct e1000_adv_tx_context_desc *tx_ctx_desc;
565 uint32_t cmd_type_len;
566 uint32_t idx;
567 uint64_t buffer_addr;
568 uint16_t length;
569
570 cmd_type_len = le32_to_cpu(tx_desc->read.cmd_type_len);
571
572 if (cmd_type_len & E1000_ADVTXD_DCMD_DEXT) {
573 if ((cmd_type_len & E1000_ADVTXD_DTYP_DATA) ==
574 E1000_ADVTXD_DTYP_DATA) {
575 /* advanced transmit data descriptor */
576 if (tx->first) {
577 tx->first_cmd_type_len = cmd_type_len;
578 tx->first_olinfo_status = le32_to_cpu(tx_desc->read.olinfo_status);
579 tx->first = false;
580 }
581 } else if ((cmd_type_len & E1000_ADVTXD_DTYP_CTXT) ==
582 E1000_ADVTXD_DTYP_CTXT) {
583 /* advanced transmit context descriptor */
584 tx_ctx_desc = (struct e1000_adv_tx_context_desc *)tx_desc;
585 idx = (le32_to_cpu(tx_ctx_desc->mss_l4len_idx) >> 4) & 1;
586 tx->ctx[idx].vlan_macip_lens = le32_to_cpu(tx_ctx_desc->vlan_macip_lens);
587 tx->ctx[idx].seqnum_seed = le32_to_cpu(tx_ctx_desc->seqnum_seed);
588 tx->ctx[idx].type_tucmd_mlhl = le32_to_cpu(tx_ctx_desc->type_tucmd_mlhl);
589 tx->ctx[idx].mss_l4len_idx = le32_to_cpu(tx_ctx_desc->mss_l4len_idx);
590 return;
591 } else {
592 /* unknown descriptor type */
593 return;
594 }
595 } else {
596 /* legacy descriptor */
597
598 /* TODO: Implement a support for legacy descriptors (7.2.2.1). */
599 }
600
601 buffer_addr = le64_to_cpu(tx_desc->read.buffer_addr);
602 length = cmd_type_len & 0xFFFF;
603
604 if (!tx->skip_cp) {
605 if (!net_tx_pkt_add_raw_fragment_pci(tx->tx_pkt, dev,
606 buffer_addr, length)) {
607 tx->skip_cp = true;
608 }
609 }
610
611 if (cmd_type_len & E1000_TXD_CMD_EOP) {
612 if (!tx->skip_cp && net_tx_pkt_parse(tx->tx_pkt)) {
613 idx = (tx->first_olinfo_status >> 4) & 1;
614 igb_tx_insert_vlan(core, queue_index, tx,
615 tx->ctx[idx].vlan_macip_lens >> 16,
616 !!(tx->first_cmd_type_len & E1000_TXD_CMD_VLE));
617
618 if (igb_tx_pkt_send(core, tx, queue_index)) {
619 igb_on_tx_done_update_stats(core, tx->tx_pkt, queue_index);
620 }
621 }
622
623 tx->first = true;
624 tx->skip_cp = false;
625 net_tx_pkt_reset(tx->tx_pkt, net_tx_pkt_unmap_frag_pci, dev);
626 }
627 }
628
629 static uint32_t igb_tx_wb_eic(IGBCore *core, int queue_idx)
630 {
631 uint32_t n, ent = 0;
632
633 n = igb_ivar_entry_tx(queue_idx);
634 ent = (core->mac[IVAR0 + n / 4] >> (8 * (n % 4))) & 0xff;
635
636 return (ent & E1000_IVAR_VALID) ? BIT(ent & 0x1f) : 0;
637 }
638
639 static uint32_t igb_rx_wb_eic(IGBCore *core, int queue_idx)
640 {
641 uint32_t n, ent = 0;
642
643 n = igb_ivar_entry_rx(queue_idx);
644 ent = (core->mac[IVAR0 + n / 4] >> (8 * (n % 4))) & 0xff;
645
646 return (ent & E1000_IVAR_VALID) ? BIT(ent & 0x1f) : 0;
647 }
648
649 typedef struct E1000E_RingInfo_st {
650 int dbah;
651 int dbal;
652 int dlen;
653 int dh;
654 int dt;
655 int idx;
656 } E1000E_RingInfo;
657
658 static inline bool
659 igb_ring_empty(IGBCore *core, const E1000E_RingInfo *r)
660 {
661 return core->mac[r->dh] == core->mac[r->dt] ||
662 core->mac[r->dt] >= core->mac[r->dlen] / E1000_RING_DESC_LEN;
663 }
664
665 static inline uint64_t
666 igb_ring_base(IGBCore *core, const E1000E_RingInfo *r)
667 {
668 uint64_t bah = core->mac[r->dbah];
669 uint64_t bal = core->mac[r->dbal];
670
671 return (bah << 32) + bal;
672 }
673
674 static inline uint64_t
675 igb_ring_head_descr(IGBCore *core, const E1000E_RingInfo *r)
676 {
677 return igb_ring_base(core, r) + E1000_RING_DESC_LEN * core->mac[r->dh];
678 }
679
680 static inline void
681 igb_ring_advance(IGBCore *core, const E1000E_RingInfo *r, uint32_t count)
682 {
683 core->mac[r->dh] += count;
684
685 if (core->mac[r->dh] * E1000_RING_DESC_LEN >= core->mac[r->dlen]) {
686 core->mac[r->dh] = 0;
687 }
688 }
689
690 static inline uint32_t
691 igb_ring_free_descr_num(IGBCore *core, const E1000E_RingInfo *r)
692 {
693 trace_e1000e_ring_free_space(r->idx, core->mac[r->dlen],
694 core->mac[r->dh], core->mac[r->dt]);
695
696 if (core->mac[r->dh] <= core->mac[r->dt]) {
697 return core->mac[r->dt] - core->mac[r->dh];
698 }
699
700 if (core->mac[r->dh] > core->mac[r->dt]) {
701 return core->mac[r->dlen] / E1000_RING_DESC_LEN +
702 core->mac[r->dt] - core->mac[r->dh];
703 }
704
705 g_assert_not_reached();
706 return 0;
707 }
708
709 static inline bool
710 igb_ring_enabled(IGBCore *core, const E1000E_RingInfo *r)
711 {
712 return core->mac[r->dlen] > 0;
713 }
714
715 typedef struct IGB_TxRing_st {
716 const E1000E_RingInfo *i;
717 struct igb_tx *tx;
718 } IGB_TxRing;
719
720 static inline int
721 igb_mq_queue_idx(int base_reg_idx, int reg_idx)
722 {
723 return (reg_idx - base_reg_idx) / 16;
724 }
725
726 static inline void
727 igb_tx_ring_init(IGBCore *core, IGB_TxRing *txr, int idx)
728 {
729 static const E1000E_RingInfo i[IGB_NUM_QUEUES] = {
730 { TDBAH0, TDBAL0, TDLEN0, TDH0, TDT0, 0 },
731 { TDBAH1, TDBAL1, TDLEN1, TDH1, TDT1, 1 },
732 { TDBAH2, TDBAL2, TDLEN2, TDH2, TDT2, 2 },
733 { TDBAH3, TDBAL3, TDLEN3, TDH3, TDT3, 3 },
734 { TDBAH4, TDBAL4, TDLEN4, TDH4, TDT4, 4 },
735 { TDBAH5, TDBAL5, TDLEN5, TDH5, TDT5, 5 },
736 { TDBAH6, TDBAL6, TDLEN6, TDH6, TDT6, 6 },
737 { TDBAH7, TDBAL7, TDLEN7, TDH7, TDT7, 7 },
738 { TDBAH8, TDBAL8, TDLEN8, TDH8, TDT8, 8 },
739 { TDBAH9, TDBAL9, TDLEN9, TDH9, TDT9, 9 },
740 { TDBAH10, TDBAL10, TDLEN10, TDH10, TDT10, 10 },
741 { TDBAH11, TDBAL11, TDLEN11, TDH11, TDT11, 11 },
742 { TDBAH12, TDBAL12, TDLEN12, TDH12, TDT12, 12 },
743 { TDBAH13, TDBAL13, TDLEN13, TDH13, TDT13, 13 },
744 { TDBAH14, TDBAL14, TDLEN14, TDH14, TDT14, 14 },
745 { TDBAH15, TDBAL15, TDLEN15, TDH15, TDT15, 15 }
746 };
747
748 assert(idx < ARRAY_SIZE(i));
749
750 txr->i = &i[idx];
751 txr->tx = &core->tx[idx];
752 }
753
754 typedef struct E1000E_RxRing_st {
755 const E1000E_RingInfo *i;
756 } E1000E_RxRing;
757
758 static inline void
759 igb_rx_ring_init(IGBCore *core, E1000E_RxRing *rxr, int idx)
760 {
761 static const E1000E_RingInfo i[IGB_NUM_QUEUES] = {
762 { RDBAH0, RDBAL0, RDLEN0, RDH0, RDT0, 0 },
763 { RDBAH1, RDBAL1, RDLEN1, RDH1, RDT1, 1 },
764 { RDBAH2, RDBAL2, RDLEN2, RDH2, RDT2, 2 },
765 { RDBAH3, RDBAL3, RDLEN3, RDH3, RDT3, 3 },
766 { RDBAH4, RDBAL4, RDLEN4, RDH4, RDT4, 4 },
767 { RDBAH5, RDBAL5, RDLEN5, RDH5, RDT5, 5 },
768 { RDBAH6, RDBAL6, RDLEN6, RDH6, RDT6, 6 },
769 { RDBAH7, RDBAL7, RDLEN7, RDH7, RDT7, 7 },
770 { RDBAH8, RDBAL8, RDLEN8, RDH8, RDT8, 8 },
771 { RDBAH9, RDBAL9, RDLEN9, RDH9, RDT9, 9 },
772 { RDBAH10, RDBAL10, RDLEN10, RDH10, RDT10, 10 },
773 { RDBAH11, RDBAL11, RDLEN11, RDH11, RDT11, 11 },
774 { RDBAH12, RDBAL12, RDLEN12, RDH12, RDT12, 12 },
775 { RDBAH13, RDBAL13, RDLEN13, RDH13, RDT13, 13 },
776 { RDBAH14, RDBAL14, RDLEN14, RDH14, RDT14, 14 },
777 { RDBAH15, RDBAL15, RDLEN15, RDH15, RDT15, 15 }
778 };
779
780 assert(idx < ARRAY_SIZE(i));
781
782 rxr->i = &i[idx];
783 }
784
785 static uint32_t
786 igb_txdesc_writeback(IGBCore *core, dma_addr_t base,
787 union e1000_adv_tx_desc *tx_desc,
788 const E1000E_RingInfo *txi)
789 {
790 PCIDevice *d;
791 uint32_t cmd_type_len = le32_to_cpu(tx_desc->read.cmd_type_len);
792 uint64_t tdwba;
793
794 tdwba = core->mac[E1000_TDWBAL(txi->idx) >> 2];
795 tdwba |= (uint64_t)core->mac[E1000_TDWBAH(txi->idx) >> 2] << 32;
796
797 if (!(cmd_type_len & E1000_TXD_CMD_RS)) {
798 return 0;
799 }
800
801 d = pcie_sriov_get_vf_at_index(core->owner, txi->idx % 8);
802 if (!d) {
803 d = core->owner;
804 }
805
806 if (tdwba & 1) {
807 uint32_t buffer = cpu_to_le32(core->mac[txi->dh]);
808 pci_dma_write(d, tdwba & ~3, &buffer, sizeof(buffer));
809 } else {
810 uint32_t status = le32_to_cpu(tx_desc->wb.status) | E1000_TXD_STAT_DD;
811
812 tx_desc->wb.status = cpu_to_le32(status);
813 pci_dma_write(d, base + offsetof(union e1000_adv_tx_desc, wb),
814 &tx_desc->wb, sizeof(tx_desc->wb));
815 }
816
817 return igb_tx_wb_eic(core, txi->idx);
818 }
819
820 static inline bool
821 igb_tx_enabled(IGBCore *core, const E1000E_RingInfo *txi)
822 {
823 bool vmdq = core->mac[MRQC] & 1;
824 uint16_t qn = txi->idx;
825 uint16_t pool = qn % IGB_NUM_VM_POOLS;
826
827 return (core->mac[TCTL] & E1000_TCTL_EN) &&
828 (!vmdq || core->mac[VFTE] & BIT(pool)) &&
829 (core->mac[TXDCTL0 + (qn * 16)] & E1000_TXDCTL_QUEUE_ENABLE);
830 }
831
832 static void
833 igb_start_xmit(IGBCore *core, const IGB_TxRing *txr)
834 {
835 PCIDevice *d;
836 dma_addr_t base;
837 union e1000_adv_tx_desc desc;
838 const E1000E_RingInfo *txi = txr->i;
839 uint32_t eic = 0;
840
841 if (!igb_tx_enabled(core, txi)) {
842 trace_e1000e_tx_disabled();
843 return;
844 }
845
846 d = pcie_sriov_get_vf_at_index(core->owner, txi->idx % 8);
847 if (!d) {
848 d = core->owner;
849 }
850
851 while (!igb_ring_empty(core, txi)) {
852 base = igb_ring_head_descr(core, txi);
853
854 pci_dma_read(d, base, &desc, sizeof(desc));
855
856 trace_e1000e_tx_descr((void *)(intptr_t)desc.read.buffer_addr,
857 desc.read.cmd_type_len, desc.wb.status);
858
859 igb_process_tx_desc(core, d, txr->tx, &desc, txi->idx);
860 igb_ring_advance(core, txi, 1);
861 eic |= igb_txdesc_writeback(core, base, &desc, txi);
862 }
863
864 if (eic) {
865 core->mac[EICR] |= eic;
866 igb_set_interrupt_cause(core, E1000_ICR_TXDW);
867 }
868
869 net_tx_pkt_reset(txr->tx->tx_pkt, net_tx_pkt_unmap_frag_pci, d);
870 }
871
872 static uint32_t
873 igb_rxbufsize(IGBCore *core, const E1000E_RingInfo *r)
874 {
875 uint32_t srrctl = core->mac[E1000_SRRCTL(r->idx) >> 2];
876 uint32_t bsizepkt = srrctl & E1000_SRRCTL_BSIZEPKT_MASK;
877 if (bsizepkt) {
878 return bsizepkt << E1000_SRRCTL_BSIZEPKT_SHIFT;
879 }
880
881 return e1000x_rxbufsize(core->mac[RCTL]);
882 }
883
884 static bool
885 igb_has_rxbufs(IGBCore *core, const E1000E_RingInfo *r, size_t total_size)
886 {
887 uint32_t bufs = igb_ring_free_descr_num(core, r);
888 uint32_t bufsize = igb_rxbufsize(core, r);
889
890 trace_e1000e_rx_has_buffers(r->idx, bufs, total_size, bufsize);
891
892 return total_size <= bufs / (core->rx_desc_len / E1000_MIN_RX_DESC_LEN) *
893 bufsize;
894 }
895
896 void
897 igb_start_recv(IGBCore *core)
898 {
899 int i;
900
901 trace_e1000e_rx_start_recv();
902
903 for (i = 0; i <= core->max_queue_num; i++) {
904 qemu_flush_queued_packets(qemu_get_subqueue(core->owner_nic, i));
905 }
906 }
907
908 bool
909 igb_can_receive(IGBCore *core)
910 {
911 int i;
912
913 if (!e1000x_rx_ready(core->owner, core->mac)) {
914 return false;
915 }
916
917 for (i = 0; i < IGB_NUM_QUEUES; i++) {
918 E1000E_RxRing rxr;
919 if (!(core->mac[RXDCTL0 + (i * 16)] & E1000_RXDCTL_QUEUE_ENABLE)) {
920 continue;
921 }
922
923 igb_rx_ring_init(core, &rxr, i);
924 if (igb_ring_enabled(core, rxr.i) && igb_has_rxbufs(core, rxr.i, 1)) {
925 trace_e1000e_rx_can_recv();
926 return true;
927 }
928 }
929
930 trace_e1000e_rx_can_recv_rings_full();
931 return false;
932 }
933
934 ssize_t
935 igb_receive(IGBCore *core, const uint8_t *buf, size_t size)
936 {
937 const struct iovec iov = {
938 .iov_base = (uint8_t *)buf,
939 .iov_len = size
940 };
941
942 return igb_receive_iov(core, &iov, 1);
943 }
944
945 static inline bool
946 igb_rx_l3_cso_enabled(IGBCore *core)
947 {
948 return !!(core->mac[RXCSUM] & E1000_RXCSUM_IPOFLD);
949 }
950
951 static inline bool
952 igb_rx_l4_cso_enabled(IGBCore *core)
953 {
954 return !!(core->mac[RXCSUM] & E1000_RXCSUM_TUOFLD);
955 }
956
957 static bool
958 igb_rx_is_oversized(IGBCore *core, uint16_t qn, size_t size)
959 {
960 uint16_t pool = qn % IGB_NUM_VM_POOLS;
961 bool lpe = !!(core->mac[VMOLR0 + pool] & E1000_VMOLR_LPE);
962 int max_ethernet_lpe_size =
963 core->mac[VMOLR0 + pool] & E1000_VMOLR_RLPML_MASK;
964 int max_ethernet_vlan_size = 1522;
965
966 return size > (lpe ? max_ethernet_lpe_size : max_ethernet_vlan_size);
967 }
968
969 static uint16_t igb_receive_assign(IGBCore *core, const L2Header *l2_header,
970 size_t size, E1000E_RSSInfo *rss_info,
971 bool *external_tx)
972 {
973 static const int ta_shift[] = { 4, 3, 2, 0 };
974 const struct eth_header *ehdr = &l2_header->eth;
975 uint32_t f, ra[2], *macp, rctl = core->mac[RCTL];
976 uint16_t queues = 0;
977 uint16_t oversized = 0;
978 uint16_t vid = be16_to_cpu(l2_header->vlan.h_tci) & VLAN_VID_MASK;
979 int i;
980
981 memset(rss_info, 0, sizeof(E1000E_RSSInfo));
982
983 if (external_tx) {
984 *external_tx = true;
985 }
986
987 if (e1000x_is_vlan_packet(ehdr, core->mac[VET] & 0xffff) &&
988 !e1000x_rx_vlan_filter(core->mac, PKT_GET_VLAN_HDR(ehdr))) {
989 return queues;
990 }
991
992 if (core->mac[MRQC] & 1) {
993 if (is_broadcast_ether_addr(ehdr->h_dest)) {
994 for (i = 0; i < IGB_NUM_VM_POOLS; i++) {
995 if (core->mac[VMOLR0 + i] & E1000_VMOLR_BAM) {
996 queues |= BIT(i);
997 }
998 }
999 } else {
1000 for (macp = core->mac + RA; macp < core->mac + RA + 32; macp += 2) {
1001 if (!(macp[1] & E1000_RAH_AV)) {
1002 continue;
1003 }
1004 ra[0] = cpu_to_le32(macp[0]);
1005 ra[1] = cpu_to_le32(macp[1]);
1006 if (!memcmp(ehdr->h_dest, (uint8_t *)ra, ETH_ALEN)) {
1007 queues |= (macp[1] & E1000_RAH_POOL_MASK) / E1000_RAH_POOL_1;
1008 }
1009 }
1010
1011 for (macp = core->mac + RA2; macp < core->mac + RA2 + 16; macp += 2) {
1012 if (!(macp[1] & E1000_RAH_AV)) {
1013 continue;
1014 }
1015 ra[0] = cpu_to_le32(macp[0]);
1016 ra[1] = cpu_to_le32(macp[1]);
1017 if (!memcmp(ehdr->h_dest, (uint8_t *)ra, ETH_ALEN)) {
1018 queues |= (macp[1] & E1000_RAH_POOL_MASK) / E1000_RAH_POOL_1;
1019 }
1020 }
1021
1022 if (!queues) {
1023 macp = core->mac + (is_multicast_ether_addr(ehdr->h_dest) ? MTA : UTA);
1024
1025 f = ta_shift[(rctl >> E1000_RCTL_MO_SHIFT) & 3];
1026 f = (((ehdr->h_dest[5] << 8) | ehdr->h_dest[4]) >> f) & 0xfff;
1027 if (macp[f >> 5] & (1 << (f & 0x1f))) {
1028 for (i = 0; i < IGB_NUM_VM_POOLS; i++) {
1029 if (core->mac[VMOLR0 + i] & E1000_VMOLR_ROMPE) {
1030 queues |= BIT(i);
1031 }
1032 }
1033 }
1034 } else if (is_unicast_ether_addr(ehdr->h_dest) && external_tx) {
1035 *external_tx = false;
1036 }
1037 }
1038
1039 if (e1000x_vlan_rx_filter_enabled(core->mac)) {
1040 uint16_t mask = 0;
1041
1042 if (e1000x_is_vlan_packet(ehdr, core->mac[VET] & 0xffff)) {
1043 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
1044 if ((core->mac[VLVF0 + i] & E1000_VLVF_VLANID_MASK) == vid &&
1045 (core->mac[VLVF0 + i] & E1000_VLVF_VLANID_ENABLE)) {
1046 uint32_t poolsel = core->mac[VLVF0 + i] & E1000_VLVF_POOLSEL_MASK;
1047 mask |= poolsel >> E1000_VLVF_POOLSEL_SHIFT;
1048 }
1049 }
1050 } else {
1051 for (i = 0; i < IGB_NUM_VM_POOLS; i++) {
1052 if (core->mac[VMOLR0 + i] & E1000_VMOLR_AUPE) {
1053 mask |= BIT(i);
1054 }
1055 }
1056 }
1057
1058 queues &= mask;
1059 }
1060
1061 if (is_unicast_ether_addr(ehdr->h_dest) && !queues && !external_tx &&
1062 !(core->mac[VT_CTL] & E1000_VT_CTL_DISABLE_DEF_POOL)) {
1063 uint32_t def_pl = core->mac[VT_CTL] & E1000_VT_CTL_DEFAULT_POOL_MASK;
1064 queues = BIT(def_pl >> E1000_VT_CTL_DEFAULT_POOL_SHIFT);
1065 }
1066
1067 queues &= core->mac[VFRE];
1068 if (queues) {
1069 for (i = 0; i < IGB_NUM_VM_POOLS; i++) {
1070 if ((queues & BIT(i)) && igb_rx_is_oversized(core, i, size)) {
1071 oversized |= BIT(i);
1072 }
1073 }
1074 /* 8.19.37 increment ROC if packet is oversized for all queues */
1075 if (oversized == queues) {
1076 trace_e1000x_rx_oversized(size);
1077 e1000x_inc_reg_if_not_full(core->mac, ROC);
1078 }
1079 queues &= ~oversized;
1080 }
1081
1082 if (queues) {
1083 igb_rss_parse_packet(core, core->rx_pkt,
1084 external_tx != NULL, rss_info);
1085 /* Sec 8.26.1: PQn = VFn + VQn*8 */
1086 if (rss_info->queue & 1) {
1087 for (i = 0; i < IGB_NUM_VM_POOLS; i++) {
1088 if ((queues & BIT(i)) &&
1089 (core->mac[VMOLR0 + i] & E1000_VMOLR_RSSE)) {
1090 queues |= BIT(i + IGB_NUM_VM_POOLS);
1091 queues &= ~BIT(i);
1092 }
1093 }
1094 }
1095 }
1096 } else {
1097 bool accepted = e1000x_rx_group_filter(core->mac, ehdr);
1098 if (!accepted) {
1099 for (macp = core->mac + RA2; macp < core->mac + RA2 + 16; macp += 2) {
1100 if (!(macp[1] & E1000_RAH_AV)) {
1101 continue;
1102 }
1103 ra[0] = cpu_to_le32(macp[0]);
1104 ra[1] = cpu_to_le32(macp[1]);
1105 if (!memcmp(ehdr->h_dest, (uint8_t *)ra, ETH_ALEN)) {
1106 trace_e1000x_rx_flt_ucast_match((int)(macp - core->mac - RA2) / 2,
1107 MAC_ARG(ehdr->h_dest));
1108
1109 accepted = true;
1110 break;
1111 }
1112 }
1113 }
1114
1115 if (accepted) {
1116 igb_rss_parse_packet(core, core->rx_pkt, false, rss_info);
1117 queues = BIT(rss_info->queue);
1118 }
1119 }
1120
1121 return queues;
1122 }
1123
1124 static inline void
1125 igb_read_lgcy_rx_descr(IGBCore *core, struct e1000_rx_desc *desc,
1126 hwaddr *buff_addr)
1127 {
1128 *buff_addr = le64_to_cpu(desc->buffer_addr);
1129 }
1130
1131 static inline void
1132 igb_read_adv_rx_descr(IGBCore *core, union e1000_adv_rx_desc *desc,
1133 hwaddr *buff_addr)
1134 {
1135 *buff_addr = le64_to_cpu(desc->read.pkt_addr);
1136 }
1137
1138 static inline void
1139 igb_read_rx_descr(IGBCore *core, union e1000_rx_desc_union *desc,
1140 hwaddr *buff_addr)
1141 {
1142 if (igb_rx_use_legacy_descriptor(core)) {
1143 igb_read_lgcy_rx_descr(core, &desc->legacy, buff_addr);
1144 } else {
1145 igb_read_adv_rx_descr(core, &desc->adv, buff_addr);
1146 }
1147 }
1148
1149 static void
1150 igb_verify_csum_in_sw(IGBCore *core,
1151 struct NetRxPkt *pkt,
1152 uint32_t *status_flags,
1153 EthL4HdrProto l4hdr_proto)
1154 {
1155 bool csum_valid;
1156 uint32_t csum_error;
1157
1158 if (igb_rx_l3_cso_enabled(core)) {
1159 if (!net_rx_pkt_validate_l3_csum(pkt, &csum_valid)) {
1160 trace_e1000e_rx_metadata_l3_csum_validation_failed();
1161 } else {
1162 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_IPE;
1163 *status_flags |= E1000_RXD_STAT_IPCS | csum_error;
1164 }
1165 } else {
1166 trace_e1000e_rx_metadata_l3_cso_disabled();
1167 }
1168
1169 if (!igb_rx_l4_cso_enabled(core)) {
1170 trace_e1000e_rx_metadata_l4_cso_disabled();
1171 return;
1172 }
1173
1174 if (!net_rx_pkt_validate_l4_csum(pkt, &csum_valid)) {
1175 trace_e1000e_rx_metadata_l4_csum_validation_failed();
1176 return;
1177 }
1178
1179 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_TCPE;
1180 *status_flags |= E1000_RXD_STAT_TCPCS | csum_error;
1181
1182 if (l4hdr_proto == ETH_L4_HDR_PROTO_UDP) {
1183 *status_flags |= E1000_RXD_STAT_UDPCS;
1184 }
1185 }
1186
1187 static void
1188 igb_build_rx_metadata(IGBCore *core,
1189 struct NetRxPkt *pkt,
1190 bool is_eop,
1191 const E1000E_RSSInfo *rss_info,
1192 uint16_t *pkt_info, uint16_t *hdr_info,
1193 uint32_t *rss,
1194 uint32_t *status_flags,
1195 uint16_t *ip_id,
1196 uint16_t *vlan_tag)
1197 {
1198 struct virtio_net_hdr *vhdr;
1199 bool hasip4, hasip6;
1200 EthL4HdrProto l4hdr_proto;
1201
1202 *status_flags = E1000_RXD_STAT_DD;
1203
1204 /* No additional metadata needed for non-EOP descriptors */
1205 /* TODO: EOP apply only to status so don't skip whole function. */
1206 if (!is_eop) {
1207 goto func_exit;
1208 }
1209
1210 *status_flags |= E1000_RXD_STAT_EOP;
1211
1212 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto);
1213 trace_e1000e_rx_metadata_protocols(hasip4, hasip6, l4hdr_proto);
1214
1215 /* VLAN state */
1216 if (net_rx_pkt_is_vlan_stripped(pkt)) {
1217 *status_flags |= E1000_RXD_STAT_VP;
1218 *vlan_tag = cpu_to_le16(net_rx_pkt_get_vlan_tag(pkt));
1219 trace_e1000e_rx_metadata_vlan(*vlan_tag);
1220 }
1221
1222 /* Packet parsing results */
1223 if ((core->mac[RXCSUM] & E1000_RXCSUM_PCSD) != 0) {
1224 if (rss_info->enabled) {
1225 *rss = cpu_to_le32(rss_info->hash);
1226 trace_igb_rx_metadata_rss(*rss);
1227 }
1228 } else if (hasip4) {
1229 *status_flags |= E1000_RXD_STAT_IPIDV;
1230 *ip_id = cpu_to_le16(net_rx_pkt_get_ip_id(pkt));
1231 trace_e1000e_rx_metadata_ip_id(*ip_id);
1232 }
1233
1234 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP && net_rx_pkt_is_tcp_ack(pkt)) {
1235 *status_flags |= E1000_RXD_STAT_ACK;
1236 trace_e1000e_rx_metadata_ack();
1237 }
1238
1239 if (pkt_info) {
1240 *pkt_info = rss_info->enabled ? rss_info->type : 0;
1241
1242 if (hasip4) {
1243 *pkt_info |= E1000_ADVRXD_PKT_IP4;
1244 }
1245
1246 if (hasip6) {
1247 *pkt_info |= E1000_ADVRXD_PKT_IP6;
1248 }
1249
1250 switch (l4hdr_proto) {
1251 case ETH_L4_HDR_PROTO_TCP:
1252 *pkt_info |= E1000_ADVRXD_PKT_TCP;
1253 break;
1254
1255 case ETH_L4_HDR_PROTO_UDP:
1256 *pkt_info |= E1000_ADVRXD_PKT_UDP;
1257 break;
1258
1259 default:
1260 break;
1261 }
1262 }
1263
1264 if (hdr_info) {
1265 *hdr_info = 0;
1266 }
1267
1268 /* RX CSO information */
1269 if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_XSUM_DIS)) {
1270 trace_e1000e_rx_metadata_ipv6_sum_disabled();
1271 goto func_exit;
1272 }
1273
1274 vhdr = net_rx_pkt_get_vhdr(pkt);
1275
1276 if (!(vhdr->flags & VIRTIO_NET_HDR_F_DATA_VALID) &&
1277 !(vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM)) {
1278 trace_e1000e_rx_metadata_virthdr_no_csum_info();
1279 igb_verify_csum_in_sw(core, pkt, status_flags, l4hdr_proto);
1280 goto func_exit;
1281 }
1282
1283 if (igb_rx_l3_cso_enabled(core)) {
1284 *status_flags |= hasip4 ? E1000_RXD_STAT_IPCS : 0;
1285 } else {
1286 trace_e1000e_rx_metadata_l3_cso_disabled();
1287 }
1288
1289 if (igb_rx_l4_cso_enabled(core)) {
1290 switch (l4hdr_proto) {
1291 case ETH_L4_HDR_PROTO_TCP:
1292 *status_flags |= E1000_RXD_STAT_TCPCS;
1293 break;
1294
1295 case ETH_L4_HDR_PROTO_UDP:
1296 *status_flags |= E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS;
1297 break;
1298
1299 default:
1300 break;
1301 }
1302 } else {
1303 trace_e1000e_rx_metadata_l4_cso_disabled();
1304 }
1305
1306 func_exit:
1307 trace_e1000e_rx_metadata_status_flags(*status_flags);
1308 *status_flags = cpu_to_le32(*status_flags);
1309 }
1310
1311 static inline void
1312 igb_write_lgcy_rx_descr(IGBCore *core, struct e1000_rx_desc *desc,
1313 struct NetRxPkt *pkt,
1314 const E1000E_RSSInfo *rss_info,
1315 uint16_t length)
1316 {
1317 uint32_t status_flags, rss;
1318 uint16_t ip_id;
1319
1320 assert(!rss_info->enabled);
1321 desc->length = cpu_to_le16(length);
1322 desc->csum = 0;
1323
1324 igb_build_rx_metadata(core, pkt, pkt != NULL,
1325 rss_info,
1326 NULL, NULL, &rss,
1327 &status_flags, &ip_id,
1328 &desc->special);
1329 desc->errors = (uint8_t) (le32_to_cpu(status_flags) >> 24);
1330 desc->status = (uint8_t) le32_to_cpu(status_flags);
1331 }
1332
1333 static inline void
1334 igb_write_adv_rx_descr(IGBCore *core, union e1000_adv_rx_desc *desc,
1335 struct NetRxPkt *pkt,
1336 const E1000E_RSSInfo *rss_info,
1337 uint16_t length)
1338 {
1339 memset(&desc->wb, 0, sizeof(desc->wb));
1340
1341 desc->wb.upper.length = cpu_to_le16(length);
1342
1343 igb_build_rx_metadata(core, pkt, pkt != NULL,
1344 rss_info,
1345 &desc->wb.lower.lo_dword.pkt_info,
1346 &desc->wb.lower.lo_dword.hdr_info,
1347 &desc->wb.lower.hi_dword.rss,
1348 &desc->wb.upper.status_error,
1349 &desc->wb.lower.hi_dword.csum_ip.ip_id,
1350 &desc->wb.upper.vlan);
1351 }
1352
1353 static inline void
1354 igb_write_rx_descr(IGBCore *core, union e1000_rx_desc_union *desc,
1355 struct NetRxPkt *pkt, const E1000E_RSSInfo *rss_info, uint16_t length)
1356 {
1357 if (igb_rx_use_legacy_descriptor(core)) {
1358 igb_write_lgcy_rx_descr(core, &desc->legacy, pkt, rss_info, length);
1359 } else {
1360 igb_write_adv_rx_descr(core, &desc->adv, pkt, rss_info, length);
1361 }
1362 }
1363
1364 static inline void
1365 igb_pci_dma_write_rx_desc(IGBCore *core, PCIDevice *dev, dma_addr_t addr,
1366 union e1000_rx_desc_union *desc, dma_addr_t len)
1367 {
1368 if (igb_rx_use_legacy_descriptor(core)) {
1369 struct e1000_rx_desc *d = &desc->legacy;
1370 size_t offset = offsetof(struct e1000_rx_desc, status);
1371 uint8_t status = d->status;
1372
1373 d->status &= ~E1000_RXD_STAT_DD;
1374 pci_dma_write(dev, addr, desc, len);
1375
1376 if (status & E1000_RXD_STAT_DD) {
1377 d->status = status;
1378 pci_dma_write(dev, addr + offset, &status, sizeof(status));
1379 }
1380 } else {
1381 union e1000_adv_rx_desc *d = &desc->adv;
1382 size_t offset =
1383 offsetof(union e1000_adv_rx_desc, wb.upper.status_error);
1384 uint32_t status = d->wb.upper.status_error;
1385
1386 d->wb.upper.status_error &= ~E1000_RXD_STAT_DD;
1387 pci_dma_write(dev, addr, desc, len);
1388
1389 if (status & E1000_RXD_STAT_DD) {
1390 d->wb.upper.status_error = status;
1391 pci_dma_write(dev, addr + offset, &status, sizeof(status));
1392 }
1393 }
1394 }
1395
1396 static void
1397 igb_write_to_rx_buffers(IGBCore *core,
1398 PCIDevice *d,
1399 hwaddr ba,
1400 uint16_t *written,
1401 const char *data,
1402 dma_addr_t data_len)
1403 {
1404 trace_igb_rx_desc_buff_write(ba, *written, data, data_len);
1405 pci_dma_write(d, ba + *written, data, data_len);
1406 *written += data_len;
1407 }
1408
1409 static void
1410 igb_update_rx_stats(IGBCore *core, const E1000E_RingInfo *rxi,
1411 size_t pkt_size, size_t pkt_fcs_size)
1412 {
1413 eth_pkt_types_e pkt_type = net_rx_pkt_get_packet_type(core->rx_pkt);
1414 e1000x_update_rx_total_stats(core->mac, pkt_type, pkt_size, pkt_fcs_size);
1415
1416 if (core->mac[MRQC] & 1) {
1417 uint16_t pool = rxi->idx % IGB_NUM_VM_POOLS;
1418
1419 core->mac[PVFGORC0 + (pool * 64)] += pkt_size + 4;
1420 core->mac[PVFGPRC0 + (pool * 64)]++;
1421 if (pkt_type == ETH_PKT_MCAST) {
1422 core->mac[PVFMPRC0 + (pool * 64)]++;
1423 }
1424 }
1425 }
1426
1427 static inline bool
1428 igb_rx_descr_threshold_hit(IGBCore *core, const E1000E_RingInfo *rxi)
1429 {
1430 return igb_ring_free_descr_num(core, rxi) ==
1431 ((core->mac[E1000_SRRCTL(rxi->idx) >> 2] >> 20) & 31) * 16;
1432 }
1433
1434 static void
1435 igb_write_packet_to_guest(IGBCore *core, struct NetRxPkt *pkt,
1436 const E1000E_RxRing *rxr,
1437 const E1000E_RSSInfo *rss_info)
1438 {
1439 PCIDevice *d;
1440 dma_addr_t base;
1441 union e1000_rx_desc_union desc;
1442 size_t desc_size;
1443 size_t desc_offset = 0;
1444 size_t iov_ofs = 0;
1445
1446 struct iovec *iov = net_rx_pkt_get_iovec(pkt);
1447 size_t size = net_rx_pkt_get_total_len(pkt);
1448 size_t total_size = size + e1000x_fcs_len(core->mac);
1449 const E1000E_RingInfo *rxi = rxr->i;
1450 size_t bufsize = igb_rxbufsize(core, rxi);
1451
1452 d = pcie_sriov_get_vf_at_index(core->owner, rxi->idx % 8);
1453 if (!d) {
1454 d = core->owner;
1455 }
1456
1457 do {
1458 hwaddr ba;
1459 uint16_t written = 0;
1460 bool is_last = false;
1461
1462 desc_size = total_size - desc_offset;
1463
1464 if (desc_size > bufsize) {
1465 desc_size = bufsize;
1466 }
1467
1468 if (igb_ring_empty(core, rxi)) {
1469 return;
1470 }
1471
1472 base = igb_ring_head_descr(core, rxi);
1473
1474 pci_dma_read(d, base, &desc, core->rx_desc_len);
1475
1476 trace_e1000e_rx_descr(rxi->idx, base, core->rx_desc_len);
1477
1478 igb_read_rx_descr(core, &desc, &ba);
1479
1480 if (ba) {
1481 if (desc_offset < size) {
1482 static const uint32_t fcs_pad;
1483 size_t iov_copy;
1484 size_t copy_size = size - desc_offset;
1485 if (copy_size > bufsize) {
1486 copy_size = bufsize;
1487 }
1488
1489 /* Copy packet payload */
1490 while (copy_size) {
1491 iov_copy = MIN(copy_size, iov->iov_len - iov_ofs);
1492
1493 igb_write_to_rx_buffers(core, d, ba, &written,
1494 iov->iov_base + iov_ofs, iov_copy);
1495
1496 copy_size -= iov_copy;
1497 iov_ofs += iov_copy;
1498 if (iov_ofs == iov->iov_len) {
1499 iov++;
1500 iov_ofs = 0;
1501 }
1502 }
1503
1504 if (desc_offset + desc_size >= total_size) {
1505 /* Simulate FCS checksum presence in the last descriptor */
1506 igb_write_to_rx_buffers(core, d, ba, &written,
1507 (const char *) &fcs_pad, e1000x_fcs_len(core->mac));
1508 }
1509 }
1510 } else { /* as per intel docs; skip descriptors with null buf addr */
1511 trace_e1000e_rx_null_descriptor();
1512 }
1513 desc_offset += desc_size;
1514 if (desc_offset >= total_size) {
1515 is_last = true;
1516 }
1517
1518 igb_write_rx_descr(core, &desc, is_last ? core->rx_pkt : NULL,
1519 rss_info, written);
1520 igb_pci_dma_write_rx_desc(core, d, base, &desc, core->rx_desc_len);
1521
1522 igb_ring_advance(core, rxi, core->rx_desc_len / E1000_MIN_RX_DESC_LEN);
1523
1524 } while (desc_offset < total_size);
1525
1526 igb_update_rx_stats(core, rxi, size, total_size);
1527 }
1528
1529 static bool
1530 igb_rx_strip_vlan(IGBCore *core, const E1000E_RingInfo *rxi)
1531 {
1532 if (core->mac[MRQC] & 1) {
1533 uint16_t pool = rxi->idx % IGB_NUM_VM_POOLS;
1534 /* Sec 7.10.3.8: CTRL.VME is ignored, only VMOLR/RPLOLR is used */
1535 return (net_rx_pkt_get_packet_type(core->rx_pkt) == ETH_PKT_MCAST) ?
1536 core->mac[RPLOLR] & E1000_RPLOLR_STRVLAN :
1537 core->mac[VMOLR0 + pool] & E1000_VMOLR_STRVLAN;
1538 }
1539
1540 return e1000x_vlan_enabled(core->mac);
1541 }
1542
1543 static inline void
1544 igb_rx_fix_l4_csum(IGBCore *core, struct NetRxPkt *pkt)
1545 {
1546 struct virtio_net_hdr *vhdr = net_rx_pkt_get_vhdr(pkt);
1547
1548 if (vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM) {
1549 net_rx_pkt_fix_l4_csum(pkt);
1550 }
1551 }
1552
1553 ssize_t
1554 igb_receive_iov(IGBCore *core, const struct iovec *iov, int iovcnt)
1555 {
1556 return igb_receive_internal(core, iov, iovcnt, core->has_vnet, NULL);
1557 }
1558
1559 static ssize_t
1560 igb_receive_internal(IGBCore *core, const struct iovec *iov, int iovcnt,
1561 bool has_vnet, bool *external_tx)
1562 {
1563 uint16_t queues = 0;
1564 uint32_t n = 0;
1565 union {
1566 L2Header l2_header;
1567 uint8_t octets[ETH_ZLEN];
1568 } buf;
1569 struct iovec min_iov;
1570 size_t size, orig_size;
1571 size_t iov_ofs = 0;
1572 E1000E_RxRing rxr;
1573 E1000E_RSSInfo rss_info;
1574 size_t total_size;
1575 int i;
1576
1577 trace_e1000e_rx_receive_iov(iovcnt);
1578
1579 if (external_tx) {
1580 *external_tx = true;
1581 }
1582
1583 if (!e1000x_hw_rx_enabled(core->mac)) {
1584 return -1;
1585 }
1586
1587 /* Pull virtio header in */
1588 if (has_vnet) {
1589 net_rx_pkt_set_vhdr_iovec(core->rx_pkt, iov, iovcnt);
1590 iov_ofs = sizeof(struct virtio_net_hdr);
1591 } else {
1592 net_rx_pkt_unset_vhdr(core->rx_pkt);
1593 }
1594
1595 orig_size = iov_size(iov, iovcnt);
1596 size = orig_size - iov_ofs;
1597
1598 /* Pad to minimum Ethernet frame length */
1599 if (size < sizeof(buf)) {
1600 iov_to_buf(iov, iovcnt, iov_ofs, &buf, size);
1601 memset(&buf.octets[size], 0, sizeof(buf) - size);
1602 e1000x_inc_reg_if_not_full(core->mac, RUC);
1603 min_iov.iov_base = &buf;
1604 min_iov.iov_len = size = sizeof(buf);
1605 iovcnt = 1;
1606 iov = &min_iov;
1607 iov_ofs = 0;
1608 } else {
1609 iov_to_buf(iov, iovcnt, iov_ofs, &buf, sizeof(buf.l2_header));
1610 }
1611
1612 /* Discard oversized packets if !LPE and !SBP. */
1613 if (e1000x_is_oversized(core->mac, size)) {
1614 return orig_size;
1615 }
1616
1617 net_rx_pkt_set_packet_type(core->rx_pkt,
1618 get_eth_packet_type(&buf.l2_header.eth));
1619 net_rx_pkt_set_protocols(core->rx_pkt, iov, iovcnt, iov_ofs);
1620
1621 queues = igb_receive_assign(core, &buf.l2_header, size,
1622 &rss_info, external_tx);
1623 if (!queues) {
1624 trace_e1000e_rx_flt_dropped();
1625 return orig_size;
1626 }
1627
1628 for (i = 0; i < IGB_NUM_QUEUES; i++) {
1629 if (!(queues & BIT(i)) ||
1630 !(core->mac[RXDCTL0 + (i * 16)] & E1000_RXDCTL_QUEUE_ENABLE)) {
1631 continue;
1632 }
1633
1634 igb_rx_ring_init(core, &rxr, i);
1635
1636 net_rx_pkt_attach_iovec_ex(core->rx_pkt, iov, iovcnt, iov_ofs,
1637 igb_rx_strip_vlan(core, rxr.i),
1638 core->mac[VET] & 0xffff);
1639
1640 total_size = net_rx_pkt_get_total_len(core->rx_pkt) +
1641 e1000x_fcs_len(core->mac);
1642
1643 if (!igb_has_rxbufs(core, rxr.i, total_size)) {
1644 n |= E1000_ICS_RXO;
1645 trace_e1000e_rx_not_written_to_guest(rxr.i->idx);
1646 continue;
1647 }
1648
1649 n |= E1000_ICR_RXDW;
1650
1651 igb_rx_fix_l4_csum(core, core->rx_pkt);
1652 igb_write_packet_to_guest(core, core->rx_pkt, &rxr, &rss_info);
1653
1654 /* Check if receive descriptor minimum threshold hit */
1655 if (igb_rx_descr_threshold_hit(core, rxr.i)) {
1656 n |= E1000_ICS_RXDMT0;
1657 }
1658
1659 core->mac[EICR] |= igb_rx_wb_eic(core, rxr.i->idx);
1660
1661 trace_e1000e_rx_written_to_guest(rxr.i->idx);
1662 }
1663
1664 trace_e1000e_rx_interrupt_set(n);
1665 igb_set_interrupt_cause(core, n);
1666
1667 return orig_size;
1668 }
1669
1670 static inline bool
1671 igb_have_autoneg(IGBCore *core)
1672 {
1673 return core->phy[MII_BMCR] & MII_BMCR_AUTOEN;
1674 }
1675
1676 static void igb_update_flowctl_status(IGBCore *core)
1677 {
1678 if (igb_have_autoneg(core) && core->phy[MII_BMSR] & MII_BMSR_AN_COMP) {
1679 trace_e1000e_link_autoneg_flowctl(true);
1680 core->mac[CTRL] |= E1000_CTRL_TFCE | E1000_CTRL_RFCE;
1681 } else {
1682 trace_e1000e_link_autoneg_flowctl(false);
1683 }
1684 }
1685
1686 static inline void
1687 igb_link_down(IGBCore *core)
1688 {
1689 e1000x_update_regs_on_link_down(core->mac, core->phy);
1690 igb_update_flowctl_status(core);
1691 }
1692
1693 static inline void
1694 igb_set_phy_ctrl(IGBCore *core, uint16_t val)
1695 {
1696 /* bits 0-5 reserved; MII_BMCR_[ANRESTART,RESET] are self clearing */
1697 core->phy[MII_BMCR] = val & ~(0x3f | MII_BMCR_RESET | MII_BMCR_ANRESTART);
1698
1699 if ((val & MII_BMCR_ANRESTART) && igb_have_autoneg(core)) {
1700 e1000x_restart_autoneg(core->mac, core->phy, core->autoneg_timer);
1701 }
1702 }
1703
1704 void igb_core_set_link_status(IGBCore *core)
1705 {
1706 NetClientState *nc = qemu_get_queue(core->owner_nic);
1707 uint32_t old_status = core->mac[STATUS];
1708
1709 trace_e1000e_link_status_changed(nc->link_down ? false : true);
1710
1711 if (nc->link_down) {
1712 e1000x_update_regs_on_link_down(core->mac, core->phy);
1713 } else {
1714 if (igb_have_autoneg(core) &&
1715 !(core->phy[MII_BMSR] & MII_BMSR_AN_COMP)) {
1716 e1000x_restart_autoneg(core->mac, core->phy,
1717 core->autoneg_timer);
1718 } else {
1719 e1000x_update_regs_on_link_up(core->mac, core->phy);
1720 igb_start_recv(core);
1721 }
1722 }
1723
1724 if (core->mac[STATUS] != old_status) {
1725 igb_set_interrupt_cause(core, E1000_ICR_LSC);
1726 }
1727 }
1728
1729 static void
1730 igb_set_ctrl(IGBCore *core, int index, uint32_t val)
1731 {
1732 trace_e1000e_core_ctrl_write(index, val);
1733
1734 /* RST is self clearing */
1735 core->mac[CTRL] = val & ~E1000_CTRL_RST;
1736 core->mac[CTRL_DUP] = core->mac[CTRL];
1737
1738 trace_e1000e_link_set_params(
1739 !!(val & E1000_CTRL_ASDE),
1740 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT,
1741 !!(val & E1000_CTRL_FRCSPD),
1742 !!(val & E1000_CTRL_FRCDPX),
1743 !!(val & E1000_CTRL_RFCE),
1744 !!(val & E1000_CTRL_TFCE));
1745
1746 if (val & E1000_CTRL_RST) {
1747 trace_e1000e_core_ctrl_sw_reset();
1748 igb_reset(core, true);
1749 }
1750
1751 if (val & E1000_CTRL_PHY_RST) {
1752 trace_e1000e_core_ctrl_phy_reset();
1753 core->mac[STATUS] |= E1000_STATUS_PHYRA;
1754 }
1755 }
1756
1757 static void
1758 igb_set_rfctl(IGBCore *core, int index, uint32_t val)
1759 {
1760 trace_e1000e_rx_set_rfctl(val);
1761
1762 if (!(val & E1000_RFCTL_ISCSI_DIS)) {
1763 trace_e1000e_wrn_iscsi_filtering_not_supported();
1764 }
1765
1766 if (!(val & E1000_RFCTL_NFSW_DIS)) {
1767 trace_e1000e_wrn_nfsw_filtering_not_supported();
1768 }
1769
1770 if (!(val & E1000_RFCTL_NFSR_DIS)) {
1771 trace_e1000e_wrn_nfsr_filtering_not_supported();
1772 }
1773
1774 core->mac[RFCTL] = val;
1775 }
1776
1777 static void
1778 igb_calc_rxdesclen(IGBCore *core)
1779 {
1780 if (igb_rx_use_legacy_descriptor(core)) {
1781 core->rx_desc_len = sizeof(struct e1000_rx_desc);
1782 } else {
1783 core->rx_desc_len = sizeof(union e1000_adv_rx_desc);
1784 }
1785 trace_e1000e_rx_desc_len(core->rx_desc_len);
1786 }
1787
1788 static void
1789 igb_set_rx_control(IGBCore *core, int index, uint32_t val)
1790 {
1791 core->mac[RCTL] = val;
1792 trace_e1000e_rx_set_rctl(core->mac[RCTL]);
1793
1794 if (val & E1000_RCTL_DTYP_MASK) {
1795 qemu_log_mask(LOG_GUEST_ERROR,
1796 "igb: RCTL.DTYP must be zero for compatibility");
1797 }
1798
1799 if (val & E1000_RCTL_EN) {
1800 igb_calc_rxdesclen(core);
1801 igb_start_recv(core);
1802 }
1803 }
1804
1805 static inline void
1806 igb_clear_ims_bits(IGBCore *core, uint32_t bits)
1807 {
1808 trace_e1000e_irq_clear_ims(bits, core->mac[IMS], core->mac[IMS] & ~bits);
1809 core->mac[IMS] &= ~bits;
1810 }
1811
1812 static inline bool
1813 igb_postpone_interrupt(IGBIntrDelayTimer *timer)
1814 {
1815 if (timer->running) {
1816 trace_e1000e_irq_postponed_by_xitr(timer->delay_reg << 2);
1817
1818 return true;
1819 }
1820
1821 if (timer->core->mac[timer->delay_reg] != 0) {
1822 igb_intrmgr_rearm_timer(timer);
1823 }
1824
1825 return false;
1826 }
1827
1828 static inline bool
1829 igb_eitr_should_postpone(IGBCore *core, int idx)
1830 {
1831 return igb_postpone_interrupt(&core->eitr[idx]);
1832 }
1833
1834 static void igb_send_msix(IGBCore *core)
1835 {
1836 uint32_t causes = core->mac[EICR] & core->mac[EIMS];
1837 uint32_t effective_eiac;
1838 int vector;
1839
1840 for (vector = 0; vector < IGB_INTR_NUM; ++vector) {
1841 if ((causes & BIT(vector)) && !igb_eitr_should_postpone(core, vector)) {
1842
1843 trace_e1000e_irq_msix_notify_vec(vector);
1844 igb_msix_notify(core, vector);
1845
1846 trace_e1000e_irq_icr_clear_eiac(core->mac[EICR], core->mac[EIAC]);
1847 effective_eiac = core->mac[EIAC] & BIT(vector);
1848 core->mac[EICR] &= ~effective_eiac;
1849 }
1850 }
1851 }
1852
1853 static inline void
1854 igb_fix_icr_asserted(IGBCore *core)
1855 {
1856 core->mac[ICR] &= ~E1000_ICR_ASSERTED;
1857 if (core->mac[ICR]) {
1858 core->mac[ICR] |= E1000_ICR_ASSERTED;
1859 }
1860
1861 trace_e1000e_irq_fix_icr_asserted(core->mac[ICR]);
1862 }
1863
1864 static void
1865 igb_update_interrupt_state(IGBCore *core)
1866 {
1867 uint32_t icr;
1868 uint32_t causes;
1869 uint32_t int_alloc;
1870
1871 icr = core->mac[ICR] & core->mac[IMS];
1872
1873 if (msix_enabled(core->owner)) {
1874 if (icr) {
1875 causes = 0;
1876 if (icr & E1000_ICR_DRSTA) {
1877 int_alloc = core->mac[IVAR_MISC] & 0xff;
1878 if (int_alloc & E1000_IVAR_VALID) {
1879 causes |= BIT(int_alloc & 0x1f);
1880 }
1881 }
1882 /* Check if other bits (excluding the TCP Timer) are enabled. */
1883 if (icr & ~E1000_ICR_DRSTA) {
1884 int_alloc = (core->mac[IVAR_MISC] >> 8) & 0xff;
1885 if (int_alloc & E1000_IVAR_VALID) {
1886 causes |= BIT(int_alloc & 0x1f);
1887 }
1888 trace_e1000e_irq_add_msi_other(core->mac[EICR]);
1889 }
1890 core->mac[EICR] |= causes;
1891 }
1892
1893 if ((core->mac[EICR] & core->mac[EIMS])) {
1894 igb_send_msix(core);
1895 }
1896 } else {
1897 igb_fix_icr_asserted(core);
1898
1899 if (icr) {
1900 core->mac[EICR] |= (icr & E1000_ICR_DRSTA) | E1000_EICR_OTHER;
1901 } else {
1902 core->mac[EICR] &= ~E1000_EICR_OTHER;
1903 }
1904
1905 trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS],
1906 core->mac[ICR], core->mac[IMS]);
1907
1908 if (msi_enabled(core->owner)) {
1909 if (icr) {
1910 msi_notify(core->owner, 0);
1911 }
1912 } else {
1913 if (icr) {
1914 igb_raise_legacy_irq(core);
1915 } else {
1916 igb_lower_legacy_irq(core);
1917 }
1918 }
1919 }
1920 }
1921
1922 static void
1923 igb_set_interrupt_cause(IGBCore *core, uint32_t val)
1924 {
1925 trace_e1000e_irq_set_cause_entry(val, core->mac[ICR]);
1926
1927 core->mac[ICR] |= val;
1928
1929 trace_e1000e_irq_set_cause_exit(val, core->mac[ICR]);
1930
1931 igb_update_interrupt_state(core);
1932 }
1933
1934 static void igb_set_eics(IGBCore *core, int index, uint32_t val)
1935 {
1936 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE);
1937
1938 trace_igb_irq_write_eics(val, msix);
1939
1940 core->mac[EICS] |=
1941 val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK);
1942
1943 /*
1944 * TODO: Move to igb_update_interrupt_state if EICS is modified in other
1945 * places.
1946 */
1947 core->mac[EICR] = core->mac[EICS];
1948
1949 igb_update_interrupt_state(core);
1950 }
1951
1952 static void igb_set_eims(IGBCore *core, int index, uint32_t val)
1953 {
1954 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE);
1955
1956 trace_igb_irq_write_eims(val, msix);
1957
1958 core->mac[EIMS] |=
1959 val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK);
1960
1961 igb_update_interrupt_state(core);
1962 }
1963
1964 static void mailbox_interrupt_to_vf(IGBCore *core, uint16_t vfn)
1965 {
1966 uint32_t ent = core->mac[VTIVAR_MISC + vfn];
1967
1968 if ((ent & E1000_IVAR_VALID)) {
1969 core->mac[EICR] |= (ent & 0x3) << (22 - vfn * IGBVF_MSIX_VEC_NUM);
1970 igb_update_interrupt_state(core);
1971 }
1972 }
1973
1974 static void mailbox_interrupt_to_pf(IGBCore *core)
1975 {
1976 igb_set_interrupt_cause(core, E1000_ICR_VMMB);
1977 }
1978
1979 static void igb_set_pfmailbox(IGBCore *core, int index, uint32_t val)
1980 {
1981 uint16_t vfn = index - P2VMAILBOX0;
1982
1983 trace_igb_set_pfmailbox(vfn, val);
1984
1985 if (val & E1000_P2VMAILBOX_STS) {
1986 core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_PFSTS;
1987 mailbox_interrupt_to_vf(core, vfn);
1988 }
1989
1990 if (val & E1000_P2VMAILBOX_ACK) {
1991 core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_PFACK;
1992 mailbox_interrupt_to_vf(core, vfn);
1993 }
1994
1995 /* Buffer Taken by PF (can be set only if the VFU is cleared). */
1996 if (val & E1000_P2VMAILBOX_PFU) {
1997 if (!(core->mac[index] & E1000_P2VMAILBOX_VFU)) {
1998 core->mac[index] |= E1000_P2VMAILBOX_PFU;
1999 core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_PFU;
2000 }
2001 } else {
2002 core->mac[index] &= ~E1000_P2VMAILBOX_PFU;
2003 core->mac[V2PMAILBOX0 + vfn] &= ~E1000_V2PMAILBOX_PFU;
2004 }
2005
2006 if (val & E1000_P2VMAILBOX_RVFU) {
2007 core->mac[V2PMAILBOX0 + vfn] &= ~E1000_V2PMAILBOX_VFU;
2008 core->mac[MBVFICR] &= ~((E1000_MBVFICR_VFACK_VF1 << vfn) |
2009 (E1000_MBVFICR_VFREQ_VF1 << vfn));
2010 }
2011 }
2012
2013 static void igb_set_vfmailbox(IGBCore *core, int index, uint32_t val)
2014 {
2015 uint16_t vfn = index - V2PMAILBOX0;
2016
2017 trace_igb_set_vfmailbox(vfn, val);
2018
2019 if (val & E1000_V2PMAILBOX_REQ) {
2020 core->mac[MBVFICR] |= E1000_MBVFICR_VFREQ_VF1 << vfn;
2021 mailbox_interrupt_to_pf(core);
2022 }
2023
2024 if (val & E1000_V2PMAILBOX_ACK) {
2025 core->mac[MBVFICR] |= E1000_MBVFICR_VFACK_VF1 << vfn;
2026 mailbox_interrupt_to_pf(core);
2027 }
2028
2029 /* Buffer Taken by VF (can be set only if the PFU is cleared). */
2030 if (val & E1000_V2PMAILBOX_VFU) {
2031 if (!(core->mac[index] & E1000_V2PMAILBOX_PFU)) {
2032 core->mac[index] |= E1000_V2PMAILBOX_VFU;
2033 core->mac[P2VMAILBOX0 + vfn] |= E1000_P2VMAILBOX_VFU;
2034 }
2035 } else {
2036 core->mac[index] &= ~E1000_V2PMAILBOX_VFU;
2037 core->mac[P2VMAILBOX0 + vfn] &= ~E1000_P2VMAILBOX_VFU;
2038 }
2039 }
2040
2041 static void igb_vf_reset(IGBCore *core, uint16_t vfn)
2042 {
2043 uint16_t qn0 = vfn;
2044 uint16_t qn1 = vfn + IGB_NUM_VM_POOLS;
2045
2046 /* disable Rx and Tx for the VF*/
2047 core->mac[RXDCTL0 + (qn0 * 16)] &= ~E1000_RXDCTL_QUEUE_ENABLE;
2048 core->mac[RXDCTL0 + (qn1 * 16)] &= ~E1000_RXDCTL_QUEUE_ENABLE;
2049 core->mac[TXDCTL0 + (qn0 * 16)] &= ~E1000_TXDCTL_QUEUE_ENABLE;
2050 core->mac[TXDCTL0 + (qn1 * 16)] &= ~E1000_TXDCTL_QUEUE_ENABLE;
2051 core->mac[VFRE] &= ~BIT(vfn);
2052 core->mac[VFTE] &= ~BIT(vfn);
2053 /* indicate VF reset to PF */
2054 core->mac[VFLRE] |= BIT(vfn);
2055 /* VFLRE and mailbox use the same interrupt cause */
2056 mailbox_interrupt_to_pf(core);
2057 }
2058
2059 static void igb_w1c(IGBCore *core, int index, uint32_t val)
2060 {
2061 core->mac[index] &= ~val;
2062 }
2063
2064 static void igb_set_eimc(IGBCore *core, int index, uint32_t val)
2065 {
2066 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE);
2067
2068 /* Interrupts are disabled via a write to EIMC and reflected in EIMS. */
2069 core->mac[EIMS] &=
2070 ~(val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK));
2071
2072 trace_igb_irq_write_eimc(val, core->mac[EIMS], msix);
2073 igb_update_interrupt_state(core);
2074 }
2075
2076 static void igb_set_eiac(IGBCore *core, int index, uint32_t val)
2077 {
2078 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE);
2079
2080 if (msix) {
2081 trace_igb_irq_write_eiac(val);
2082
2083 /*
2084 * TODO: When using IOV, the bits that correspond to MSI-X vectors
2085 * that are assigned to a VF are read-only.
2086 */
2087 core->mac[EIAC] |= (val & E1000_EICR_MSIX_MASK);
2088 }
2089 }
2090
2091 static void igb_set_eiam(IGBCore *core, int index, uint32_t val)
2092 {
2093 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE);
2094
2095 /*
2096 * TODO: When using IOV, the bits that correspond to MSI-X vectors that
2097 * are assigned to a VF are read-only.
2098 */
2099 core->mac[EIAM] |=
2100 ~(val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK));
2101
2102 trace_igb_irq_write_eiam(val, msix);
2103 }
2104
2105 static void igb_set_eicr(IGBCore *core, int index, uint32_t val)
2106 {
2107 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE);
2108
2109 /*
2110 * TODO: In IOV mode, only bit zero of this vector is available for the PF
2111 * function.
2112 */
2113 core->mac[EICR] &=
2114 ~(val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK));
2115
2116 trace_igb_irq_write_eicr(val, msix);
2117 igb_update_interrupt_state(core);
2118 }
2119
2120 static void igb_set_vtctrl(IGBCore *core, int index, uint32_t val)
2121 {
2122 uint16_t vfn;
2123
2124 if (val & E1000_CTRL_RST) {
2125 vfn = (index - PVTCTRL0) / 0x40;
2126 igb_vf_reset(core, vfn);
2127 }
2128 }
2129
2130 static void igb_set_vteics(IGBCore *core, int index, uint32_t val)
2131 {
2132 uint16_t vfn = (index - PVTEICS0) / 0x40;
2133
2134 core->mac[index] = val;
2135 igb_set_eics(core, EICS, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM));
2136 }
2137
2138 static void igb_set_vteims(IGBCore *core, int index, uint32_t val)
2139 {
2140 uint16_t vfn = (index - PVTEIMS0) / 0x40;
2141
2142 core->mac[index] = val;
2143 igb_set_eims(core, EIMS, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM));
2144 }
2145
2146 static void igb_set_vteimc(IGBCore *core, int index, uint32_t val)
2147 {
2148 uint16_t vfn = (index - PVTEIMC0) / 0x40;
2149
2150 core->mac[index] = val;
2151 igb_set_eimc(core, EIMC, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM));
2152 }
2153
2154 static void igb_set_vteiac(IGBCore *core, int index, uint32_t val)
2155 {
2156 uint16_t vfn = (index - PVTEIAC0) / 0x40;
2157
2158 core->mac[index] = val;
2159 igb_set_eiac(core, EIAC, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM));
2160 }
2161
2162 static void igb_set_vteiam(IGBCore *core, int index, uint32_t val)
2163 {
2164 uint16_t vfn = (index - PVTEIAM0) / 0x40;
2165
2166 core->mac[index] = val;
2167 igb_set_eiam(core, EIAM, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM));
2168 }
2169
2170 static void igb_set_vteicr(IGBCore *core, int index, uint32_t val)
2171 {
2172 uint16_t vfn = (index - PVTEICR0) / 0x40;
2173
2174 core->mac[index] = val;
2175 igb_set_eicr(core, EICR, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM));
2176 }
2177
2178 static void igb_set_vtivar(IGBCore *core, int index, uint32_t val)
2179 {
2180 uint16_t vfn = (index - VTIVAR);
2181 uint16_t qn = vfn;
2182 uint8_t ent;
2183 int n;
2184
2185 core->mac[index] = val;
2186
2187 /* Get assigned vector associated with queue Rx#0. */
2188 if ((val & E1000_IVAR_VALID)) {
2189 n = igb_ivar_entry_rx(qn);
2190 ent = E1000_IVAR_VALID | (24 - vfn * IGBVF_MSIX_VEC_NUM - (2 - (val & 0x7)));
2191 core->mac[IVAR0 + n / 4] |= ent << 8 * (n % 4);
2192 }
2193
2194 /* Get assigned vector associated with queue Tx#0 */
2195 ent = val >> 8;
2196 if ((ent & E1000_IVAR_VALID)) {
2197 n = igb_ivar_entry_tx(qn);
2198 ent = E1000_IVAR_VALID | (24 - vfn * IGBVF_MSIX_VEC_NUM - (2 - (ent & 0x7)));
2199 core->mac[IVAR0 + n / 4] |= ent << 8 * (n % 4);
2200 }
2201
2202 /*
2203 * Ignoring assigned vectors associated with queues Rx#1 and Tx#1 for now.
2204 */
2205 }
2206
2207 static inline void
2208 igb_autoneg_timer(void *opaque)
2209 {
2210 IGBCore *core = opaque;
2211 if (!qemu_get_queue(core->owner_nic)->link_down) {
2212 e1000x_update_regs_on_autoneg_done(core->mac, core->phy);
2213 igb_start_recv(core);
2214
2215 igb_update_flowctl_status(core);
2216 /* signal link status change to the guest */
2217 igb_set_interrupt_cause(core, E1000_ICR_LSC);
2218 }
2219 }
2220
2221 static inline uint16_t
2222 igb_get_reg_index_with_offset(const uint16_t *mac_reg_access, hwaddr addr)
2223 {
2224 uint16_t index = (addr & 0x1ffff) >> 2;
2225 return index + (mac_reg_access[index] & 0xfffe);
2226 }
2227
2228 static const char igb_phy_regcap[MAX_PHY_REG_ADDRESS + 1] = {
2229 [MII_BMCR] = PHY_RW,
2230 [MII_BMSR] = PHY_R,
2231 [MII_PHYID1] = PHY_R,
2232 [MII_PHYID2] = PHY_R,
2233 [MII_ANAR] = PHY_RW,
2234 [MII_ANLPAR] = PHY_R,
2235 [MII_ANER] = PHY_R,
2236 [MII_ANNP] = PHY_RW,
2237 [MII_ANLPRNP] = PHY_R,
2238 [MII_CTRL1000] = PHY_RW,
2239 [MII_STAT1000] = PHY_R,
2240 [MII_EXTSTAT] = PHY_R,
2241
2242 [IGP01E1000_PHY_PORT_CONFIG] = PHY_RW,
2243 [IGP01E1000_PHY_PORT_STATUS] = PHY_R,
2244 [IGP01E1000_PHY_PORT_CTRL] = PHY_RW,
2245 [IGP01E1000_PHY_LINK_HEALTH] = PHY_R,
2246 [IGP02E1000_PHY_POWER_MGMT] = PHY_RW,
2247 [IGP01E1000_PHY_PAGE_SELECT] = PHY_W
2248 };
2249
2250 static void
2251 igb_phy_reg_write(IGBCore *core, uint32_t addr, uint16_t data)
2252 {
2253 assert(addr <= MAX_PHY_REG_ADDRESS);
2254
2255 if (addr == MII_BMCR) {
2256 igb_set_phy_ctrl(core, data);
2257 } else {
2258 core->phy[addr] = data;
2259 }
2260 }
2261
2262 static void
2263 igb_set_mdic(IGBCore *core, int index, uint32_t val)
2264 {
2265 uint32_t data = val & E1000_MDIC_DATA_MASK;
2266 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
2267
2268 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) { /* phy # */
2269 val = core->mac[MDIC] | E1000_MDIC_ERROR;
2270 } else if (val & E1000_MDIC_OP_READ) {
2271 if (!(igb_phy_regcap[addr] & PHY_R)) {
2272 trace_igb_core_mdic_read_unhandled(addr);
2273 val |= E1000_MDIC_ERROR;
2274 } else {
2275 val = (val ^ data) | core->phy[addr];
2276 trace_igb_core_mdic_read(addr, val);
2277 }
2278 } else if (val & E1000_MDIC_OP_WRITE) {
2279 if (!(igb_phy_regcap[addr] & PHY_W)) {
2280 trace_igb_core_mdic_write_unhandled(addr);
2281 val |= E1000_MDIC_ERROR;
2282 } else {
2283 trace_igb_core_mdic_write(addr, data);
2284 igb_phy_reg_write(core, addr, data);
2285 }
2286 }
2287 core->mac[MDIC] = val | E1000_MDIC_READY;
2288
2289 if (val & E1000_MDIC_INT_EN) {
2290 igb_set_interrupt_cause(core, E1000_ICR_MDAC);
2291 }
2292 }
2293
2294 static void
2295 igb_set_rdt(IGBCore *core, int index, uint32_t val)
2296 {
2297 core->mac[index] = val & 0xffff;
2298 trace_e1000e_rx_set_rdt(igb_mq_queue_idx(RDT0, index), val);
2299 igb_start_recv(core);
2300 }
2301
2302 static void
2303 igb_set_status(IGBCore *core, int index, uint32_t val)
2304 {
2305 if ((val & E1000_STATUS_PHYRA) == 0) {
2306 core->mac[index] &= ~E1000_STATUS_PHYRA;
2307 }
2308 }
2309
2310 static void
2311 igb_set_ctrlext(IGBCore *core, int index, uint32_t val)
2312 {
2313 trace_igb_link_set_ext_params(!!(val & E1000_CTRL_EXT_ASDCHK),
2314 !!(val & E1000_CTRL_EXT_SPD_BYPS),
2315 !!(val & E1000_CTRL_EXT_PFRSTD));
2316
2317 /* Zero self-clearing bits */
2318 val &= ~(E1000_CTRL_EXT_ASDCHK | E1000_CTRL_EXT_EE_RST);
2319 core->mac[CTRL_EXT] = val;
2320
2321 if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_PFRSTD) {
2322 for (int vfn = 0; vfn < IGB_MAX_VF_FUNCTIONS; vfn++) {
2323 core->mac[V2PMAILBOX0 + vfn] &= ~E1000_V2PMAILBOX_RSTI;
2324 core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_RSTD;
2325 }
2326 }
2327 }
2328
2329 static void
2330 igb_set_pbaclr(IGBCore *core, int index, uint32_t val)
2331 {
2332 int i;
2333
2334 core->mac[PBACLR] = val & E1000_PBACLR_VALID_MASK;
2335
2336 if (!msix_enabled(core->owner)) {
2337 return;
2338 }
2339
2340 for (i = 0; i < IGB_INTR_NUM; i++) {
2341 if (core->mac[PBACLR] & BIT(i)) {
2342 msix_clr_pending(core->owner, i);
2343 }
2344 }
2345 }
2346
2347 static void
2348 igb_set_fcrth(IGBCore *core, int index, uint32_t val)
2349 {
2350 core->mac[FCRTH] = val & 0xFFF8;
2351 }
2352
2353 static void
2354 igb_set_fcrtl(IGBCore *core, int index, uint32_t val)
2355 {
2356 core->mac[FCRTL] = val & 0x8000FFF8;
2357 }
2358
2359 #define IGB_LOW_BITS_SET_FUNC(num) \
2360 static void \
2361 igb_set_##num##bit(IGBCore *core, int index, uint32_t val) \
2362 { \
2363 core->mac[index] = val & (BIT(num) - 1); \
2364 }
2365
2366 IGB_LOW_BITS_SET_FUNC(4)
2367 IGB_LOW_BITS_SET_FUNC(13)
2368 IGB_LOW_BITS_SET_FUNC(16)
2369
2370 static void
2371 igb_set_dlen(IGBCore *core, int index, uint32_t val)
2372 {
2373 core->mac[index] = val & 0xffff0;
2374 }
2375
2376 static void
2377 igb_set_dbal(IGBCore *core, int index, uint32_t val)
2378 {
2379 core->mac[index] = val & E1000_XDBAL_MASK;
2380 }
2381
2382 static void
2383 igb_set_tdt(IGBCore *core, int index, uint32_t val)
2384 {
2385 IGB_TxRing txr;
2386 int qn = igb_mq_queue_idx(TDT0, index);
2387
2388 core->mac[index] = val & 0xffff;
2389
2390 igb_tx_ring_init(core, &txr, qn);
2391 igb_start_xmit(core, &txr);
2392 }
2393
2394 static void
2395 igb_set_ics(IGBCore *core, int index, uint32_t val)
2396 {
2397 trace_e1000e_irq_write_ics(val);
2398 igb_set_interrupt_cause(core, val);
2399 }
2400
2401 static void
2402 igb_set_imc(IGBCore *core, int index, uint32_t val)
2403 {
2404 trace_e1000e_irq_ims_clear_set_imc(val);
2405 igb_clear_ims_bits(core, val);
2406 igb_update_interrupt_state(core);
2407 }
2408
2409 static void
2410 igb_set_ims(IGBCore *core, int index, uint32_t val)
2411 {
2412 uint32_t valid_val = val & 0x77D4FBFD;
2413
2414 trace_e1000e_irq_set_ims(val, core->mac[IMS], core->mac[IMS] | valid_val);
2415 core->mac[IMS] |= valid_val;
2416 igb_update_interrupt_state(core);
2417 }
2418
2419 static void igb_commit_icr(IGBCore *core)
2420 {
2421 /*
2422 * If GPIE.NSICR = 0, then the clear of IMS will occur only if at
2423 * least one bit is set in the IMS and there is a true interrupt as
2424 * reflected in ICR.INTA.
2425 */
2426 if ((core->mac[GPIE] & E1000_GPIE_NSICR) ||
2427 (core->mac[IMS] && (core->mac[ICR] & E1000_ICR_INT_ASSERTED))) {
2428 igb_clear_ims_bits(core, core->mac[IAM]);
2429 }
2430
2431 igb_update_interrupt_state(core);
2432 }
2433
2434 static void igb_set_icr(IGBCore *core, int index, uint32_t val)
2435 {
2436 uint32_t icr = core->mac[ICR] & ~val;
2437
2438 trace_igb_irq_icr_write(val, core->mac[ICR], icr);
2439 core->mac[ICR] = icr;
2440 igb_commit_icr(core);
2441 }
2442
2443 static uint32_t
2444 igb_mac_readreg(IGBCore *core, int index)
2445 {
2446 return core->mac[index];
2447 }
2448
2449 static uint32_t
2450 igb_mac_ics_read(IGBCore *core, int index)
2451 {
2452 trace_e1000e_irq_read_ics(core->mac[ICS]);
2453 return core->mac[ICS];
2454 }
2455
2456 static uint32_t
2457 igb_mac_ims_read(IGBCore *core, int index)
2458 {
2459 trace_e1000e_irq_read_ims(core->mac[IMS]);
2460 return core->mac[IMS];
2461 }
2462
2463 static uint32_t
2464 igb_mac_swsm_read(IGBCore *core, int index)
2465 {
2466 uint32_t val = core->mac[SWSM];
2467 core->mac[SWSM] = val | E1000_SWSM_SMBI;
2468 return val;
2469 }
2470
2471 static uint32_t
2472 igb_mac_eitr_read(IGBCore *core, int index)
2473 {
2474 return core->eitr_guest_value[index - EITR0];
2475 }
2476
2477 static uint32_t igb_mac_vfmailbox_read(IGBCore *core, int index)
2478 {
2479 uint32_t val = core->mac[index];
2480
2481 core->mac[index] &= ~(E1000_V2PMAILBOX_PFSTS | E1000_V2PMAILBOX_PFACK |
2482 E1000_V2PMAILBOX_RSTD);
2483
2484 return val;
2485 }
2486
2487 static uint32_t
2488 igb_mac_icr_read(IGBCore *core, int index)
2489 {
2490 uint32_t ret = core->mac[ICR];
2491 trace_e1000e_irq_icr_read_entry(ret);
2492
2493 if (core->mac[GPIE] & E1000_GPIE_NSICR) {
2494 trace_igb_irq_icr_clear_gpie_nsicr();
2495 core->mac[ICR] = 0;
2496 } else if (core->mac[IMS] == 0) {
2497 trace_e1000e_irq_icr_clear_zero_ims();
2498 core->mac[ICR] = 0;
2499 } else if (!msix_enabled(core->owner)) {
2500 trace_e1000e_irq_icr_clear_nonmsix_icr_read();
2501 core->mac[ICR] = 0;
2502 }
2503
2504 trace_e1000e_irq_icr_read_exit(core->mac[ICR]);
2505 igb_commit_icr(core);
2506 return ret;
2507 }
2508
2509 static uint32_t
2510 igb_mac_read_clr4(IGBCore *core, int index)
2511 {
2512 uint32_t ret = core->mac[index];
2513
2514 core->mac[index] = 0;
2515 return ret;
2516 }
2517
2518 static uint32_t
2519 igb_mac_read_clr8(IGBCore *core, int index)
2520 {
2521 uint32_t ret = core->mac[index];
2522
2523 core->mac[index] = 0;
2524 core->mac[index - 1] = 0;
2525 return ret;
2526 }
2527
2528 static uint32_t
2529 igb_get_ctrl(IGBCore *core, int index)
2530 {
2531 uint32_t val = core->mac[CTRL];
2532
2533 trace_e1000e_link_read_params(
2534 !!(val & E1000_CTRL_ASDE),
2535 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT,
2536 !!(val & E1000_CTRL_FRCSPD),
2537 !!(val & E1000_CTRL_FRCDPX),
2538 !!(val & E1000_CTRL_RFCE),
2539 !!(val & E1000_CTRL_TFCE));
2540
2541 return val;
2542 }
2543
2544 static uint32_t igb_get_status(IGBCore *core, int index)
2545 {
2546 uint32_t res = core->mac[STATUS];
2547 uint16_t num_vfs = pcie_sriov_num_vfs(core->owner);
2548
2549 if (core->mac[CTRL] & E1000_CTRL_FRCDPX) {
2550 res |= (core->mac[CTRL] & E1000_CTRL_FD) ? E1000_STATUS_FD : 0;
2551 } else {
2552 res |= E1000_STATUS_FD;
2553 }
2554
2555 if ((core->mac[CTRL] & E1000_CTRL_FRCSPD) ||
2556 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_SPD_BYPS)) {
2557 switch (core->mac[CTRL] & E1000_CTRL_SPD_SEL) {
2558 case E1000_CTRL_SPD_10:
2559 res |= E1000_STATUS_SPEED_10;
2560 break;
2561 case E1000_CTRL_SPD_100:
2562 res |= E1000_STATUS_SPEED_100;
2563 break;
2564 case E1000_CTRL_SPD_1000:
2565 default:
2566 res |= E1000_STATUS_SPEED_1000;
2567 break;
2568 }
2569 } else {
2570 res |= E1000_STATUS_SPEED_1000;
2571 }
2572
2573 if (num_vfs) {
2574 res |= num_vfs << E1000_STATUS_NUM_VFS_SHIFT;
2575 res |= E1000_STATUS_IOV_MODE;
2576 }
2577
2578 /*
2579 * Windows driver 12.18.9.23 resets if E1000_STATUS_GIO_MASTER_ENABLE is
2580 * left set after E1000_CTRL_LRST is set.
2581 */
2582 if (!(core->mac[CTRL] & E1000_CTRL_GIO_MASTER_DISABLE) &&
2583 !(core->mac[CTRL] & E1000_CTRL_LRST)) {
2584 res |= E1000_STATUS_GIO_MASTER_ENABLE;
2585 }
2586
2587 return res;
2588 }
2589
2590 static void
2591 igb_mac_writereg(IGBCore *core, int index, uint32_t val)
2592 {
2593 core->mac[index] = val;
2594 }
2595
2596 static void
2597 igb_mac_setmacaddr(IGBCore *core, int index, uint32_t val)
2598 {
2599 uint32_t macaddr[2];
2600
2601 core->mac[index] = val;
2602
2603 macaddr[0] = cpu_to_le32(core->mac[RA]);
2604 macaddr[1] = cpu_to_le32(core->mac[RA + 1]);
2605 qemu_format_nic_info_str(qemu_get_queue(core->owner_nic),
2606 (uint8_t *) macaddr);
2607
2608 trace_e1000e_mac_set_sw(MAC_ARG(macaddr));
2609 }
2610
2611 static void
2612 igb_set_eecd(IGBCore *core, int index, uint32_t val)
2613 {
2614 static const uint32_t ro_bits = E1000_EECD_PRES |
2615 E1000_EECD_AUTO_RD |
2616 E1000_EECD_SIZE_EX_MASK;
2617
2618 core->mac[EECD] = (core->mac[EECD] & ro_bits) | (val & ~ro_bits);
2619 }
2620
2621 static void
2622 igb_set_eerd(IGBCore *core, int index, uint32_t val)
2623 {
2624 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK;
2625 uint32_t flags = 0;
2626 uint32_t data = 0;
2627
2628 if ((addr < IGB_EEPROM_SIZE) && (val & E1000_EERW_START)) {
2629 data = core->eeprom[addr];
2630 flags = E1000_EERW_DONE;
2631 }
2632
2633 core->mac[EERD] = flags |
2634 (addr << E1000_EERW_ADDR_SHIFT) |
2635 (data << E1000_EERW_DATA_SHIFT);
2636 }
2637
2638 static void
2639 igb_set_eitr(IGBCore *core, int index, uint32_t val)
2640 {
2641 uint32_t eitr_num = index - EITR0;
2642
2643 trace_igb_irq_eitr_set(eitr_num, val);
2644
2645 core->eitr_guest_value[eitr_num] = val & ~E1000_EITR_CNT_IGNR;
2646 core->mac[index] = val & 0x7FFE;
2647 }
2648
2649 static void
2650 igb_update_rx_offloads(IGBCore *core)
2651 {
2652 int cso_state = igb_rx_l4_cso_enabled(core);
2653
2654 trace_e1000e_rx_set_cso(cso_state);
2655
2656 if (core->has_vnet) {
2657 qemu_set_offload(qemu_get_queue(core->owner_nic)->peer,
2658 cso_state, 0, 0, 0, 0);
2659 }
2660 }
2661
2662 static void
2663 igb_set_rxcsum(IGBCore *core, int index, uint32_t val)
2664 {
2665 core->mac[RXCSUM] = val;
2666 igb_update_rx_offloads(core);
2667 }
2668
2669 static void
2670 igb_set_gcr(IGBCore *core, int index, uint32_t val)
2671 {
2672 uint32_t ro_bits = core->mac[GCR] & E1000_GCR_RO_BITS;
2673 core->mac[GCR] = (val & ~E1000_GCR_RO_BITS) | ro_bits;
2674 }
2675
2676 static uint32_t igb_get_systiml(IGBCore *core, int index)
2677 {
2678 e1000x_timestamp(core->mac, core->timadj, SYSTIML, SYSTIMH);
2679 return core->mac[SYSTIML];
2680 }
2681
2682 static uint32_t igb_get_rxsatrh(IGBCore *core, int index)
2683 {
2684 core->mac[TSYNCRXCTL] &= ~E1000_TSYNCRXCTL_VALID;
2685 return core->mac[RXSATRH];
2686 }
2687
2688 static uint32_t igb_get_txstmph(IGBCore *core, int index)
2689 {
2690 core->mac[TSYNCTXCTL] &= ~E1000_TSYNCTXCTL_VALID;
2691 return core->mac[TXSTMPH];
2692 }
2693
2694 static void igb_set_timinca(IGBCore *core, int index, uint32_t val)
2695 {
2696 e1000x_set_timinca(core->mac, &core->timadj, val);
2697 }
2698
2699 static void igb_set_timadjh(IGBCore *core, int index, uint32_t val)
2700 {
2701 core->mac[TIMADJH] = val;
2702 core->timadj += core->mac[TIMADJL] | ((int64_t)core->mac[TIMADJH] << 32);
2703 }
2704
2705 #define igb_getreg(x) [x] = igb_mac_readreg
2706 typedef uint32_t (*readops)(IGBCore *, int);
2707 static const readops igb_macreg_readops[] = {
2708 igb_getreg(WUFC),
2709 igb_getreg(MANC),
2710 igb_getreg(TOTL),
2711 igb_getreg(RDT0),
2712 igb_getreg(RDT1),
2713 igb_getreg(RDT2),
2714 igb_getreg(RDT3),
2715 igb_getreg(RDT4),
2716 igb_getreg(RDT5),
2717 igb_getreg(RDT6),
2718 igb_getreg(RDT7),
2719 igb_getreg(RDT8),
2720 igb_getreg(RDT9),
2721 igb_getreg(RDT10),
2722 igb_getreg(RDT11),
2723 igb_getreg(RDT12),
2724 igb_getreg(RDT13),
2725 igb_getreg(RDT14),
2726 igb_getreg(RDT15),
2727 igb_getreg(RDBAH0),
2728 igb_getreg(RDBAH1),
2729 igb_getreg(RDBAH2),
2730 igb_getreg(RDBAH3),
2731 igb_getreg(RDBAH4),
2732 igb_getreg(RDBAH5),
2733 igb_getreg(RDBAH6),
2734 igb_getreg(RDBAH7),
2735 igb_getreg(RDBAH8),
2736 igb_getreg(RDBAH9),
2737 igb_getreg(RDBAH10),
2738 igb_getreg(RDBAH11),
2739 igb_getreg(RDBAH12),
2740 igb_getreg(RDBAH13),
2741 igb_getreg(RDBAH14),
2742 igb_getreg(RDBAH15),
2743 igb_getreg(TDBAL0),
2744 igb_getreg(TDBAL1),
2745 igb_getreg(TDBAL2),
2746 igb_getreg(TDBAL3),
2747 igb_getreg(TDBAL4),
2748 igb_getreg(TDBAL5),
2749 igb_getreg(TDBAL6),
2750 igb_getreg(TDBAL7),
2751 igb_getreg(TDBAL8),
2752 igb_getreg(TDBAL9),
2753 igb_getreg(TDBAL10),
2754 igb_getreg(TDBAL11),
2755 igb_getreg(TDBAL12),
2756 igb_getreg(TDBAL13),
2757 igb_getreg(TDBAL14),
2758 igb_getreg(TDBAL15),
2759 igb_getreg(RDLEN0),
2760 igb_getreg(RDLEN1),
2761 igb_getreg(RDLEN2),
2762 igb_getreg(RDLEN3),
2763 igb_getreg(RDLEN4),
2764 igb_getreg(RDLEN5),
2765 igb_getreg(RDLEN6),
2766 igb_getreg(RDLEN7),
2767 igb_getreg(RDLEN8),
2768 igb_getreg(RDLEN9),
2769 igb_getreg(RDLEN10),
2770 igb_getreg(RDLEN11),
2771 igb_getreg(RDLEN12),
2772 igb_getreg(RDLEN13),
2773 igb_getreg(RDLEN14),
2774 igb_getreg(RDLEN15),
2775 igb_getreg(SRRCTL0),
2776 igb_getreg(SRRCTL1),
2777 igb_getreg(SRRCTL2),
2778 igb_getreg(SRRCTL3),
2779 igb_getreg(SRRCTL4),
2780 igb_getreg(SRRCTL5),
2781 igb_getreg(SRRCTL6),
2782 igb_getreg(SRRCTL7),
2783 igb_getreg(SRRCTL8),
2784 igb_getreg(SRRCTL9),
2785 igb_getreg(SRRCTL10),
2786 igb_getreg(SRRCTL11),
2787 igb_getreg(SRRCTL12),
2788 igb_getreg(SRRCTL13),
2789 igb_getreg(SRRCTL14),
2790 igb_getreg(SRRCTL15),
2791 igb_getreg(LATECOL),
2792 igb_getreg(XONTXC),
2793 igb_getreg(TDFH),
2794 igb_getreg(TDFT),
2795 igb_getreg(TDFHS),
2796 igb_getreg(TDFTS),
2797 igb_getreg(TDFPC),
2798 igb_getreg(WUS),
2799 igb_getreg(RDFH),
2800 igb_getreg(RDFT),
2801 igb_getreg(RDFHS),
2802 igb_getreg(RDFTS),
2803 igb_getreg(RDFPC),
2804 igb_getreg(GORCL),
2805 igb_getreg(MGTPRC),
2806 igb_getreg(EERD),
2807 igb_getreg(EIAC),
2808 igb_getreg(MANC2H),
2809 igb_getreg(RXCSUM),
2810 igb_getreg(GSCL_3),
2811 igb_getreg(GSCN_2),
2812 igb_getreg(FCAH),
2813 igb_getreg(FCRTH),
2814 igb_getreg(FLOP),
2815 igb_getreg(RXSTMPH),
2816 igb_getreg(TXSTMPL),
2817 igb_getreg(TIMADJL),
2818 igb_getreg(RDH0),
2819 igb_getreg(RDH1),
2820 igb_getreg(RDH2),
2821 igb_getreg(RDH3),
2822 igb_getreg(RDH4),
2823 igb_getreg(RDH5),
2824 igb_getreg(RDH6),
2825 igb_getreg(RDH7),
2826 igb_getreg(RDH8),
2827 igb_getreg(RDH9),
2828 igb_getreg(RDH10),
2829 igb_getreg(RDH11),
2830 igb_getreg(RDH12),
2831 igb_getreg(RDH13),
2832 igb_getreg(RDH14),
2833 igb_getreg(RDH15),
2834 igb_getreg(TDT0),
2835 igb_getreg(TDT1),
2836 igb_getreg(TDT2),
2837 igb_getreg(TDT3),
2838 igb_getreg(TDT4),
2839 igb_getreg(TDT5),
2840 igb_getreg(TDT6),
2841 igb_getreg(TDT7),
2842 igb_getreg(TDT8),
2843 igb_getreg(TDT9),
2844 igb_getreg(TDT10),
2845 igb_getreg(TDT11),
2846 igb_getreg(TDT12),
2847 igb_getreg(TDT13),
2848 igb_getreg(TDT14),
2849 igb_getreg(TDT15),
2850 igb_getreg(TNCRS),
2851 igb_getreg(RJC),
2852 igb_getreg(IAM),
2853 igb_getreg(GSCL_2),
2854 igb_getreg(TIPG),
2855 igb_getreg(FLMNGCTL),
2856 igb_getreg(FLMNGCNT),
2857 igb_getreg(TSYNCTXCTL),
2858 igb_getreg(EEMNGDATA),
2859 igb_getreg(CTRL_EXT),
2860 igb_getreg(SYSTIMH),
2861 igb_getreg(EEMNGCTL),
2862 igb_getreg(FLMNGDATA),
2863 igb_getreg(TSYNCRXCTL),
2864 igb_getreg(LEDCTL),
2865 igb_getreg(TCTL),
2866 igb_getreg(TCTL_EXT),
2867 igb_getreg(DTXCTL),
2868 igb_getreg(RXPBS),
2869 igb_getreg(TDH0),
2870 igb_getreg(TDH1),
2871 igb_getreg(TDH2),
2872 igb_getreg(TDH3),
2873 igb_getreg(TDH4),
2874 igb_getreg(TDH5),
2875 igb_getreg(TDH6),
2876 igb_getreg(TDH7),
2877 igb_getreg(TDH8),
2878 igb_getreg(TDH9),
2879 igb_getreg(TDH10),
2880 igb_getreg(TDH11),
2881 igb_getreg(TDH12),
2882 igb_getreg(TDH13),
2883 igb_getreg(TDH14),
2884 igb_getreg(TDH15),
2885 igb_getreg(ECOL),
2886 igb_getreg(DC),
2887 igb_getreg(RLEC),
2888 igb_getreg(XOFFTXC),
2889 igb_getreg(RFC),
2890 igb_getreg(RNBC),
2891 igb_getreg(MGTPTC),
2892 igb_getreg(TIMINCA),
2893 igb_getreg(FACTPS),
2894 igb_getreg(GSCL_1),
2895 igb_getreg(GSCN_0),
2896 igb_getreg(PBACLR),
2897 igb_getreg(FCTTV),
2898 igb_getreg(RXSATRL),
2899 igb_getreg(TORL),
2900 igb_getreg(TDLEN0),
2901 igb_getreg(TDLEN1),
2902 igb_getreg(TDLEN2),
2903 igb_getreg(TDLEN3),
2904 igb_getreg(TDLEN4),
2905 igb_getreg(TDLEN5),
2906 igb_getreg(TDLEN6),
2907 igb_getreg(TDLEN7),
2908 igb_getreg(TDLEN8),
2909 igb_getreg(TDLEN9),
2910 igb_getreg(TDLEN10),
2911 igb_getreg(TDLEN11),
2912 igb_getreg(TDLEN12),
2913 igb_getreg(TDLEN13),
2914 igb_getreg(TDLEN14),
2915 igb_getreg(TDLEN15),
2916 igb_getreg(MCC),
2917 igb_getreg(WUC),
2918 igb_getreg(EECD),
2919 igb_getreg(FCRTV),
2920 igb_getreg(TXDCTL0),
2921 igb_getreg(TXDCTL1),
2922 igb_getreg(TXDCTL2),
2923 igb_getreg(TXDCTL3),
2924 igb_getreg(TXDCTL4),
2925 igb_getreg(TXDCTL5),
2926 igb_getreg(TXDCTL6),
2927 igb_getreg(TXDCTL7),
2928 igb_getreg(TXDCTL8),
2929 igb_getreg(TXDCTL9),
2930 igb_getreg(TXDCTL10),
2931 igb_getreg(TXDCTL11),
2932 igb_getreg(TXDCTL12),
2933 igb_getreg(TXDCTL13),
2934 igb_getreg(TXDCTL14),
2935 igb_getreg(TXDCTL15),
2936 igb_getreg(TXCTL0),
2937 igb_getreg(TXCTL1),
2938 igb_getreg(TXCTL2),
2939 igb_getreg(TXCTL3),
2940 igb_getreg(TXCTL4),
2941 igb_getreg(TXCTL5),
2942 igb_getreg(TXCTL6),
2943 igb_getreg(TXCTL7),
2944 igb_getreg(TXCTL8),
2945 igb_getreg(TXCTL9),
2946 igb_getreg(TXCTL10),
2947 igb_getreg(TXCTL11),
2948 igb_getreg(TXCTL12),
2949 igb_getreg(TXCTL13),
2950 igb_getreg(TXCTL14),
2951 igb_getreg(TXCTL15),
2952 igb_getreg(TDWBAL0),
2953 igb_getreg(TDWBAL1),
2954 igb_getreg(TDWBAL2),
2955 igb_getreg(TDWBAL3),
2956 igb_getreg(TDWBAL4),
2957 igb_getreg(TDWBAL5),
2958 igb_getreg(TDWBAL6),
2959 igb_getreg(TDWBAL7),
2960 igb_getreg(TDWBAL8),
2961 igb_getreg(TDWBAL9),
2962 igb_getreg(TDWBAL10),
2963 igb_getreg(TDWBAL11),
2964 igb_getreg(TDWBAL12),
2965 igb_getreg(TDWBAL13),
2966 igb_getreg(TDWBAL14),
2967 igb_getreg(TDWBAL15),
2968 igb_getreg(TDWBAH0),
2969 igb_getreg(TDWBAH1),
2970 igb_getreg(TDWBAH2),
2971 igb_getreg(TDWBAH3),
2972 igb_getreg(TDWBAH4),
2973 igb_getreg(TDWBAH5),
2974 igb_getreg(TDWBAH6),
2975 igb_getreg(TDWBAH7),
2976 igb_getreg(TDWBAH8),
2977 igb_getreg(TDWBAH9),
2978 igb_getreg(TDWBAH10),
2979 igb_getreg(TDWBAH11),
2980 igb_getreg(TDWBAH12),
2981 igb_getreg(TDWBAH13),
2982 igb_getreg(TDWBAH14),
2983 igb_getreg(TDWBAH15),
2984 igb_getreg(PVTCTRL0),
2985 igb_getreg(PVTCTRL1),
2986 igb_getreg(PVTCTRL2),
2987 igb_getreg(PVTCTRL3),
2988 igb_getreg(PVTCTRL4),
2989 igb_getreg(PVTCTRL5),
2990 igb_getreg(PVTCTRL6),
2991 igb_getreg(PVTCTRL7),
2992 igb_getreg(PVTEIMS0),
2993 igb_getreg(PVTEIMS1),
2994 igb_getreg(PVTEIMS2),
2995 igb_getreg(PVTEIMS3),
2996 igb_getreg(PVTEIMS4),
2997 igb_getreg(PVTEIMS5),
2998 igb_getreg(PVTEIMS6),
2999 igb_getreg(PVTEIMS7),
3000 igb_getreg(PVTEIAC0),
3001 igb_getreg(PVTEIAC1),
3002 igb_getreg(PVTEIAC2),
3003 igb_getreg(PVTEIAC3),
3004 igb_getreg(PVTEIAC4),
3005 igb_getreg(PVTEIAC5),
3006 igb_getreg(PVTEIAC6),
3007 igb_getreg(PVTEIAC7),
3008 igb_getreg(PVTEIAM0),
3009 igb_getreg(PVTEIAM1),
3010 igb_getreg(PVTEIAM2),
3011 igb_getreg(PVTEIAM3),
3012 igb_getreg(PVTEIAM4),
3013 igb_getreg(PVTEIAM5),
3014 igb_getreg(PVTEIAM6),
3015 igb_getreg(PVTEIAM7),
3016 igb_getreg(PVFGPRC0),
3017 igb_getreg(PVFGPRC1),
3018 igb_getreg(PVFGPRC2),
3019 igb_getreg(PVFGPRC3),
3020 igb_getreg(PVFGPRC4),
3021 igb_getreg(PVFGPRC5),
3022 igb_getreg(PVFGPRC6),
3023 igb_getreg(PVFGPRC7),
3024 igb_getreg(PVFGPTC0),
3025 igb_getreg(PVFGPTC1),
3026 igb_getreg(PVFGPTC2),
3027 igb_getreg(PVFGPTC3),
3028 igb_getreg(PVFGPTC4),
3029 igb_getreg(PVFGPTC5),
3030 igb_getreg(PVFGPTC6),
3031 igb_getreg(PVFGPTC7),
3032 igb_getreg(PVFGORC0),
3033 igb_getreg(PVFGORC1),
3034 igb_getreg(PVFGORC2),
3035 igb_getreg(PVFGORC3),
3036 igb_getreg(PVFGORC4),
3037 igb_getreg(PVFGORC5),
3038 igb_getreg(PVFGORC6),
3039 igb_getreg(PVFGORC7),
3040 igb_getreg(PVFGOTC0),
3041 igb_getreg(PVFGOTC1),
3042 igb_getreg(PVFGOTC2),
3043 igb_getreg(PVFGOTC3),
3044 igb_getreg(PVFGOTC4),
3045 igb_getreg(PVFGOTC5),
3046 igb_getreg(PVFGOTC6),
3047 igb_getreg(PVFGOTC7),
3048 igb_getreg(PVFMPRC0),
3049 igb_getreg(PVFMPRC1),
3050 igb_getreg(PVFMPRC2),
3051 igb_getreg(PVFMPRC3),
3052 igb_getreg(PVFMPRC4),
3053 igb_getreg(PVFMPRC5),
3054 igb_getreg(PVFMPRC6),
3055 igb_getreg(PVFMPRC7),
3056 igb_getreg(PVFGPRLBC0),
3057 igb_getreg(PVFGPRLBC1),
3058 igb_getreg(PVFGPRLBC2),
3059 igb_getreg(PVFGPRLBC3),
3060 igb_getreg(PVFGPRLBC4),
3061 igb_getreg(PVFGPRLBC5),
3062 igb_getreg(PVFGPRLBC6),
3063 igb_getreg(PVFGPRLBC7),
3064 igb_getreg(PVFGPTLBC0),
3065 igb_getreg(PVFGPTLBC1),
3066 igb_getreg(PVFGPTLBC2),
3067 igb_getreg(PVFGPTLBC3),
3068 igb_getreg(PVFGPTLBC4),
3069 igb_getreg(PVFGPTLBC5),
3070 igb_getreg(PVFGPTLBC6),
3071 igb_getreg(PVFGPTLBC7),
3072 igb_getreg(PVFGORLBC0),
3073 igb_getreg(PVFGORLBC1),
3074 igb_getreg(PVFGORLBC2),
3075 igb_getreg(PVFGORLBC3),
3076 igb_getreg(PVFGORLBC4),
3077 igb_getreg(PVFGORLBC5),
3078 igb_getreg(PVFGORLBC6),
3079 igb_getreg(PVFGORLBC7),
3080 igb_getreg(PVFGOTLBC0),
3081 igb_getreg(PVFGOTLBC1),
3082 igb_getreg(PVFGOTLBC2),
3083 igb_getreg(PVFGOTLBC3),
3084 igb_getreg(PVFGOTLBC4),
3085 igb_getreg(PVFGOTLBC5),
3086 igb_getreg(PVFGOTLBC6),
3087 igb_getreg(PVFGOTLBC7),
3088 igb_getreg(RCTL),
3089 igb_getreg(MDIC),
3090 igb_getreg(FCRUC),
3091 igb_getreg(VET),
3092 igb_getreg(RDBAL0),
3093 igb_getreg(RDBAL1),
3094 igb_getreg(RDBAL2),
3095 igb_getreg(RDBAL3),
3096 igb_getreg(RDBAL4),
3097 igb_getreg(RDBAL5),
3098 igb_getreg(RDBAL6),
3099 igb_getreg(RDBAL7),
3100 igb_getreg(RDBAL8),
3101 igb_getreg(RDBAL9),
3102 igb_getreg(RDBAL10),
3103 igb_getreg(RDBAL11),
3104 igb_getreg(RDBAL12),
3105 igb_getreg(RDBAL13),
3106 igb_getreg(RDBAL14),
3107 igb_getreg(RDBAL15),
3108 igb_getreg(TDBAH0),
3109 igb_getreg(TDBAH1),
3110 igb_getreg(TDBAH2),
3111 igb_getreg(TDBAH3),
3112 igb_getreg(TDBAH4),
3113 igb_getreg(TDBAH5),
3114 igb_getreg(TDBAH6),
3115 igb_getreg(TDBAH7),
3116 igb_getreg(TDBAH8),
3117 igb_getreg(TDBAH9),
3118 igb_getreg(TDBAH10),
3119 igb_getreg(TDBAH11),
3120 igb_getreg(TDBAH12),
3121 igb_getreg(TDBAH13),
3122 igb_getreg(TDBAH14),
3123 igb_getreg(TDBAH15),
3124 igb_getreg(SCC),
3125 igb_getreg(COLC),
3126 igb_getreg(XOFFRXC),
3127 igb_getreg(IPAV),
3128 igb_getreg(GOTCL),
3129 igb_getreg(MGTPDC),
3130 igb_getreg(GCR),
3131 igb_getreg(MFVAL),
3132 igb_getreg(FUNCTAG),
3133 igb_getreg(GSCL_4),
3134 igb_getreg(GSCN_3),
3135 igb_getreg(MRQC),
3136 igb_getreg(FCT),
3137 igb_getreg(FLA),
3138 igb_getreg(RXDCTL0),
3139 igb_getreg(RXDCTL1),
3140 igb_getreg(RXDCTL2),
3141 igb_getreg(RXDCTL3),
3142 igb_getreg(RXDCTL4),
3143 igb_getreg(RXDCTL5),
3144 igb_getreg(RXDCTL6),
3145 igb_getreg(RXDCTL7),
3146 igb_getreg(RXDCTL8),
3147 igb_getreg(RXDCTL9),
3148 igb_getreg(RXDCTL10),
3149 igb_getreg(RXDCTL11),
3150 igb_getreg(RXDCTL12),
3151 igb_getreg(RXDCTL13),
3152 igb_getreg(RXDCTL14),
3153 igb_getreg(RXDCTL15),
3154 igb_getreg(RXSTMPL),
3155 igb_getreg(TIMADJH),
3156 igb_getreg(FCRTL),
3157 igb_getreg(XONRXC),
3158 igb_getreg(RFCTL),
3159 igb_getreg(GSCN_1),
3160 igb_getreg(FCAL),
3161 igb_getreg(GPIE),
3162 igb_getreg(TXPBS),
3163 igb_getreg(RLPML),
3164
3165 [TOTH] = igb_mac_read_clr8,
3166 [GOTCH] = igb_mac_read_clr8,
3167 [PRC64] = igb_mac_read_clr4,
3168 [PRC255] = igb_mac_read_clr4,
3169 [PRC1023] = igb_mac_read_clr4,
3170 [PTC64] = igb_mac_read_clr4,
3171 [PTC255] = igb_mac_read_clr4,
3172 [PTC1023] = igb_mac_read_clr4,
3173 [GPRC] = igb_mac_read_clr4,
3174 [TPT] = igb_mac_read_clr4,
3175 [RUC] = igb_mac_read_clr4,
3176 [BPRC] = igb_mac_read_clr4,
3177 [MPTC] = igb_mac_read_clr4,
3178 [IAC] = igb_mac_read_clr4,
3179 [ICR] = igb_mac_icr_read,
3180 [STATUS] = igb_get_status,
3181 [ICS] = igb_mac_ics_read,
3182 /*
3183 * 8.8.10: Reading the IMC register returns the value of the IMS register.
3184 */
3185 [IMC] = igb_mac_ims_read,
3186 [TORH] = igb_mac_read_clr8,
3187 [GORCH] = igb_mac_read_clr8,
3188 [PRC127] = igb_mac_read_clr4,
3189 [PRC511] = igb_mac_read_clr4,
3190 [PRC1522] = igb_mac_read_clr4,
3191 [PTC127] = igb_mac_read_clr4,
3192 [PTC511] = igb_mac_read_clr4,
3193 [PTC1522] = igb_mac_read_clr4,
3194 [GPTC] = igb_mac_read_clr4,
3195 [TPR] = igb_mac_read_clr4,
3196 [ROC] = igb_mac_read_clr4,
3197 [MPRC] = igb_mac_read_clr4,
3198 [BPTC] = igb_mac_read_clr4,
3199 [TSCTC] = igb_mac_read_clr4,
3200 [CTRL] = igb_get_ctrl,
3201 [SWSM] = igb_mac_swsm_read,
3202 [IMS] = igb_mac_ims_read,
3203 [SYSTIML] = igb_get_systiml,
3204 [RXSATRH] = igb_get_rxsatrh,
3205 [TXSTMPH] = igb_get_txstmph,
3206
3207 [CRCERRS ... MPC] = igb_mac_readreg,
3208 [IP6AT ... IP6AT + 3] = igb_mac_readreg,
3209 [IP4AT ... IP4AT + 6] = igb_mac_readreg,
3210 [RA ... RA + 31] = igb_mac_readreg,
3211 [RA2 ... RA2 + 31] = igb_mac_readreg,
3212 [WUPM ... WUPM + 31] = igb_mac_readreg,
3213 [MTA ... MTA + E1000_MC_TBL_SIZE - 1] = igb_mac_readreg,
3214 [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] = igb_mac_readreg,
3215 [FFMT ... FFMT + 254] = igb_mac_readreg,
3216 [MDEF ... MDEF + 7] = igb_mac_readreg,
3217 [FTFT ... FTFT + 254] = igb_mac_readreg,
3218 [RETA ... RETA + 31] = igb_mac_readreg,
3219 [RSSRK ... RSSRK + 9] = igb_mac_readreg,
3220 [MAVTV0 ... MAVTV3] = igb_mac_readreg,
3221 [EITR0 ... EITR0 + IGB_INTR_NUM - 1] = igb_mac_eitr_read,
3222 [PVTEICR0] = igb_mac_read_clr4,
3223 [PVTEICR1] = igb_mac_read_clr4,
3224 [PVTEICR2] = igb_mac_read_clr4,
3225 [PVTEICR3] = igb_mac_read_clr4,
3226 [PVTEICR4] = igb_mac_read_clr4,
3227 [PVTEICR5] = igb_mac_read_clr4,
3228 [PVTEICR6] = igb_mac_read_clr4,
3229 [PVTEICR7] = igb_mac_read_clr4,
3230
3231 /* IGB specific: */
3232 [FWSM] = igb_mac_readreg,
3233 [SW_FW_SYNC] = igb_mac_readreg,
3234 [HTCBDPC] = igb_mac_read_clr4,
3235 [EICR] = igb_mac_read_clr4,
3236 [EIMS] = igb_mac_readreg,
3237 [EIAM] = igb_mac_readreg,
3238 [IVAR0 ... IVAR0 + 7] = igb_mac_readreg,
3239 igb_getreg(IVAR_MISC),
3240 igb_getreg(VT_CTL),
3241 [P2VMAILBOX0 ... P2VMAILBOX7] = igb_mac_readreg,
3242 [V2PMAILBOX0 ... V2PMAILBOX7] = igb_mac_vfmailbox_read,
3243 igb_getreg(MBVFICR),
3244 [VMBMEM0 ... VMBMEM0 + 127] = igb_mac_readreg,
3245 igb_getreg(MBVFIMR),
3246 igb_getreg(VFLRE),
3247 igb_getreg(VFRE),
3248 igb_getreg(VFTE),
3249 igb_getreg(QDE),
3250 igb_getreg(DTXSWC),
3251 igb_getreg(RPLOLR),
3252 [VLVF0 ... VLVF0 + E1000_VLVF_ARRAY_SIZE - 1] = igb_mac_readreg,
3253 [VMVIR0 ... VMVIR7] = igb_mac_readreg,
3254 [VMOLR0 ... VMOLR7] = igb_mac_readreg,
3255 [WVBR] = igb_mac_read_clr4,
3256 [RQDPC0] = igb_mac_read_clr4,
3257 [RQDPC1] = igb_mac_read_clr4,
3258 [RQDPC2] = igb_mac_read_clr4,
3259 [RQDPC3] = igb_mac_read_clr4,
3260 [RQDPC4] = igb_mac_read_clr4,
3261 [RQDPC5] = igb_mac_read_clr4,
3262 [RQDPC6] = igb_mac_read_clr4,
3263 [RQDPC7] = igb_mac_read_clr4,
3264 [RQDPC8] = igb_mac_read_clr4,
3265 [RQDPC9] = igb_mac_read_clr4,
3266 [RQDPC10] = igb_mac_read_clr4,
3267 [RQDPC11] = igb_mac_read_clr4,
3268 [RQDPC12] = igb_mac_read_clr4,
3269 [RQDPC13] = igb_mac_read_clr4,
3270 [RQDPC14] = igb_mac_read_clr4,
3271 [RQDPC15] = igb_mac_read_clr4,
3272 [VTIVAR ... VTIVAR + 7] = igb_mac_readreg,
3273 [VTIVAR_MISC ... VTIVAR_MISC + 7] = igb_mac_readreg,
3274 };
3275 enum { IGB_NREADOPS = ARRAY_SIZE(igb_macreg_readops) };
3276
3277 #define igb_putreg(x) [x] = igb_mac_writereg
3278 typedef void (*writeops)(IGBCore *, int, uint32_t);
3279 static const writeops igb_macreg_writeops[] = {
3280 igb_putreg(SWSM),
3281 igb_putreg(WUFC),
3282 igb_putreg(RDBAH0),
3283 igb_putreg(RDBAH1),
3284 igb_putreg(RDBAH2),
3285 igb_putreg(RDBAH3),
3286 igb_putreg(RDBAH4),
3287 igb_putreg(RDBAH5),
3288 igb_putreg(RDBAH6),
3289 igb_putreg(RDBAH7),
3290 igb_putreg(RDBAH8),
3291 igb_putreg(RDBAH9),
3292 igb_putreg(RDBAH10),
3293 igb_putreg(RDBAH11),
3294 igb_putreg(RDBAH12),
3295 igb_putreg(RDBAH13),
3296 igb_putreg(RDBAH14),
3297 igb_putreg(RDBAH15),
3298 igb_putreg(SRRCTL0),
3299 igb_putreg(SRRCTL1),
3300 igb_putreg(SRRCTL2),
3301 igb_putreg(SRRCTL3),
3302 igb_putreg(SRRCTL4),
3303 igb_putreg(SRRCTL5),
3304 igb_putreg(SRRCTL6),
3305 igb_putreg(SRRCTL7),
3306 igb_putreg(SRRCTL8),
3307 igb_putreg(SRRCTL9),
3308 igb_putreg(SRRCTL10),
3309 igb_putreg(SRRCTL11),
3310 igb_putreg(SRRCTL12),
3311 igb_putreg(SRRCTL13),
3312 igb_putreg(SRRCTL14),
3313 igb_putreg(SRRCTL15),
3314 igb_putreg(RXDCTL0),
3315 igb_putreg(RXDCTL1),
3316 igb_putreg(RXDCTL2),
3317 igb_putreg(RXDCTL3),
3318 igb_putreg(RXDCTL4),
3319 igb_putreg(RXDCTL5),
3320 igb_putreg(RXDCTL6),
3321 igb_putreg(RXDCTL7),
3322 igb_putreg(RXDCTL8),
3323 igb_putreg(RXDCTL9),
3324 igb_putreg(RXDCTL10),
3325 igb_putreg(RXDCTL11),
3326 igb_putreg(RXDCTL12),
3327 igb_putreg(RXDCTL13),
3328 igb_putreg(RXDCTL14),
3329 igb_putreg(RXDCTL15),
3330 igb_putreg(LEDCTL),
3331 igb_putreg(TCTL),
3332 igb_putreg(TCTL_EXT),
3333 igb_putreg(DTXCTL),
3334 igb_putreg(RXPBS),
3335 igb_putreg(RQDPC0),
3336 igb_putreg(FCAL),
3337 igb_putreg(FCRUC),
3338 igb_putreg(WUC),
3339 igb_putreg(WUS),
3340 igb_putreg(IPAV),
3341 igb_putreg(TDBAH0),
3342 igb_putreg(TDBAH1),
3343 igb_putreg(TDBAH2),
3344 igb_putreg(TDBAH3),
3345 igb_putreg(TDBAH4),
3346 igb_putreg(TDBAH5),
3347 igb_putreg(TDBAH6),
3348 igb_putreg(TDBAH7),
3349 igb_putreg(TDBAH8),
3350 igb_putreg(TDBAH9),
3351 igb_putreg(TDBAH10),
3352 igb_putreg(TDBAH11),
3353 igb_putreg(TDBAH12),
3354 igb_putreg(TDBAH13),
3355 igb_putreg(TDBAH14),
3356 igb_putreg(TDBAH15),
3357 igb_putreg(IAM),
3358 igb_putreg(MANC),
3359 igb_putreg(MANC2H),
3360 igb_putreg(MFVAL),
3361 igb_putreg(FACTPS),
3362 igb_putreg(FUNCTAG),
3363 igb_putreg(GSCL_1),
3364 igb_putreg(GSCL_2),
3365 igb_putreg(GSCL_3),
3366 igb_putreg(GSCL_4),
3367 igb_putreg(GSCN_0),
3368 igb_putreg(GSCN_1),
3369 igb_putreg(GSCN_2),
3370 igb_putreg(GSCN_3),
3371 igb_putreg(MRQC),
3372 igb_putreg(FLOP),
3373 igb_putreg(FLA),
3374 igb_putreg(TXDCTL0),
3375 igb_putreg(TXDCTL1),
3376 igb_putreg(TXDCTL2),
3377 igb_putreg(TXDCTL3),
3378 igb_putreg(TXDCTL4),
3379 igb_putreg(TXDCTL5),
3380 igb_putreg(TXDCTL6),
3381 igb_putreg(TXDCTL7),
3382 igb_putreg(TXDCTL8),
3383 igb_putreg(TXDCTL9),
3384 igb_putreg(TXDCTL10),
3385 igb_putreg(TXDCTL11),
3386 igb_putreg(TXDCTL12),
3387 igb_putreg(TXDCTL13),
3388 igb_putreg(TXDCTL14),
3389 igb_putreg(TXDCTL15),
3390 igb_putreg(TXCTL0),
3391 igb_putreg(TXCTL1),
3392 igb_putreg(TXCTL2),
3393 igb_putreg(TXCTL3),
3394 igb_putreg(TXCTL4),
3395 igb_putreg(TXCTL5),
3396 igb_putreg(TXCTL6),
3397 igb_putreg(TXCTL7),
3398 igb_putreg(TXCTL8),
3399 igb_putreg(TXCTL9),
3400 igb_putreg(TXCTL10),
3401 igb_putreg(TXCTL11),
3402 igb_putreg(TXCTL12),
3403 igb_putreg(TXCTL13),
3404 igb_putreg(TXCTL14),
3405 igb_putreg(TXCTL15),
3406 igb_putreg(TDWBAL0),
3407 igb_putreg(TDWBAL1),
3408 igb_putreg(TDWBAL2),
3409 igb_putreg(TDWBAL3),
3410 igb_putreg(TDWBAL4),
3411 igb_putreg(TDWBAL5),
3412 igb_putreg(TDWBAL6),
3413 igb_putreg(TDWBAL7),
3414 igb_putreg(TDWBAL8),
3415 igb_putreg(TDWBAL9),
3416 igb_putreg(TDWBAL10),
3417 igb_putreg(TDWBAL11),
3418 igb_putreg(TDWBAL12),
3419 igb_putreg(TDWBAL13),
3420 igb_putreg(TDWBAL14),
3421 igb_putreg(TDWBAL15),
3422 igb_putreg(TDWBAH0),
3423 igb_putreg(TDWBAH1),
3424 igb_putreg(TDWBAH2),
3425 igb_putreg(TDWBAH3),
3426 igb_putreg(TDWBAH4),
3427 igb_putreg(TDWBAH5),
3428 igb_putreg(TDWBAH6),
3429 igb_putreg(TDWBAH7),
3430 igb_putreg(TDWBAH8),
3431 igb_putreg(TDWBAH9),
3432 igb_putreg(TDWBAH10),
3433 igb_putreg(TDWBAH11),
3434 igb_putreg(TDWBAH12),
3435 igb_putreg(TDWBAH13),
3436 igb_putreg(TDWBAH14),
3437 igb_putreg(TDWBAH15),
3438 igb_putreg(TIPG),
3439 igb_putreg(RXSTMPH),
3440 igb_putreg(RXSTMPL),
3441 igb_putreg(RXSATRL),
3442 igb_putreg(RXSATRH),
3443 igb_putreg(TXSTMPL),
3444 igb_putreg(TXSTMPH),
3445 igb_putreg(SYSTIML),
3446 igb_putreg(SYSTIMH),
3447 igb_putreg(TIMADJL),
3448 igb_putreg(TSYNCRXCTL),
3449 igb_putreg(TSYNCTXCTL),
3450 igb_putreg(EEMNGCTL),
3451 igb_putreg(GPIE),
3452 igb_putreg(TXPBS),
3453 igb_putreg(RLPML),
3454 igb_putreg(VET),
3455
3456 [TDH0] = igb_set_16bit,
3457 [TDH1] = igb_set_16bit,
3458 [TDH2] = igb_set_16bit,
3459 [TDH3] = igb_set_16bit,
3460 [TDH4] = igb_set_16bit,
3461 [TDH5] = igb_set_16bit,
3462 [TDH6] = igb_set_16bit,
3463 [TDH7] = igb_set_16bit,
3464 [TDH8] = igb_set_16bit,
3465 [TDH9] = igb_set_16bit,
3466 [TDH10] = igb_set_16bit,
3467 [TDH11] = igb_set_16bit,
3468 [TDH12] = igb_set_16bit,
3469 [TDH13] = igb_set_16bit,
3470 [TDH14] = igb_set_16bit,
3471 [TDH15] = igb_set_16bit,
3472 [TDT0] = igb_set_tdt,
3473 [TDT1] = igb_set_tdt,
3474 [TDT2] = igb_set_tdt,
3475 [TDT3] = igb_set_tdt,
3476 [TDT4] = igb_set_tdt,
3477 [TDT5] = igb_set_tdt,
3478 [TDT6] = igb_set_tdt,
3479 [TDT7] = igb_set_tdt,
3480 [TDT8] = igb_set_tdt,
3481 [TDT9] = igb_set_tdt,
3482 [TDT10] = igb_set_tdt,
3483 [TDT11] = igb_set_tdt,
3484 [TDT12] = igb_set_tdt,
3485 [TDT13] = igb_set_tdt,
3486 [TDT14] = igb_set_tdt,
3487 [TDT15] = igb_set_tdt,
3488 [MDIC] = igb_set_mdic,
3489 [ICS] = igb_set_ics,
3490 [RDH0] = igb_set_16bit,
3491 [RDH1] = igb_set_16bit,
3492 [RDH2] = igb_set_16bit,
3493 [RDH3] = igb_set_16bit,
3494 [RDH4] = igb_set_16bit,
3495 [RDH5] = igb_set_16bit,
3496 [RDH6] = igb_set_16bit,
3497 [RDH7] = igb_set_16bit,
3498 [RDH8] = igb_set_16bit,
3499 [RDH9] = igb_set_16bit,
3500 [RDH10] = igb_set_16bit,
3501 [RDH11] = igb_set_16bit,
3502 [RDH12] = igb_set_16bit,
3503 [RDH13] = igb_set_16bit,
3504 [RDH14] = igb_set_16bit,
3505 [RDH15] = igb_set_16bit,
3506 [RDT0] = igb_set_rdt,
3507 [RDT1] = igb_set_rdt,
3508 [RDT2] = igb_set_rdt,
3509 [RDT3] = igb_set_rdt,
3510 [RDT4] = igb_set_rdt,
3511 [RDT5] = igb_set_rdt,
3512 [RDT6] = igb_set_rdt,
3513 [RDT7] = igb_set_rdt,
3514 [RDT8] = igb_set_rdt,
3515 [RDT9] = igb_set_rdt,
3516 [RDT10] = igb_set_rdt,
3517 [RDT11] = igb_set_rdt,
3518 [RDT12] = igb_set_rdt,
3519 [RDT13] = igb_set_rdt,
3520 [RDT14] = igb_set_rdt,
3521 [RDT15] = igb_set_rdt,
3522 [IMC] = igb_set_imc,
3523 [IMS] = igb_set_ims,
3524 [ICR] = igb_set_icr,
3525 [EECD] = igb_set_eecd,
3526 [RCTL] = igb_set_rx_control,
3527 [CTRL] = igb_set_ctrl,
3528 [EERD] = igb_set_eerd,
3529 [TDFH] = igb_set_13bit,
3530 [TDFT] = igb_set_13bit,
3531 [TDFHS] = igb_set_13bit,
3532 [TDFTS] = igb_set_13bit,
3533 [TDFPC] = igb_set_13bit,
3534 [RDFH] = igb_set_13bit,
3535 [RDFT] = igb_set_13bit,
3536 [RDFHS] = igb_set_13bit,
3537 [RDFTS] = igb_set_13bit,
3538 [RDFPC] = igb_set_13bit,
3539 [GCR] = igb_set_gcr,
3540 [RXCSUM] = igb_set_rxcsum,
3541 [TDLEN0] = igb_set_dlen,
3542 [TDLEN1] = igb_set_dlen,
3543 [TDLEN2] = igb_set_dlen,
3544 [TDLEN3] = igb_set_dlen,
3545 [TDLEN4] = igb_set_dlen,
3546 [TDLEN5] = igb_set_dlen,
3547 [TDLEN6] = igb_set_dlen,
3548 [TDLEN7] = igb_set_dlen,
3549 [TDLEN8] = igb_set_dlen,
3550 [TDLEN9] = igb_set_dlen,
3551 [TDLEN10] = igb_set_dlen,
3552 [TDLEN11] = igb_set_dlen,
3553 [TDLEN12] = igb_set_dlen,
3554 [TDLEN13] = igb_set_dlen,
3555 [TDLEN14] = igb_set_dlen,
3556 [TDLEN15] = igb_set_dlen,
3557 [RDLEN0] = igb_set_dlen,
3558 [RDLEN1] = igb_set_dlen,
3559 [RDLEN2] = igb_set_dlen,
3560 [RDLEN3] = igb_set_dlen,
3561 [RDLEN4] = igb_set_dlen,
3562 [RDLEN5] = igb_set_dlen,
3563 [RDLEN6] = igb_set_dlen,
3564 [RDLEN7] = igb_set_dlen,
3565 [RDLEN8] = igb_set_dlen,
3566 [RDLEN9] = igb_set_dlen,
3567 [RDLEN10] = igb_set_dlen,
3568 [RDLEN11] = igb_set_dlen,
3569 [RDLEN12] = igb_set_dlen,
3570 [RDLEN13] = igb_set_dlen,
3571 [RDLEN14] = igb_set_dlen,
3572 [RDLEN15] = igb_set_dlen,
3573 [TDBAL0] = igb_set_dbal,
3574 [TDBAL1] = igb_set_dbal,
3575 [TDBAL2] = igb_set_dbal,
3576 [TDBAL3] = igb_set_dbal,
3577 [TDBAL4] = igb_set_dbal,
3578 [TDBAL5] = igb_set_dbal,
3579 [TDBAL6] = igb_set_dbal,
3580 [TDBAL7] = igb_set_dbal,
3581 [TDBAL8] = igb_set_dbal,
3582 [TDBAL9] = igb_set_dbal,
3583 [TDBAL10] = igb_set_dbal,
3584 [TDBAL11] = igb_set_dbal,
3585 [TDBAL12] = igb_set_dbal,
3586 [TDBAL13] = igb_set_dbal,
3587 [TDBAL14] = igb_set_dbal,
3588 [TDBAL15] = igb_set_dbal,
3589 [RDBAL0] = igb_set_dbal,
3590 [RDBAL1] = igb_set_dbal,
3591 [RDBAL2] = igb_set_dbal,
3592 [RDBAL3] = igb_set_dbal,
3593 [RDBAL4] = igb_set_dbal,
3594 [RDBAL5] = igb_set_dbal,
3595 [RDBAL6] = igb_set_dbal,
3596 [RDBAL7] = igb_set_dbal,
3597 [RDBAL8] = igb_set_dbal,
3598 [RDBAL9] = igb_set_dbal,
3599 [RDBAL10] = igb_set_dbal,
3600 [RDBAL11] = igb_set_dbal,
3601 [RDBAL12] = igb_set_dbal,
3602 [RDBAL13] = igb_set_dbal,
3603 [RDBAL14] = igb_set_dbal,
3604 [RDBAL15] = igb_set_dbal,
3605 [STATUS] = igb_set_status,
3606 [PBACLR] = igb_set_pbaclr,
3607 [CTRL_EXT] = igb_set_ctrlext,
3608 [FCAH] = igb_set_16bit,
3609 [FCT] = igb_set_16bit,
3610 [FCTTV] = igb_set_16bit,
3611 [FCRTV] = igb_set_16bit,
3612 [FCRTH] = igb_set_fcrth,
3613 [FCRTL] = igb_set_fcrtl,
3614 [CTRL_DUP] = igb_set_ctrl,
3615 [RFCTL] = igb_set_rfctl,
3616 [TIMINCA] = igb_set_timinca,
3617 [TIMADJH] = igb_set_timadjh,
3618
3619 [IP6AT ... IP6AT + 3] = igb_mac_writereg,
3620 [IP4AT ... IP4AT + 6] = igb_mac_writereg,
3621 [RA] = igb_mac_writereg,
3622 [RA + 1] = igb_mac_setmacaddr,
3623 [RA + 2 ... RA + 31] = igb_mac_writereg,
3624 [RA2 ... RA2 + 31] = igb_mac_writereg,
3625 [WUPM ... WUPM + 31] = igb_mac_writereg,
3626 [MTA ... MTA + E1000_MC_TBL_SIZE - 1] = igb_mac_writereg,
3627 [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] = igb_mac_writereg,
3628 [FFMT ... FFMT + 254] = igb_set_4bit,
3629 [MDEF ... MDEF + 7] = igb_mac_writereg,
3630 [FTFT ... FTFT + 254] = igb_mac_writereg,
3631 [RETA ... RETA + 31] = igb_mac_writereg,
3632 [RSSRK ... RSSRK + 9] = igb_mac_writereg,
3633 [MAVTV0 ... MAVTV3] = igb_mac_writereg,
3634 [EITR0 ... EITR0 + IGB_INTR_NUM - 1] = igb_set_eitr,
3635
3636 /* IGB specific: */
3637 [FWSM] = igb_mac_writereg,
3638 [SW_FW_SYNC] = igb_mac_writereg,
3639 [EICR] = igb_set_eicr,
3640 [EICS] = igb_set_eics,
3641 [EIAC] = igb_set_eiac,
3642 [EIAM] = igb_set_eiam,
3643 [EIMC] = igb_set_eimc,
3644 [EIMS] = igb_set_eims,
3645 [IVAR0 ... IVAR0 + 7] = igb_mac_writereg,
3646 igb_putreg(IVAR_MISC),
3647 igb_putreg(VT_CTL),
3648 [P2VMAILBOX0 ... P2VMAILBOX7] = igb_set_pfmailbox,
3649 [V2PMAILBOX0 ... V2PMAILBOX7] = igb_set_vfmailbox,
3650 [MBVFICR] = igb_w1c,
3651 [VMBMEM0 ... VMBMEM0 + 127] = igb_mac_writereg,
3652 igb_putreg(MBVFIMR),
3653 [VFLRE] = igb_w1c,
3654 igb_putreg(VFRE),
3655 igb_putreg(VFTE),
3656 igb_putreg(QDE),
3657 igb_putreg(DTXSWC),
3658 igb_putreg(RPLOLR),
3659 [VLVF0 ... VLVF0 + E1000_VLVF_ARRAY_SIZE - 1] = igb_mac_writereg,
3660 [VMVIR0 ... VMVIR7] = igb_mac_writereg,
3661 [VMOLR0 ... VMOLR7] = igb_mac_writereg,
3662 [UTA ... UTA + E1000_MC_TBL_SIZE - 1] = igb_mac_writereg,
3663 [PVTCTRL0] = igb_set_vtctrl,
3664 [PVTCTRL1] = igb_set_vtctrl,
3665 [PVTCTRL2] = igb_set_vtctrl,
3666 [PVTCTRL3] = igb_set_vtctrl,
3667 [PVTCTRL4] = igb_set_vtctrl,
3668 [PVTCTRL5] = igb_set_vtctrl,
3669 [PVTCTRL6] = igb_set_vtctrl,
3670 [PVTCTRL7] = igb_set_vtctrl,
3671 [PVTEICS0] = igb_set_vteics,
3672 [PVTEICS1] = igb_set_vteics,
3673 [PVTEICS2] = igb_set_vteics,
3674 [PVTEICS3] = igb_set_vteics,
3675 [PVTEICS4] = igb_set_vteics,
3676 [PVTEICS5] = igb_set_vteics,
3677 [PVTEICS6] = igb_set_vteics,
3678 [PVTEICS7] = igb_set_vteics,
3679 [PVTEIMS0] = igb_set_vteims,
3680 [PVTEIMS1] = igb_set_vteims,
3681 [PVTEIMS2] = igb_set_vteims,
3682 [PVTEIMS3] = igb_set_vteims,
3683 [PVTEIMS4] = igb_set_vteims,
3684 [PVTEIMS5] = igb_set_vteims,
3685 [PVTEIMS6] = igb_set_vteims,
3686 [PVTEIMS7] = igb_set_vteims,
3687 [PVTEIMC0] = igb_set_vteimc,
3688 [PVTEIMC1] = igb_set_vteimc,
3689 [PVTEIMC2] = igb_set_vteimc,
3690 [PVTEIMC3] = igb_set_vteimc,
3691 [PVTEIMC4] = igb_set_vteimc,
3692 [PVTEIMC5] = igb_set_vteimc,
3693 [PVTEIMC6] = igb_set_vteimc,
3694 [PVTEIMC7] = igb_set_vteimc,
3695 [PVTEIAC0] = igb_set_vteiac,
3696 [PVTEIAC1] = igb_set_vteiac,
3697 [PVTEIAC2] = igb_set_vteiac,
3698 [PVTEIAC3] = igb_set_vteiac,
3699 [PVTEIAC4] = igb_set_vteiac,
3700 [PVTEIAC5] = igb_set_vteiac,
3701 [PVTEIAC6] = igb_set_vteiac,
3702 [PVTEIAC7] = igb_set_vteiac,
3703 [PVTEIAM0] = igb_set_vteiam,
3704 [PVTEIAM1] = igb_set_vteiam,
3705 [PVTEIAM2] = igb_set_vteiam,
3706 [PVTEIAM3] = igb_set_vteiam,
3707 [PVTEIAM4] = igb_set_vteiam,
3708 [PVTEIAM5] = igb_set_vteiam,
3709 [PVTEIAM6] = igb_set_vteiam,
3710 [PVTEIAM7] = igb_set_vteiam,
3711 [PVTEICR0] = igb_set_vteicr,
3712 [PVTEICR1] = igb_set_vteicr,
3713 [PVTEICR2] = igb_set_vteicr,
3714 [PVTEICR3] = igb_set_vteicr,
3715 [PVTEICR4] = igb_set_vteicr,
3716 [PVTEICR5] = igb_set_vteicr,
3717 [PVTEICR6] = igb_set_vteicr,
3718 [PVTEICR7] = igb_set_vteicr,
3719 [VTIVAR ... VTIVAR + 7] = igb_set_vtivar,
3720 [VTIVAR_MISC ... VTIVAR_MISC + 7] = igb_mac_writereg
3721 };
3722 enum { IGB_NWRITEOPS = ARRAY_SIZE(igb_macreg_writeops) };
3723
3724 enum { MAC_ACCESS_PARTIAL = 1 };
3725
3726 /*
3727 * The array below combines alias offsets of the index values for the
3728 * MAC registers that have aliases, with the indication of not fully
3729 * implemented registers (lowest bit). This combination is possible
3730 * because all of the offsets are even.
3731 */
3732 static const uint16_t mac_reg_access[E1000E_MAC_SIZE] = {
3733 /* Alias index offsets */
3734 [FCRTL_A] = 0x07fe,
3735 [RDFH_A] = 0xe904, [RDFT_A] = 0xe904,
3736 [TDFH_A] = 0xed00, [TDFT_A] = 0xed00,
3737 [RA_A ... RA_A + 31] = 0x14f0,
3738 [VFTA_A ... VFTA_A + E1000_VLAN_FILTER_TBL_SIZE - 1] = 0x1400,
3739
3740 [RDBAL0_A] = 0x2600,
3741 [RDBAH0_A] = 0x2600,
3742 [RDLEN0_A] = 0x2600,
3743 [SRRCTL0_A] = 0x2600,
3744 [RDH0_A] = 0x2600,
3745 [RDT0_A] = 0x2600,
3746 [RXDCTL0_A] = 0x2600,
3747 [RXCTL0_A] = 0x2600,
3748 [RQDPC0_A] = 0x2600,
3749 [RDBAL1_A] = 0x25D0,
3750 [RDBAL2_A] = 0x25A0,
3751 [RDBAL3_A] = 0x2570,
3752 [RDBAH1_A] = 0x25D0,
3753 [RDBAH2_A] = 0x25A0,
3754 [RDBAH3_A] = 0x2570,
3755 [RDLEN1_A] = 0x25D0,
3756 [RDLEN2_A] = 0x25A0,
3757 [RDLEN3_A] = 0x2570,
3758 [SRRCTL1_A] = 0x25D0,
3759 [SRRCTL2_A] = 0x25A0,
3760 [SRRCTL3_A] = 0x2570,
3761 [RDH1_A] = 0x25D0,
3762 [RDH2_A] = 0x25A0,
3763 [RDH3_A] = 0x2570,
3764 [RDT1_A] = 0x25D0,
3765 [RDT2_A] = 0x25A0,
3766 [RDT3_A] = 0x2570,
3767 [RXDCTL1_A] = 0x25D0,
3768 [RXDCTL2_A] = 0x25A0,
3769 [RXDCTL3_A] = 0x2570,
3770 [RXCTL1_A] = 0x25D0,
3771 [RXCTL2_A] = 0x25A0,
3772 [RXCTL3_A] = 0x2570,
3773 [RQDPC1_A] = 0x25D0,
3774 [RQDPC2_A] = 0x25A0,
3775 [RQDPC3_A] = 0x2570,
3776 [TDBAL0_A] = 0x2A00,
3777 [TDBAH0_A] = 0x2A00,
3778 [TDLEN0_A] = 0x2A00,
3779 [TDH0_A] = 0x2A00,
3780 [TDT0_A] = 0x2A00,
3781 [TXCTL0_A] = 0x2A00,
3782 [TDWBAL0_A] = 0x2A00,
3783 [TDWBAH0_A] = 0x2A00,
3784 [TDBAL1_A] = 0x29D0,
3785 [TDBAL2_A] = 0x29A0,
3786 [TDBAL3_A] = 0x2970,
3787 [TDBAH1_A] = 0x29D0,
3788 [TDBAH2_A] = 0x29A0,
3789 [TDBAH3_A] = 0x2970,
3790 [TDLEN1_A] = 0x29D0,
3791 [TDLEN2_A] = 0x29A0,
3792 [TDLEN3_A] = 0x2970,
3793 [TDH1_A] = 0x29D0,
3794 [TDH2_A] = 0x29A0,
3795 [TDH3_A] = 0x2970,
3796 [TDT1_A] = 0x29D0,
3797 [TDT2_A] = 0x29A0,
3798 [TDT3_A] = 0x2970,
3799 [TXDCTL0_A] = 0x2A00,
3800 [TXDCTL1_A] = 0x29D0,
3801 [TXDCTL2_A] = 0x29A0,
3802 [TXDCTL3_A] = 0x2970,
3803 [TXCTL1_A] = 0x29D0,
3804 [TXCTL2_A] = 0x29A0,
3805 [TXCTL3_A] = 0x29D0,
3806 [TDWBAL1_A] = 0x29D0,
3807 [TDWBAL2_A] = 0x29A0,
3808 [TDWBAL3_A] = 0x2970,
3809 [TDWBAH1_A] = 0x29D0,
3810 [TDWBAH2_A] = 0x29A0,
3811 [TDWBAH3_A] = 0x2970,
3812
3813 /* Access options */
3814 [RDFH] = MAC_ACCESS_PARTIAL, [RDFT] = MAC_ACCESS_PARTIAL,
3815 [RDFHS] = MAC_ACCESS_PARTIAL, [RDFTS] = MAC_ACCESS_PARTIAL,
3816 [RDFPC] = MAC_ACCESS_PARTIAL,
3817 [TDFH] = MAC_ACCESS_PARTIAL, [TDFT] = MAC_ACCESS_PARTIAL,
3818 [TDFHS] = MAC_ACCESS_PARTIAL, [TDFTS] = MAC_ACCESS_PARTIAL,
3819 [TDFPC] = MAC_ACCESS_PARTIAL, [EECD] = MAC_ACCESS_PARTIAL,
3820 [FLA] = MAC_ACCESS_PARTIAL,
3821 [FCAL] = MAC_ACCESS_PARTIAL, [FCAH] = MAC_ACCESS_PARTIAL,
3822 [FCT] = MAC_ACCESS_PARTIAL, [FCTTV] = MAC_ACCESS_PARTIAL,
3823 [FCRTV] = MAC_ACCESS_PARTIAL, [FCRTL] = MAC_ACCESS_PARTIAL,
3824 [FCRTH] = MAC_ACCESS_PARTIAL,
3825 [MAVTV0 ... MAVTV3] = MAC_ACCESS_PARTIAL
3826 };
3827
3828 void
3829 igb_core_write(IGBCore *core, hwaddr addr, uint64_t val, unsigned size)
3830 {
3831 uint16_t index = igb_get_reg_index_with_offset(mac_reg_access, addr);
3832
3833 if (index < IGB_NWRITEOPS && igb_macreg_writeops[index]) {
3834 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) {
3835 trace_e1000e_wrn_regs_write_trivial(index << 2);
3836 }
3837 trace_e1000e_core_write(index << 2, size, val);
3838 igb_macreg_writeops[index](core, index, val);
3839 } else if (index < IGB_NREADOPS && igb_macreg_readops[index]) {
3840 trace_e1000e_wrn_regs_write_ro(index << 2, size, val);
3841 } else {
3842 trace_e1000e_wrn_regs_write_unknown(index << 2, size, val);
3843 }
3844 }
3845
3846 uint64_t
3847 igb_core_read(IGBCore *core, hwaddr addr, unsigned size)
3848 {
3849 uint64_t val;
3850 uint16_t index = igb_get_reg_index_with_offset(mac_reg_access, addr);
3851
3852 if (index < IGB_NREADOPS && igb_macreg_readops[index]) {
3853 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) {
3854 trace_e1000e_wrn_regs_read_trivial(index << 2);
3855 }
3856 val = igb_macreg_readops[index](core, index);
3857 trace_e1000e_core_read(index << 2, size, val);
3858 return val;
3859 } else {
3860 trace_e1000e_wrn_regs_read_unknown(index << 2, size);
3861 }
3862 return 0;
3863 }
3864
3865 static inline void
3866 igb_autoneg_pause(IGBCore *core)
3867 {
3868 timer_del(core->autoneg_timer);
3869 }
3870
3871 static void
3872 igb_autoneg_resume(IGBCore *core)
3873 {
3874 if (igb_have_autoneg(core) &&
3875 !(core->phy[MII_BMSR] & MII_BMSR_AN_COMP)) {
3876 qemu_get_queue(core->owner_nic)->link_down = false;
3877 timer_mod(core->autoneg_timer,
3878 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 500);
3879 }
3880 }
3881
3882 static void
3883 igb_vm_state_change(void *opaque, bool running, RunState state)
3884 {
3885 IGBCore *core = opaque;
3886
3887 if (running) {
3888 trace_e1000e_vm_state_running();
3889 igb_intrmgr_resume(core);
3890 igb_autoneg_resume(core);
3891 } else {
3892 trace_e1000e_vm_state_stopped();
3893 igb_autoneg_pause(core);
3894 igb_intrmgr_pause(core);
3895 }
3896 }
3897
3898 void
3899 igb_core_pci_realize(IGBCore *core,
3900 const uint16_t *eeprom_templ,
3901 uint32_t eeprom_size,
3902 const uint8_t *macaddr)
3903 {
3904 int i;
3905
3906 core->autoneg_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL,
3907 igb_autoneg_timer, core);
3908 igb_intrmgr_pci_realize(core);
3909
3910 core->vmstate = qemu_add_vm_change_state_handler(igb_vm_state_change, core);
3911
3912 for (i = 0; i < IGB_NUM_QUEUES; i++) {
3913 net_tx_pkt_init(&core->tx[i].tx_pkt, E1000E_MAX_TX_FRAGS);
3914 }
3915
3916 net_rx_pkt_init(&core->rx_pkt);
3917
3918 e1000x_core_prepare_eeprom(core->eeprom,
3919 eeprom_templ,
3920 eeprom_size,
3921 PCI_DEVICE_GET_CLASS(core->owner)->device_id,
3922 macaddr);
3923 igb_update_rx_offloads(core);
3924 }
3925
3926 void
3927 igb_core_pci_uninit(IGBCore *core)
3928 {
3929 int i;
3930
3931 timer_free(core->autoneg_timer);
3932
3933 igb_intrmgr_pci_unint(core);
3934
3935 qemu_del_vm_change_state_handler(core->vmstate);
3936
3937 for (i = 0; i < IGB_NUM_QUEUES; i++) {
3938 net_tx_pkt_uninit(core->tx[i].tx_pkt);
3939 }
3940
3941 net_rx_pkt_uninit(core->rx_pkt);
3942 }
3943
3944 static const uint16_t
3945 igb_phy_reg_init[] = {
3946 [MII_BMCR] = MII_BMCR_SPEED1000 |
3947 MII_BMCR_FD |
3948 MII_BMCR_AUTOEN,
3949
3950 [MII_BMSR] = MII_BMSR_EXTCAP |
3951 MII_BMSR_LINK_ST |
3952 MII_BMSR_AUTONEG |
3953 MII_BMSR_MFPS |
3954 MII_BMSR_EXTSTAT |
3955 MII_BMSR_10T_HD |
3956 MII_BMSR_10T_FD |
3957 MII_BMSR_100TX_HD |
3958 MII_BMSR_100TX_FD,
3959
3960 [MII_PHYID1] = IGP03E1000_E_PHY_ID >> 16,
3961 [MII_PHYID2] = (IGP03E1000_E_PHY_ID & 0xfff0) | 1,
3962 [MII_ANAR] = MII_ANAR_CSMACD | MII_ANAR_10 |
3963 MII_ANAR_10FD | MII_ANAR_TX |
3964 MII_ANAR_TXFD | MII_ANAR_PAUSE |
3965 MII_ANAR_PAUSE_ASYM,
3966 [MII_ANLPAR] = MII_ANLPAR_10 | MII_ANLPAR_10FD |
3967 MII_ANLPAR_TX | MII_ANLPAR_TXFD |
3968 MII_ANLPAR_T4 | MII_ANLPAR_PAUSE,
3969 [MII_ANER] = MII_ANER_NP | MII_ANER_NWAY,
3970 [MII_ANNP] = 0x1 | MII_ANNP_MP,
3971 [MII_CTRL1000] = MII_CTRL1000_HALF | MII_CTRL1000_FULL |
3972 MII_CTRL1000_PORT | MII_CTRL1000_MASTER,
3973 [MII_STAT1000] = MII_STAT1000_HALF | MII_STAT1000_FULL |
3974 MII_STAT1000_ROK | MII_STAT1000_LOK,
3975 [MII_EXTSTAT] = MII_EXTSTAT_1000T_HD | MII_EXTSTAT_1000T_FD,
3976
3977 [IGP01E1000_PHY_PORT_CONFIG] = BIT(5) | BIT(8),
3978 [IGP01E1000_PHY_PORT_STATUS] = IGP01E1000_PSSR_SPEED_1000MBPS,
3979 [IGP02E1000_PHY_POWER_MGMT] = BIT(0) | BIT(3) | IGP02E1000_PM_D3_LPLU |
3980 IGP01E1000_PSCFR_SMART_SPEED
3981 };
3982
3983 static const uint32_t igb_mac_reg_init[] = {
3984 [LEDCTL] = 2 | (3 << 8) | BIT(15) | (6 << 16) | (7 << 24),
3985 [EEMNGCTL] = BIT(31),
3986 [TXDCTL0] = E1000_TXDCTL_QUEUE_ENABLE,
3987 [RXDCTL0] = E1000_RXDCTL_QUEUE_ENABLE | (1 << 16),
3988 [RXDCTL1] = 1 << 16,
3989 [RXDCTL2] = 1 << 16,
3990 [RXDCTL3] = 1 << 16,
3991 [RXDCTL4] = 1 << 16,
3992 [RXDCTL5] = 1 << 16,
3993 [RXDCTL6] = 1 << 16,
3994 [RXDCTL7] = 1 << 16,
3995 [RXDCTL8] = 1 << 16,
3996 [RXDCTL9] = 1 << 16,
3997 [RXDCTL10] = 1 << 16,
3998 [RXDCTL11] = 1 << 16,
3999 [RXDCTL12] = 1 << 16,
4000 [RXDCTL13] = 1 << 16,
4001 [RXDCTL14] = 1 << 16,
4002 [RXDCTL15] = 1 << 16,
4003 [TIPG] = 0x08 | (0x04 << 10) | (0x06 << 20),
4004 [CTRL] = E1000_CTRL_FD | E1000_CTRL_LRST | E1000_CTRL_SPD_1000 |
4005 E1000_CTRL_ADVD3WUC,
4006 [STATUS] = E1000_STATUS_PHYRA | BIT(31),
4007 [EECD] = E1000_EECD_FWE_DIS | E1000_EECD_PRES |
4008 (2 << E1000_EECD_SIZE_EX_SHIFT),
4009 [GCR] = E1000_L0S_ADJUST |
4010 E1000_GCR_CMPL_TMOUT_RESEND |
4011 E1000_GCR_CAP_VER2 |
4012 E1000_L1_ENTRY_LATENCY_MSB |
4013 E1000_L1_ENTRY_LATENCY_LSB,
4014 [RXCSUM] = E1000_RXCSUM_IPOFLD | E1000_RXCSUM_TUOFLD,
4015 [TXPBS] = 0x28,
4016 [RXPBS] = 0x40,
4017 [TCTL] = E1000_TCTL_PSP | (0xF << E1000_CT_SHIFT) |
4018 (0x40 << E1000_COLD_SHIFT) | (0x1 << 26) | (0xA << 28),
4019 [TCTL_EXT] = 0x40 | (0x42 << 10),
4020 [DTXCTL] = E1000_DTXCTL_8023LL | E1000_DTXCTL_SPOOF_INT,
4021 [VET] = ETH_P_VLAN | (ETH_P_VLAN << 16),
4022
4023 [V2PMAILBOX0 ... V2PMAILBOX0 + IGB_MAX_VF_FUNCTIONS - 1] = E1000_V2PMAILBOX_RSTI,
4024 [MBVFIMR] = 0xFF,
4025 [VFRE] = 0xFF,
4026 [VFTE] = 0xFF,
4027 [VMOLR0 ... VMOLR0 + 7] = 0x2600 | E1000_VMOLR_STRCRC,
4028 [RPLOLR] = E1000_RPLOLR_STRCRC,
4029 [RLPML] = 0x2600,
4030 [TXCTL0] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4031 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4032 E1000_DCA_TXCTRL_DESC_RRO_EN,
4033 [TXCTL1] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4034 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4035 E1000_DCA_TXCTRL_DESC_RRO_EN,
4036 [TXCTL2] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4037 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4038 E1000_DCA_TXCTRL_DESC_RRO_EN,
4039 [TXCTL3] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4040 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4041 E1000_DCA_TXCTRL_DESC_RRO_EN,
4042 [TXCTL4] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4043 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4044 E1000_DCA_TXCTRL_DESC_RRO_EN,
4045 [TXCTL5] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4046 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4047 E1000_DCA_TXCTRL_DESC_RRO_EN,
4048 [TXCTL6] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4049 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4050 E1000_DCA_TXCTRL_DESC_RRO_EN,
4051 [TXCTL7] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4052 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4053 E1000_DCA_TXCTRL_DESC_RRO_EN,
4054 [TXCTL8] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4055 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4056 E1000_DCA_TXCTRL_DESC_RRO_EN,
4057 [TXCTL9] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4058 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4059 E1000_DCA_TXCTRL_DESC_RRO_EN,
4060 [TXCTL10] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4061 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4062 E1000_DCA_TXCTRL_DESC_RRO_EN,
4063 [TXCTL11] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4064 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4065 E1000_DCA_TXCTRL_DESC_RRO_EN,
4066 [TXCTL12] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4067 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4068 E1000_DCA_TXCTRL_DESC_RRO_EN,
4069 [TXCTL13] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4070 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4071 E1000_DCA_TXCTRL_DESC_RRO_EN,
4072 [TXCTL14] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4073 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4074 E1000_DCA_TXCTRL_DESC_RRO_EN,
4075 [TXCTL15] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4076 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4077 E1000_DCA_TXCTRL_DESC_RRO_EN,
4078 };
4079
4080 static void igb_reset(IGBCore *core, bool sw)
4081 {
4082 struct igb_tx *tx;
4083 int i;
4084
4085 timer_del(core->autoneg_timer);
4086
4087 igb_intrmgr_reset(core);
4088
4089 memset(core->phy, 0, sizeof core->phy);
4090 memcpy(core->phy, igb_phy_reg_init, sizeof igb_phy_reg_init);
4091
4092 for (i = 0; i < E1000E_MAC_SIZE; i++) {
4093 if (sw &&
4094 (i == RXPBS || i == TXPBS ||
4095 (i >= EITR0 && i < EITR0 + IGB_INTR_NUM))) {
4096 continue;
4097 }
4098
4099 core->mac[i] = i < ARRAY_SIZE(igb_mac_reg_init) ?
4100 igb_mac_reg_init[i] : 0;
4101 }
4102
4103 if (qemu_get_queue(core->owner_nic)->link_down) {
4104 igb_link_down(core);
4105 }
4106
4107 e1000x_reset_mac_addr(core->owner_nic, core->mac, core->permanent_mac);
4108
4109 for (int vfn = 0; vfn < IGB_MAX_VF_FUNCTIONS; vfn++) {
4110 /* Set RSTI, so VF can identify a PF reset is in progress */
4111 core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_RSTI;
4112 }
4113
4114 for (i = 0; i < ARRAY_SIZE(core->tx); i++) {
4115 tx = &core->tx[i];
4116 memset(tx->ctx, 0, sizeof(tx->ctx));
4117 tx->first = true;
4118 tx->skip_cp = false;
4119 }
4120 }
4121
4122 void
4123 igb_core_reset(IGBCore *core)
4124 {
4125 igb_reset(core, false);
4126 }
4127
4128 void igb_core_pre_save(IGBCore *core)
4129 {
4130 int i;
4131 NetClientState *nc = qemu_get_queue(core->owner_nic);
4132
4133 /*
4134 * If link is down and auto-negotiation is supported and ongoing,
4135 * complete auto-negotiation immediately. This allows us to look
4136 * at MII_BMSR_AN_COMP to infer link status on load.
4137 */
4138 if (nc->link_down && igb_have_autoneg(core)) {
4139 core->phy[MII_BMSR] |= MII_BMSR_AN_COMP;
4140 igb_update_flowctl_status(core);
4141 }
4142
4143 for (i = 0; i < ARRAY_SIZE(core->tx); i++) {
4144 if (net_tx_pkt_has_fragments(core->tx[i].tx_pkt)) {
4145 core->tx[i].skip_cp = true;
4146 }
4147 }
4148 }
4149
4150 int
4151 igb_core_post_load(IGBCore *core)
4152 {
4153 NetClientState *nc = qemu_get_queue(core->owner_nic);
4154
4155 /*
4156 * nc.link_down can't be migrated, so infer link_down according
4157 * to link status bit in core.mac[STATUS].
4158 */
4159 nc->link_down = (core->mac[STATUS] & E1000_STATUS_LU) == 0;
4160
4161 return 0;
4162 }
armbru's QEMU hackery