| blob | 980ea10211a812a8ef60a0415feb0d5b8d5e4850 |
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2021 WANG Xuerui <git@xen0n.name>
5 *
6 * Based on tcg/riscv/tcg-target.c.inc
7 *
8 * Copyright (c) 2018 SiFive, Inc
9 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
10 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
11 * Copyright (c) 2008 Fabrice Bellard
12 *
13 * Permission is hereby granted, free of charge, to any person obtaining a copy
14 * of this software and associated documentation files (the "Software"), to deal
15 * in the Software without restriction, including without limitation the rights
16 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
17 * copies of the Software, and to permit persons to whom the Software is
18 * furnished to do so, subject to the following conditions:
19 *
20 * The above copyright notice and this permission notice shall be included in
21 * all copies or substantial portions of the Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
27 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
28 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
29 * THE SOFTWARE.
30 */
32 #include "../tcg-ldst.c.inc"
33 #include <asm/hwcap.h>
35 #ifdef CONFIG_DEBUG_TCG
36 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
37 "zero",
38 "ra",
39 "tp",
40 "sp",
41 "a0",
42 "a1",
43 "a2",
44 "a3",
45 "a4",
46 "a5",
47 "a6",
48 "a7",
49 "t0",
50 "t1",
51 "t2",
52 "t3",
53 "t4",
54 "t5",
55 "t6",
56 "t7",
57 "t8",
58 "r21", /* reserved in the LP64* ABI, hence no ABI name */
59 "s9",
60 "s0",
61 "s1",
62 "s2",
63 "s3",
64 "s4",
65 "s5",
66 "s6",
67 "s7",
68 "s8",
69 "vr0",
70 "vr1",
71 "vr2",
72 "vr3",
73 "vr4",
74 "vr5",
75 "vr6",
76 "vr7",
77 "vr8",
78 "vr9",
79 "vr10",
80 "vr11",
81 "vr12",
82 "vr13",
83 "vr14",
84 "vr15",
85 "vr16",
86 "vr17",
87 "vr18",
88 "vr19",
89 "vr20",
90 "vr21",
91 "vr22",
92 "vr23",
93 "vr24",
94 "vr25",
95 "vr26",
96 "vr27",
97 "vr28",
98 "vr29",
99 "vr30",
100 "vr31",
101 };
102 #endif
104 static const int tcg_target_reg_alloc_order[] = {
105 /* Registers preserved across calls */
106 /* TCG_REG_S0 reserved for TCG_AREG0 */
107 TCG_REG_S1,
108 TCG_REG_S2,
109 TCG_REG_S3,
110 TCG_REG_S4,
111 TCG_REG_S5,
112 TCG_REG_S6,
113 TCG_REG_S7,
114 TCG_REG_S8,
115 TCG_REG_S9,
117 /* Registers (potentially) clobbered across calls */
118 TCG_REG_T0,
119 TCG_REG_T1,
120 TCG_REG_T2,
121 TCG_REG_T3,
122 TCG_REG_T4,
123 TCG_REG_T5,
124 TCG_REG_T6,
125 TCG_REG_T7,
126 TCG_REG_T8,
128 /* Argument registers, opposite order of allocation. */
129 TCG_REG_A7,
130 TCG_REG_A6,
131 TCG_REG_A5,
132 TCG_REG_A4,
133 TCG_REG_A3,
134 TCG_REG_A2,
135 TCG_REG_A1,
136 TCG_REG_A0,
138 /* Vector registers */
139 TCG_REG_V0, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3,
140 TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7,
141 TCG_REG_V8, TCG_REG_V9, TCG_REG_V10, TCG_REG_V11,
142 TCG_REG_V12, TCG_REG_V13, TCG_REG_V14, TCG_REG_V15,
143 TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19,
144 TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23,
145 /* V24 - V31 are caller-saved, and skipped. */
146 };
148 static const int tcg_target_call_iarg_regs[] = {
149 TCG_REG_A0,
150 TCG_REG_A1,
151 TCG_REG_A2,
152 TCG_REG_A3,
153 TCG_REG_A4,
154 TCG_REG_A5,
155 TCG_REG_A6,
156 TCG_REG_A7,
157 };
159 static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
160 {
161 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL);
162 tcg_debug_assert(slot >= 0 && slot <= 1);
163 return TCG_REG_A0 + slot;
164 }
166 #define TCG_GUEST_BASE_REG TCG_REG_S1
168 #define TCG_CT_CONST_ZERO 0x100
169 #define TCG_CT_CONST_S12 0x200
170 #define TCG_CT_CONST_S32 0x400
171 #define TCG_CT_CONST_U12 0x800
172 #define TCG_CT_CONST_C12 0x1000
173 #define TCG_CT_CONST_WSZ 0x2000
174 #define TCG_CT_CONST_VCMP 0x4000
175 #define TCG_CT_CONST_VADD 0x8000
177 #define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32)
178 #define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32)
180 static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len)
181 {
182 return sextract64(val, pos, len);
183 }
185 /* test if a constant matches the constraint */
186 static bool tcg_target_const_match(int64_t val, int ct,
187 TCGType type, TCGCond cond, int vece)
188 {
189 if (ct & TCG_CT_CONST) {
190 return true;
191 }
192 if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
193 return true;
194 }
195 if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) {
196 return true;
197 }
198 if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
199 return true;
200 }
201 if ((ct & TCG_CT_CONST_U12) && val >= 0 && val <= 0xfff) {
202 return true;
203 }
204 if ((ct & TCG_CT_CONST_C12) && ~val >= 0 && ~val <= 0xfff) {
205 return true;
206 }
207 if ((ct & TCG_CT_CONST_WSZ) && val == (type == TCG_TYPE_I32 ? 32 : 64)) {
208 return true;
209 }
210 int64_t vec_val = sextract64(val, 0, 8 << vece);
211 if ((ct & TCG_CT_CONST_VCMP) && -0x10 <= vec_val && vec_val <= 0x1f) {
212 return true;
213 }
214 if ((ct & TCG_CT_CONST_VADD) && -0x1f <= vec_val && vec_val <= 0x1f) {
215 return true;
216 }
217 return false;
218 }
220 /*
221 * Relocations
222 */
224 /*
225 * Relocation records defined in LoongArch ELF psABI v1.00 is way too
226 * complicated; a whopping stack machine is needed to stuff the fields, at
227 * the very least one SOP_PUSH and one SOP_POP (of the correct format) are
228 * needed.
229 *
230 * Hence, define our own simpler relocation types. Numbers are chosen as to
231 * not collide with potential future additions to the true ELF relocation
232 * type enum.
233 */
235 /* Field Sk16, shifted right by 2; suitable for conditional jumps */
236 #define R_LOONGARCH_BR_SK16 256
237 /* Field Sd10k16, shifted right by 2; suitable for B and BL */
238 #define R_LOONGARCH_BR_SD10K16 257
240 static bool reloc_br_sk16(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
241 {
242 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
243 intptr_t offset = (intptr_t)target - (intptr_t)src_rx;
245 tcg_debug_assert((offset & 3) == 0);
246 offset >>= 2;
247 if (offset == sextreg(offset, 0, 16)) {
248 *src_rw = deposit64(*src_rw, 10, 16, offset);
249 return true;
250 }
252 return false;
253 }
255 static bool reloc_br_sd10k16(tcg_insn_unit *src_rw,
256 const tcg_insn_unit *target)
257 {
258 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
259 intptr_t offset = (intptr_t)target - (intptr_t)src_rx;
261 tcg_debug_assert((offset & 3) == 0);
262 offset >>= 2;
263 if (offset == sextreg(offset, 0, 26)) {
264 *src_rw = deposit64(*src_rw, 0, 10, offset >> 16); /* slot d10 */
265 *src_rw = deposit64(*src_rw, 10, 16, offset); /* slot k16 */
266 return true;
267 }
269 return false;
270 }
272 static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
273 intptr_t value, intptr_t addend)
274 {
275 tcg_debug_assert(addend == 0);
276 switch (type) {
277 case R_LOONGARCH_BR_SK16:
278 return reloc_br_sk16(code_ptr, (tcg_insn_unit *)value);
279 case R_LOONGARCH_BR_SD10K16:
280 return reloc_br_sd10k16(code_ptr, (tcg_insn_unit *)value);
281 default:
282 g_assert_not_reached();
283 }
284 }
286 #include "tcg-insn-defs.c.inc"
288 /*
289 * TCG intrinsics
290 */
292 static void tcg_out_mb(TCGContext *s, TCGArg a0)
293 {
294 /* Baseline LoongArch only has the full barrier, unfortunately. */
295 tcg_out_opc_dbar(s, 0);
296 }
298 static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
299 {
300 if (ret == arg) {
301 return true;
302 }
303 switch (type) {
304 case TCG_TYPE_I32:
305 case TCG_TYPE_I64:
306 if (ret < TCG_REG_V0) {
307 if (arg < TCG_REG_V0) {
308 /*
309 * Conventional register-register move used in LoongArch is
310 * `or dst, src, zero`.
311 */
312 tcg_out_opc_or(s, ret, arg, TCG_REG_ZERO);
313 } else {
314 tcg_out_opc_movfr2gr_d(s, ret, arg);
315 }
316 } else {
317 if (arg < TCG_REG_V0) {
318 tcg_out_opc_movgr2fr_d(s, ret, arg);
319 } else {
320 tcg_out_opc_fmov_d(s, ret, arg);
321 }
322 }
323 break;
324 case TCG_TYPE_V64:
325 case TCG_TYPE_V128:
326 tcg_out_opc_vori_b(s, ret, arg, 0);
327 break;
328 default:
329 g_assert_not_reached();
330 }
331 return true;
332 }
334 /* Loads a 32-bit immediate into rd, sign-extended. */
335 static void tcg_out_movi_i32(TCGContext *s, TCGReg rd, int32_t val)
336 {
337 tcg_target_long lo = sextreg(val, 0, 12);
338 tcg_target_long hi12 = sextreg(val, 12, 20);
340 /* Single-instruction cases. */
341 if (hi12 == 0) {
342 /* val fits in uimm12: ori rd, zero, val */
343 tcg_out_opc_ori(s, rd, TCG_REG_ZERO, val);
344 return;
345 }
346 if (hi12 == sextreg(lo, 12, 20)) {
347 /* val fits in simm12: addi.w rd, zero, val */
348 tcg_out_opc_addi_w(s, rd, TCG_REG_ZERO, val);
349 return;
350 }
352 /* High bits must be set; load with lu12i.w + optional ori. */
353 tcg_out_opc_lu12i_w(s, rd, hi12);
354 if (lo != 0) {
355 tcg_out_opc_ori(s, rd, rd, lo & 0xfff);
356 }
357 }
359 static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
360 tcg_target_long val)
361 {
362 /*
363 * LoongArch conventionally loads 64-bit immediates in at most 4 steps,
364 * with dedicated instructions for filling the respective bitfields
365 * below:
366 *
367 * 6 5 4 3
368 * 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2
369 * +-----------------------+---------------------------------------+...
370 * | hi52 | hi32 |
371 * +-----------------------+---------------------------------------+...
372 * 3 2 1
373 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
374 * ...+-------------------------------------+-------------------------+
375 * | hi12 | lo |
376 * ...+-------------------------------------+-------------------------+
377 *
378 * Check if val belong to one of the several fast cases, before falling
379 * back to the slow path.
380 */
382 intptr_t pc_offset;
383 tcg_target_long val_lo, val_hi, pc_hi, offset_hi;
384 tcg_target_long hi12, hi32, hi52;
386 /* Value fits in signed i32. */
387 if (type == TCG_TYPE_I32 || val == (int32_t)val) {
388 tcg_out_movi_i32(s, rd, val);
389 return;
390 }
392 /* PC-relative cases. */
393 pc_offset = tcg_pcrel_diff(s, (void *)val);
394 if (pc_offset == sextreg(pc_offset, 0, 22) && (pc_offset & 3) == 0) {
395 /* Single pcaddu2i. */
396 tcg_out_opc_pcaddu2i(s, rd, pc_offset >> 2);
397 return;
398 }
400 if (pc_offset == (int32_t)pc_offset) {
401 /* Offset within 32 bits; load with pcalau12i + ori. */
402 val_lo = sextreg(val, 0, 12);
403 val_hi = val >> 12;
404 pc_hi = (val - pc_offset) >> 12;
405 offset_hi = val_hi - pc_hi;
407 tcg_debug_assert(offset_hi == sextreg(offset_hi, 0, 20));
408 tcg_out_opc_pcalau12i(s, rd, offset_hi);
409 if (val_lo != 0) {
410 tcg_out_opc_ori(s, rd, rd, val_lo & 0xfff);
411 }
412 return;
413 }
415 hi12 = sextreg(val, 12, 20);
416 hi32 = sextreg(val, 32, 20);
417 hi52 = sextreg(val, 52, 12);
419 /* Single cu52i.d case. */
420 if ((hi52 != 0) && (ctz64(val) >= 52)) {
421 tcg_out_opc_cu52i_d(s, rd, TCG_REG_ZERO, hi52);
422 return;
423 }
425 /* Slow path. Initialize the low 32 bits, then concat high bits. */
426 tcg_out_movi_i32(s, rd, val);
428 /* Load hi32 and hi52 explicitly when they are unexpected values. */
429 if (hi32 != sextreg(hi12, 20, 20)) {
430 tcg_out_opc_cu32i_d(s, rd, hi32);
431 }
433 if (hi52 != sextreg(hi32, 20, 12)) {
434 tcg_out_opc_cu52i_d(s, rd, rd, hi52);
435 }
436 }
438 static void tcg_out_addi(TCGContext *s, TCGType type, TCGReg rd,
439 TCGReg rs, tcg_target_long imm)
440 {
441 tcg_target_long lo12 = sextreg(imm, 0, 12);
442 tcg_target_long hi16 = sextreg(imm - lo12, 16, 16);
444 /*
445 * Note that there's a hole in between hi16 and lo12:
446 *
447 * 3 2 1 0
448 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
449 * ...+-------------------------------+-------+-----------------------+
450 * | hi16 | | lo12 |
451 * ...+-------------------------------+-------+-----------------------+
452 *
453 * For bits within that hole, it's more efficient to use LU12I and ADD.
454 */
455 if (imm == (hi16 << 16) + lo12) {
456 if (hi16) {
457 tcg_out_opc_addu16i_d(s, rd, rs, hi16);
458 rs = rd;
459 }
460 if (type == TCG_TYPE_I32) {
461 tcg_out_opc_addi_w(s, rd, rs, lo12);
462 } else if (lo12) {
463 tcg_out_opc_addi_d(s, rd, rs, lo12);
464 } else {
465 tcg_out_mov(s, type, rd, rs);
466 }
467 } else {
468 tcg_out_movi(s, type, TCG_REG_TMP0, imm);
469 if (type == TCG_TYPE_I32) {
470 tcg_out_opc_add_w(s, rd, rs, TCG_REG_TMP0);
471 } else {
472 tcg_out_opc_add_d(s, rd, rs, TCG_REG_TMP0);
473 }
474 }
475 }
477 static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2)
478 {
479 return false;
480 }
482 static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs,
483 tcg_target_long imm)
484 {
485 /* This function is only used for passing structs by reference. */
486 g_assert_not_reached();
487 }
489 static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg)
490 {
491 tcg_out_opc_andi(s, ret, arg, 0xff);
492 }
494 static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg)
495 {
496 tcg_out_opc_bstrpick_w(s, ret, arg, 0, 15);
497 }
499 static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
500 {
501 tcg_out_opc_bstrpick_d(s, ret, arg, 0, 31);
502 }
504 static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
505 {
506 tcg_out_opc_sext_b(s, ret, arg);
507 }
509 static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
510 {
511 tcg_out_opc_sext_h(s, ret, arg);
512 }
514 static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg)
515 {
516 tcg_out_opc_addi_w(s, ret, arg, 0);
517 }
519 static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg)
520 {
521 if (ret != arg) {
522 tcg_out_ext32s(s, ret, arg);
523 }
524 }
526 static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg)
527 {
528 tcg_out_ext32u(s, ret, arg);
529 }
531 static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg ret, TCGReg arg)
532 {
533 tcg_out_ext32s(s, ret, arg);
534 }
536 static void tcg_out_clzctz(TCGContext *s, LoongArchInsn opc,
537 TCGReg a0, TCGReg a1, TCGReg a2,
538 bool c2, bool is_32bit)
539 {
540 if (c2) {
541 /*
542 * Fast path: semantics already satisfied due to constraint and
543 * insn behavior, single instruction is enough.
544 */
545 tcg_debug_assert(a2 == (is_32bit ? 32 : 64));
546 /* all clz/ctz insns belong to DJ-format */
547 tcg_out32(s, encode_dj_insn(opc, a0, a1));
548 return;
549 }
551 tcg_out32(s, encode_dj_insn(opc, TCG_REG_TMP0, a1));
552 /* a0 = a1 ? REG_TMP0 : a2 */
553 tcg_out_opc_maskeqz(s, TCG_REG_TMP0, TCG_REG_TMP0, a1);
554 tcg_out_opc_masknez(s, a0, a2, a1);
555 tcg_out_opc_or(s, a0, TCG_REG_TMP0, a0);
556 }
558 #define SETCOND_INV TCG_TARGET_NB_REGS
559 #define SETCOND_NEZ (SETCOND_INV << 1)
560 #define SETCOND_FLAGS (SETCOND_INV | SETCOND_NEZ)
562 static int tcg_out_setcond_int(TCGContext *s, TCGCond cond, TCGReg ret,
563 TCGReg arg1, tcg_target_long arg2, bool c2)
564 {
565 int flags = 0;
567 switch (cond) {
568 case TCG_COND_EQ: /* -> NE */
569 case TCG_COND_GE: /* -> LT */
570 case TCG_COND_GEU: /* -> LTU */
571 case TCG_COND_GT: /* -> LE */
572 case TCG_COND_GTU: /* -> LEU */
573 cond = tcg_invert_cond(cond);
574 flags ^= SETCOND_INV;
575 break;
576 default:
577 break;
578 }
580 switch (cond) {
581 case TCG_COND_LE:
582 case TCG_COND_LEU:
583 /*
584 * If we have a constant input, the most efficient way to implement
585 * LE is by adding 1 and using LT. Watch out for wrap around for LEU.
586 * We don't need to care for this for LE because the constant input
587 * is still constrained to int32_t, and INT32_MAX+1 is representable
588 * in the 64-bit temporary register.
589 */
590 if (c2) {
591 if (cond == TCG_COND_LEU) {
592 /* unsigned <= -1 is true */
593 if (arg2 == -1) {
594 tcg_out_movi(s, TCG_TYPE_REG, ret, !(flags & SETCOND_INV));
595 return ret;
596 }
597 cond = TCG_COND_LTU;
598 } else {
599 cond = TCG_COND_LT;
600 }
601 arg2 += 1;
602 } else {
603 TCGReg tmp = arg2;
604 arg2 = arg1;
605 arg1 = tmp;
606 cond = tcg_swap_cond(cond); /* LE -> GE */
607 cond = tcg_invert_cond(cond); /* GE -> LT */
608 flags ^= SETCOND_INV;
609 }
610 break;
611 default:
612 break;
613 }
615 switch (cond) {
616 case TCG_COND_NE:
617 flags |= SETCOND_NEZ;
618 if (!c2) {
619 tcg_out_opc_xor(s, ret, arg1, arg2);
620 } else if (arg2 == 0) {
621 ret = arg1;
622 } else if (arg2 >= 0 && arg2 <= 0xfff) {
623 tcg_out_opc_xori(s, ret, arg1, arg2);
624 } else {
625 tcg_out_addi(s, TCG_TYPE_REG, ret, arg1, -arg2);
626 }
627 break;
629 case TCG_COND_LT:
630 case TCG_COND_LTU:
631 if (c2) {
632 if (arg2 >= -0x800 && arg2 <= 0x7ff) {
633 if (cond == TCG_COND_LT) {
634 tcg_out_opc_slti(s, ret, arg1, arg2);
635 } else {
636 tcg_out_opc_sltui(s, ret, arg1, arg2);
637 }
638 break;
639 }
640 tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_TMP0, arg2);
641 arg2 = TCG_REG_TMP0;
642 }
643 if (cond == TCG_COND_LT) {
644 tcg_out_opc_slt(s, ret, arg1, arg2);
645 } else {
646 tcg_out_opc_sltu(s, ret, arg1, arg2);
647 }
648 break;
650 default:
651 g_assert_not_reached();
652 break;
653 }
655 return ret | flags;
656 }
658 static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret,
659 TCGReg arg1, tcg_target_long arg2, bool c2)
660 {
661 int tmpflags = tcg_out_setcond_int(s, cond, ret, arg1, arg2, c2);
663 if (tmpflags != ret) {
664 TCGReg tmp = tmpflags & ~SETCOND_FLAGS;
666 switch (tmpflags & SETCOND_FLAGS) {
667 case SETCOND_INV:
668 /* Intermediate result is boolean: simply invert. */
669 tcg_out_opc_xori(s, ret, tmp, 1);
670 break;
671 case SETCOND_NEZ:
672 /* Intermediate result is zero/non-zero: test != 0. */
673 tcg_out_opc_sltu(s, ret, TCG_REG_ZERO, tmp);
674 break;
675 case SETCOND_NEZ | SETCOND_INV:
676 /* Intermediate result is zero/non-zero: test == 0. */
677 tcg_out_opc_sltui(s, ret, tmp, 1);
678 break;
679 default:
680 g_assert_not_reached();
681 }
682 }
683 }
685 static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret,
686 TCGReg c1, tcg_target_long c2, bool const2,
687 TCGReg v1, TCGReg v2)
688 {
689 int tmpflags = tcg_out_setcond_int(s, cond, TCG_REG_TMP0, c1, c2, const2);
690 TCGReg t;
692 /* Standardize the test below to t != 0. */
693 if (tmpflags & SETCOND_INV) {
694 t = v1, v1 = v2, v2 = t;
695 }
697 t = tmpflags & ~SETCOND_FLAGS;
698 if (v1 == TCG_REG_ZERO) {
699 tcg_out_opc_masknez(s, ret, v2, t);
700 } else if (v2 == TCG_REG_ZERO) {
701 tcg_out_opc_maskeqz(s, ret, v1, t);
702 } else {
703 tcg_out_opc_masknez(s, TCG_REG_TMP2, v2, t); /* t ? 0 : v2 */
704 tcg_out_opc_maskeqz(s, TCG_REG_TMP1, v1, t); /* t ? v1 : 0 */
705 tcg_out_opc_or(s, ret, TCG_REG_TMP1, TCG_REG_TMP2);
706 }
707 }
709 /*
710 * Branch helpers
711 */
713 static const struct {
714 LoongArchInsn op;
715 bool swap;
716 } tcg_brcond_to_loongarch[] = {
717 [TCG_COND_EQ] = { OPC_BEQ, false },
718 [TCG_COND_NE] = { OPC_BNE, false },
719 [TCG_COND_LT] = { OPC_BGT, true },
720 [TCG_COND_GE] = { OPC_BLE, true },
721 [TCG_COND_LE] = { OPC_BLE, false },
722 [TCG_COND_GT] = { OPC_BGT, false },
723 [TCG_COND_LTU] = { OPC_BGTU, true },
724 [TCG_COND_GEU] = { OPC_BLEU, true },
725 [TCG_COND_LEU] = { OPC_BLEU, false },
726 [TCG_COND_GTU] = { OPC_BGTU, false }
727 };
729 static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1,
730 TCGReg arg2, TCGLabel *l)
731 {
732 LoongArchInsn op = tcg_brcond_to_loongarch[cond].op;
734 tcg_debug_assert(op != 0);
736 if (tcg_brcond_to_loongarch[cond].swap) {
737 TCGReg t = arg1;
738 arg1 = arg2;
739 arg2 = t;
740 }
742 /* all conditional branch insns belong to DJSk16-format */
743 tcg_out_reloc(s, s->code_ptr, R_LOONGARCH_BR_SK16, l, 0);
744 tcg_out32(s, encode_djsk16_insn(op, arg1, arg2, 0));
745 }
747 static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail)
748 {
749 TCGReg link = tail ? TCG_REG_ZERO : TCG_REG_RA;
750 ptrdiff_t offset = tcg_pcrel_diff(s, arg);
752 tcg_debug_assert((offset & 3) == 0);
753 if (offset == sextreg(offset, 0, 28)) {
754 /* short jump: +/- 256MiB */
755 if (tail) {
756 tcg_out_opc_b(s, offset >> 2);
757 } else {
758 tcg_out_opc_bl(s, offset >> 2);
759 }
760 } else if (offset == sextreg(offset, 0, 38)) {
761 /* long jump: +/- 256GiB */
762 tcg_target_long lo = sextreg(offset, 0, 18);
763 tcg_target_long hi = offset - lo;
764 tcg_out_opc_pcaddu18i(s, TCG_REG_TMP0, hi >> 18);
765 tcg_out_opc_jirl(s, link, TCG_REG_TMP0, lo >> 2);
766 } else {
767 /* far jump: 64-bit */
768 tcg_target_long lo = sextreg((tcg_target_long)arg, 0, 18);
769 tcg_target_long hi = (tcg_target_long)arg - lo;
770 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, hi);
771 tcg_out_opc_jirl(s, link, TCG_REG_TMP0, lo >> 2);
772 }
773 }
775 static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg,
776 const TCGHelperInfo *info)
777 {
778 tcg_out_call_int(s, arg, false);
779 }
781 /*
782 * Load/store helpers
783 */
785 static void tcg_out_ldst(TCGContext *s, LoongArchInsn opc, TCGReg data,
786 TCGReg addr, intptr_t offset)
787 {
788 intptr_t imm12 = sextreg(offset, 0, 12);
790 if (offset != imm12) {
791 intptr_t diff = tcg_pcrel_diff(s, (void *)offset);
793 if (addr == TCG_REG_ZERO && diff == (int32_t)diff) {
794 imm12 = sextreg(diff, 0, 12);
795 tcg_out_opc_pcaddu12i(s, TCG_REG_TMP2, (diff - imm12) >> 12);
796 } else {
797 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP2, offset - imm12);
798 if (addr != TCG_REG_ZERO) {
799 tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, addr);
800 }
801 }
802 addr = TCG_REG_TMP2;
803 }
805 switch (opc) {
806 case OPC_LD_B:
807 case OPC_LD_BU:
808 case OPC_LD_H:
809 case OPC_LD_HU:
810 case OPC_LD_W:
811 case OPC_LD_WU:
812 case OPC_LD_D:
813 case OPC_ST_B:
814 case OPC_ST_H:
815 case OPC_ST_W:
816 case OPC_ST_D:
817 tcg_out32(s, encode_djsk12_insn(opc, data, addr, imm12));
818 break;
819 case OPC_FLD_S:
820 case OPC_FLD_D:
821 case OPC_FST_S:
822 case OPC_FST_D:
823 tcg_out32(s, encode_fdjsk12_insn(opc, data, addr, imm12));
824 break;
825 default:
826 g_assert_not_reached();
827 }
828 }
830 static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg dest,
831 TCGReg base, intptr_t offset)
832 {
833 switch (type) {
834 case TCG_TYPE_I32:
835 if (dest < TCG_REG_V0) {
836 tcg_out_ldst(s, OPC_LD_W, dest, base, offset);
837 } else {
838 tcg_out_ldst(s, OPC_FLD_S, dest, base, offset);
839 }
840 break;
841 case TCG_TYPE_I64:
842 case TCG_TYPE_V64:
843 if (dest < TCG_REG_V0) {
844 tcg_out_ldst(s, OPC_LD_D, dest, base, offset);
845 } else {
846 tcg_out_ldst(s, OPC_FLD_D, dest, base, offset);
847 }
848 break;
849 case TCG_TYPE_V128:
850 if (-0x800 <= offset && offset <= 0x7ff) {
851 tcg_out_opc_vld(s, dest, base, offset);
852 } else {
853 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, offset);
854 tcg_out_opc_vldx(s, dest, base, TCG_REG_TMP0);
855 }
856 break;
857 default:
858 g_assert_not_reached();
859 }
860 }
862 static void tcg_out_st(TCGContext *s, TCGType type, TCGReg src,
863 TCGReg base, intptr_t offset)
864 {
865 switch (type) {
866 case TCG_TYPE_I32:
867 if (src < TCG_REG_V0) {
868 tcg_out_ldst(s, OPC_ST_W, src, base, offset);
869 } else {
870 tcg_out_ldst(s, OPC_FST_S, src, base, offset);
871 }
872 break;
873 case TCG_TYPE_I64:
874 case TCG_TYPE_V64:
875 if (src < TCG_REG_V0) {
876 tcg_out_ldst(s, OPC_ST_D, src, base, offset);
877 } else {
878 tcg_out_ldst(s, OPC_FST_D, src, base, offset);
879 }
880 break;
881 case TCG_TYPE_V128:
882 if (-0x800 <= offset && offset <= 0x7ff) {
883 tcg_out_opc_vst(s, src, base, offset);
884 } else {
885 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, offset);
886 tcg_out_opc_vstx(s, src, base, TCG_REG_TMP0);
887 }
888 break;
889 default:
890 g_assert_not_reached();
891 }
892 }
894 static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
895 TCGReg base, intptr_t ofs)
896 {
897 if (val == 0) {
898 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs);
899 return true;
900 }
901 return false;
902 }
904 /*
905 * Load/store helpers for SoftMMU, and qemu_ld/st implementations
906 */
908 static bool tcg_out_goto(TCGContext *s, const tcg_insn_unit *target)
909 {
910 tcg_out_opc_b(s, 0);
911 return reloc_br_sd10k16(s->code_ptr - 1, target);
912 }
914 static const TCGLdstHelperParam ldst_helper_param = {
915 .ntmp = 1, .tmp = { TCG_REG_TMP0 }
916 };
918 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
919 {
920 MemOp opc = get_memop(l->oi);
922 /* resolve label address */
923 if (!reloc_br_sk16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
924 return false;
925 }
927 tcg_out_ld_helper_args(s, l, &ldst_helper_param);
928 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE], false);
929 tcg_out_ld_helper_ret(s, l, false, &ldst_helper_param);
930 return tcg_out_goto(s, l->raddr);
931 }
933 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
934 {
935 MemOp opc = get_memop(l->oi);
937 /* resolve label address */
938 if (!reloc_br_sk16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
939 return false;
940 }
942 tcg_out_st_helper_args(s, l, &ldst_helper_param);
943 tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false);
944 return tcg_out_goto(s, l->raddr);
945 }
947 typedef struct {
948 TCGReg base;
949 TCGReg index;
950 TCGAtomAlign aa;
951 } HostAddress;
953 bool tcg_target_has_memory_bswap(MemOp memop)
954 {
955 return false;
956 }
958 /* We expect to use a 12-bit negative offset from ENV. */
959 #define MIN_TLB_MASK_TABLE_OFS -(1 << 11)
961 /*
962 * For system-mode, perform the TLB load and compare.
963 * For user-mode, perform any required alignment tests.
964 * In both cases, return a TCGLabelQemuLdst structure if the slow path
965 * is required and fill in @h with the host address for the fast path.
966 */
967 static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
968 TCGReg addr_reg, MemOpIdx oi,
969 bool is_ld)
970 {
971 TCGType addr_type = s->addr_type;
972 TCGLabelQemuLdst *ldst = NULL;
973 MemOp opc = get_memop(oi);
974 MemOp a_bits;
976 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false);
977 a_bits = h->aa.align;
979 if (tcg_use_softmmu) {
980 unsigned s_bits = opc & MO_SIZE;
981 int mem_index = get_mmuidx(oi);
982 int fast_ofs = tlb_mask_table_ofs(s, mem_index);
983 int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask);
984 int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table);
986 ldst = new_ldst_label(s);
987 ldst->is_ld = is_ld;
988 ldst->oi = oi;
989 ldst->addrlo_reg = addr_reg;
991 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_AREG0, mask_ofs);
992 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs);
994 tcg_out_opc_srli_d(s, TCG_REG_TMP2, addr_reg,
995 s->page_bits - CPU_TLB_ENTRY_BITS);
996 tcg_out_opc_and(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0);
997 tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1);
999 /* Load the tlb comparator and the addend. */
1000 QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN);
1001 tcg_out_ld(s, addr_type, TCG_REG_TMP0, TCG_REG_TMP2,
1002 is_ld ? offsetof(CPUTLBEntry, addr_read)
1003 : offsetof(CPUTLBEntry, addr_write));
1004 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2,
1005 offsetof(CPUTLBEntry, addend));
1007 /*
1008 * For aligned accesses, we check the first byte and include the
1009 * alignment bits within the address. For unaligned access, we
1010 * check that we don't cross pages using the address of the last
1011 * byte of the access.
1012 */
1013 if (a_bits < s_bits) {
1014 unsigned a_mask = (1u << a_bits) - 1;
1015 unsigned s_mask = (1u << s_bits) - 1;
1016 tcg_out_addi(s, addr_type, TCG_REG_TMP1, addr_reg, s_mask - a_mask);
1017 } else {
1018 tcg_out_mov(s, addr_type, TCG_REG_TMP1, addr_reg);
1019 }
1020 tcg_out_opc_bstrins_d(s, TCG_REG_TMP1, TCG_REG_ZERO,
1021 a_bits, s->page_bits - 1);
1023 /* Compare masked address with the TLB entry. */
1024 ldst->label_ptr[0] = s->code_ptr;
1025 tcg_out_opc_bne(s, TCG_REG_TMP0, TCG_REG_TMP1, 0);
1027 h->index = TCG_REG_TMP2;
1028 } else {
1029 if (a_bits) {
1030 ldst = new_ldst_label(s);
1032 ldst->is_ld = is_ld;
1033 ldst->oi = oi;
1034 ldst->addrlo_reg = addr_reg;
1036 /*
1037 * Without micro-architecture details, we don't know which of
1038 * bstrpick or andi is faster, so use bstrpick as it's not
1039 * constrained by imm field width. Not to say alignments >= 2^12
1040 * are going to happen any time soon.
1041 */
1042 tcg_out_opc_bstrpick_d(s, TCG_REG_TMP1, addr_reg, 0, a_bits - 1);
1044 ldst->label_ptr[0] = s->code_ptr;
1045 tcg_out_opc_bne(s, TCG_REG_TMP1, TCG_REG_ZERO, 0);
1046 }
1048 h->index = guest_base ? TCG_GUEST_BASE_REG : TCG_REG_ZERO;
1049 }
1051 if (addr_type == TCG_TYPE_I32) {
1052 h->base = TCG_REG_TMP0;
1053 tcg_out_ext32u(s, h->base, addr_reg);
1054 } else {
1055 h->base = addr_reg;
1056 }
1058 return ldst;
1059 }
1061 static void tcg_out_qemu_ld_indexed(TCGContext *s, MemOp opc, TCGType type,
1062 TCGReg rd, HostAddress h)
1063 {
1064 /* Byte swapping is left to middle-end expansion. */
1065 tcg_debug_assert((opc & MO_BSWAP) == 0);
1067 switch (opc & MO_SSIZE) {
1068 case MO_UB:
1069 tcg_out_opc_ldx_bu(s, rd, h.base, h.index);
1070 break;
1071 case MO_SB:
1072 tcg_out_opc_ldx_b(s, rd, h.base, h.index);
1073 break;
1074 case MO_UW:
1075 tcg_out_opc_ldx_hu(s, rd, h.base, h.index);
1076 break;
1077 case MO_SW:
1078 tcg_out_opc_ldx_h(s, rd, h.base, h.index);
1079 break;
1080 case MO_UL:
1081 if (type == TCG_TYPE_I64) {
1082 tcg_out_opc_ldx_wu(s, rd, h.base, h.index);
1083 break;
1084 }
1085 /* fallthrough */
1086 case MO_SL:
1087 tcg_out_opc_ldx_w(s, rd, h.base, h.index);
1088 break;
1089 case MO_UQ:
1090 tcg_out_opc_ldx_d(s, rd, h.base, h.index);
1091 break;
1092 default:
1093 g_assert_not_reached();
1094 }
1095 }
1097 static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
1098 MemOpIdx oi, TCGType data_type)
1099 {
1100 TCGLabelQemuLdst *ldst;
1101 HostAddress h;
1103 ldst = prepare_host_addr(s, &h, addr_reg, oi, true);
1104 tcg_out_qemu_ld_indexed(s, get_memop(oi), data_type, data_reg, h);
1106 if (ldst) {
1107 ldst->type = data_type;
1108 ldst->datalo_reg = data_reg;
1109 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr);
1110 }
1111 }
1113 static void tcg_out_qemu_st_indexed(TCGContext *s, MemOp opc,
1114 TCGReg rd, HostAddress h)
1115 {
1116 /* Byte swapping is left to middle-end expansion. */
1117 tcg_debug_assert((opc & MO_BSWAP) == 0);
1119 switch (opc & MO_SIZE) {
1120 case MO_8:
1121 tcg_out_opc_stx_b(s, rd, h.base, h.index);
1122 break;
1123 case MO_16:
1124 tcg_out_opc_stx_h(s, rd, h.base, h.index);
1125 break;
1126 case MO_32:
1127 tcg_out_opc_stx_w(s, rd, h.base, h.index);
1128 break;
1129 case MO_64:
1130 tcg_out_opc_stx_d(s, rd, h.base, h.index);
1131 break;
1132 default:
1133 g_assert_not_reached();
1134 }
1135 }
1137 static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
1138 MemOpIdx oi, TCGType data_type)
1139 {
1140 TCGLabelQemuLdst *ldst;
1141 HostAddress h;
1143 ldst = prepare_host_addr(s, &h, addr_reg, oi, false);
1144 tcg_out_qemu_st_indexed(s, get_memop(oi), data_reg, h);
1146 if (ldst) {
1147 ldst->type = data_type;
1148 ldst->datalo_reg = data_reg;
1149 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr);
1150 }
1151 }
1153 static void tcg_out_qemu_ldst_i128(TCGContext *s, TCGReg data_lo, TCGReg data_hi,
1154 TCGReg addr_reg, MemOpIdx oi, bool is_ld)
1155 {
1156 TCGLabelQemuLdst *ldst;
1157 HostAddress h;
1159 ldst = prepare_host_addr(s, &h, addr_reg, oi, is_ld);
1161 if (h.aa.atom == MO_128) {
1162 /*
1163 * Use VLDX/VSTX when 128-bit atomicity is required.
1164 * If address is aligned to 16-bytes, the 128-bit load/store is atomic.
1165 */
1166 if (is_ld) {
1167 tcg_out_opc_vldx(s, TCG_VEC_TMP0, h.base, h.index);
1168 tcg_out_opc_vpickve2gr_d(s, data_lo, TCG_VEC_TMP0, 0);
1169 tcg_out_opc_vpickve2gr_d(s, data_hi, TCG_VEC_TMP0, 1);
1170 } else {
1171 tcg_out_opc_vinsgr2vr_d(s, TCG_VEC_TMP0, data_lo, 0);
1172 tcg_out_opc_vinsgr2vr_d(s, TCG_VEC_TMP0, data_hi, 1);
1173 tcg_out_opc_vstx(s, TCG_VEC_TMP0, h.base, h.index);
1174 }
1175 } else {
1176 /* Otherwise use a pair of LD/ST. */
1177 TCGReg base = h.base;
1178 if (h.index != TCG_REG_ZERO) {
1179 base = TCG_REG_TMP0;
1180 tcg_out_opc_add_d(s, base, h.base, h.index);
1181 }
1182 if (is_ld) {
1183 tcg_debug_assert(base != data_lo);
1184 tcg_out_opc_ld_d(s, data_lo, base, 0);
1185 tcg_out_opc_ld_d(s, data_hi, base, 8);
1186 } else {
1187 tcg_out_opc_st_d(s, data_lo, base, 0);
1188 tcg_out_opc_st_d(s, data_hi, base, 8);
1189 }
1190 }
1192 if (ldst) {
1193 ldst->type = TCG_TYPE_I128;
1194 ldst->datalo_reg = data_lo;
1195 ldst->datahi_reg = data_hi;
1196 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr);
1197 }
1198 }
1200 /*
1201 * Entry-points
1202 */
1204 static const tcg_insn_unit *tb_ret_addr;
1206 static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0)
1207 {
1208 /* Reuse the zeroing that exists for goto_ptr. */
1209 if (a0 == 0) {
1210 tcg_out_call_int(s, tcg_code_gen_epilogue, true);
1211 } else {
1212 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A0, a0);
1213 tcg_out_call_int(s, tb_ret_addr, true);
1214 }
1215 }
1217 static void tcg_out_goto_tb(TCGContext *s, int which)
1218 {
1219 /*
1220 * Direct branch, or load indirect address, to be patched
1221 * by tb_target_set_jmp_target. Check indirect load offset
1222 * in range early, regardless of direct branch distance,
1223 * via assert within tcg_out_opc_pcaddu2i.
1224 */
1225 uintptr_t i_addr = get_jmp_target_addr(s, which);
1226 intptr_t i_disp = tcg_pcrel_diff(s, (void *)i_addr);
1228 set_jmp_insn_offset(s, which);
1229 tcg_out_opc_pcaddu2i(s, TCG_REG_TMP0, i_disp >> 2);
1231 /* Finish the load and indirect branch. */
1232 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_REG_TMP0, 0);
1233 tcg_out_opc_jirl(s, TCG_REG_ZERO, TCG_REG_TMP0, 0);
1234 set_jmp_reset_offset(s, which);
1235 }
1237 void tb_target_set_jmp_target(const TranslationBlock *tb, int n,
1238 uintptr_t jmp_rx, uintptr_t jmp_rw)
1239 {
1240 uintptr_t d_addr = tb->jmp_target_addr[n];
1241 ptrdiff_t d_disp = (ptrdiff_t)(d_addr - jmp_rx) >> 2;
1242 tcg_insn_unit insn;
1244 /* Either directly branch, or load slot address for indirect branch. */
1245 if (d_disp == sextreg(d_disp, 0, 26)) {
1246 insn = encode_sd10k16_insn(OPC_B, d_disp);
1247 } else {
1248 uintptr_t i_addr = (uintptr_t)&tb->jmp_target_addr[n];
1249 intptr_t i_disp = i_addr - jmp_rx;
1250 insn = encode_dsj20_insn(OPC_PCADDU2I, TCG_REG_TMP0, i_disp >> 2);
1251 }
1253 qatomic_set((tcg_insn_unit *)jmp_rw, insn);
1254 flush_idcache_range(jmp_rx, jmp_rw, 4);
1255 }
1257 static void tcg_out_op(TCGContext *s, TCGOpcode opc,
1258 const TCGArg args[TCG_MAX_OP_ARGS],
1259 const int const_args[TCG_MAX_OP_ARGS])
1260 {
1261 TCGArg a0 = args[0];
1262 TCGArg a1 = args[1];
1263 TCGArg a2 = args[2];
1264 TCGArg a3 = args[3];
1265 int c2 = const_args[2];
1267 switch (opc) {
1268 case INDEX_op_mb:
1269 tcg_out_mb(s, a0);
1270 break;
1272 case INDEX_op_goto_ptr:
1273 tcg_out_opc_jirl(s, TCG_REG_ZERO, a0, 0);
1274 break;
1276 case INDEX_op_br:
1277 tcg_out_reloc(s, s->code_ptr, R_LOONGARCH_BR_SD10K16, arg_label(a0),
1278 0);
1279 tcg_out_opc_b(s, 0);
1280 break;
1282 case INDEX_op_brcond_i32:
1283 case INDEX_op_brcond_i64:
1284 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3]));
1285 break;
1287 case INDEX_op_extrh_i64_i32:
1288 tcg_out_opc_srai_d(s, a0, a1, 32);
1289 break;
1291 case INDEX_op_not_i32:
1292 case INDEX_op_not_i64:
1293 tcg_out_opc_nor(s, a0, a1, TCG_REG_ZERO);
1294 break;
1296 case INDEX_op_nor_i32:
1297 case INDEX_op_nor_i64:
1298 if (c2) {
1299 tcg_out_opc_ori(s, a0, a1, a2);
1300 tcg_out_opc_nor(s, a0, a0, TCG_REG_ZERO);
1301 } else {
1302 tcg_out_opc_nor(s, a0, a1, a2);
1303 }
1304 break;
1306 case INDEX_op_andc_i32:
1307 case INDEX_op_andc_i64:
1308 if (c2) {
1309 /* guaranteed to fit due to constraint */
1310 tcg_out_opc_andi(s, a0, a1, ~a2);
1311 } else {
1312 tcg_out_opc_andn(s, a0, a1, a2);
1313 }
1314 break;
1316 case INDEX_op_orc_i32:
1317 case INDEX_op_orc_i64:
1318 if (c2) {
1319 /* guaranteed to fit due to constraint */
1320 tcg_out_opc_ori(s, a0, a1, ~a2);
1321 } else {
1322 tcg_out_opc_orn(s, a0, a1, a2);
1323 }
1324 break;
1326 case INDEX_op_and_i32:
1327 case INDEX_op_and_i64:
1328 if (c2) {
1329 tcg_out_opc_andi(s, a0, a1, a2);
1330 } else {
1331 tcg_out_opc_and(s, a0, a1, a2);
1332 }
1333 break;
1335 case INDEX_op_or_i32:
1336 case INDEX_op_or_i64:
1337 if (c2) {
1338 tcg_out_opc_ori(s, a0, a1, a2);
1339 } else {
1340 tcg_out_opc_or(s, a0, a1, a2);
1341 }
1342 break;
1344 case INDEX_op_xor_i32:
1345 case INDEX_op_xor_i64:
1346 if (c2) {
1347 tcg_out_opc_xori(s, a0, a1, a2);
1348 } else {
1349 tcg_out_opc_xor(s, a0, a1, a2);
1350 }
1351 break;
1353 case INDEX_op_extract_i32:
1354 tcg_out_opc_bstrpick_w(s, a0, a1, a2, a2 + args[3] - 1);
1355 break;
1356 case INDEX_op_extract_i64:
1357 tcg_out_opc_bstrpick_d(s, a0, a1, a2, a2 + args[3] - 1);
1358 break;
1360 case INDEX_op_deposit_i32:
1361 tcg_out_opc_bstrins_w(s, a0, a2, args[3], args[3] + args[4] - 1);
1362 break;
1363 case INDEX_op_deposit_i64:
1364 tcg_out_opc_bstrins_d(s, a0, a2, args[3], args[3] + args[4] - 1);
1365 break;
1367 case INDEX_op_bswap16_i32:
1368 case INDEX_op_bswap16_i64:
1369 tcg_out_opc_revb_2h(s, a0, a1);
1370 if (a2 & TCG_BSWAP_OS) {
1371 tcg_out_ext16s(s, TCG_TYPE_REG, a0, a0);
1372 } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
1373 tcg_out_ext16u(s, a0, a0);
1374 }
1375 break;
1377 case INDEX_op_bswap32_i32:
1378 /* All 32-bit values are computed sign-extended in the register. */
1379 a2 = TCG_BSWAP_OS;
1380 /* fallthrough */
1381 case INDEX_op_bswap32_i64:
1382 tcg_out_opc_revb_2w(s, a0, a1);
1383 if (a2 & TCG_BSWAP_OS) {
1384 tcg_out_ext32s(s, a0, a0);
1385 } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
1386 tcg_out_ext32u(s, a0, a0);
1387 }
1388 break;
1390 case INDEX_op_bswap64_i64:
1391 tcg_out_opc_revb_d(s, a0, a1);
1392 break;
1394 case INDEX_op_clz_i32:
1395 tcg_out_clzctz(s, OPC_CLZ_W, a0, a1, a2, c2, true);
1396 break;
1397 case INDEX_op_clz_i64:
1398 tcg_out_clzctz(s, OPC_CLZ_D, a0, a1, a2, c2, false);
1399 break;
1401 case INDEX_op_ctz_i32:
1402 tcg_out_clzctz(s, OPC_CTZ_W, a0, a1, a2, c2, true);
1403 break;
1404 case INDEX_op_ctz_i64:
1405 tcg_out_clzctz(s, OPC_CTZ_D, a0, a1, a2, c2, false);
1406 break;
1408 case INDEX_op_shl_i32:
1409 if (c2) {
1410 tcg_out_opc_slli_w(s, a0, a1, a2 & 0x1f);
1411 } else {
1412 tcg_out_opc_sll_w(s, a0, a1, a2);
1413 }
1414 break;
1415 case INDEX_op_shl_i64:
1416 if (c2) {
1417 tcg_out_opc_slli_d(s, a0, a1, a2 & 0x3f);
1418 } else {
1419 tcg_out_opc_sll_d(s, a0, a1, a2);
1420 }
1421 break;
1423 case INDEX_op_shr_i32:
1424 if (c2) {
1425 tcg_out_opc_srli_w(s, a0, a1, a2 & 0x1f);
1426 } else {
1427 tcg_out_opc_srl_w(s, a0, a1, a2);
1428 }
1429 break;
1430 case INDEX_op_shr_i64:
1431 if (c2) {
1432 tcg_out_opc_srli_d(s, a0, a1, a2 & 0x3f);
1433 } else {
1434 tcg_out_opc_srl_d(s, a0, a1, a2);
1435 }
1436 break;
1438 case INDEX_op_sar_i32:
1439 if (c2) {
1440 tcg_out_opc_srai_w(s, a0, a1, a2 & 0x1f);
1441 } else {
1442 tcg_out_opc_sra_w(s, a0, a1, a2);
1443 }
1444 break;
1445 case INDEX_op_sar_i64:
1446 if (c2) {
1447 tcg_out_opc_srai_d(s, a0, a1, a2 & 0x3f);
1448 } else {
1449 tcg_out_opc_sra_d(s, a0, a1, a2);
1450 }
1451 break;
1453 case INDEX_op_rotl_i32:
1454 /* transform into equivalent rotr/rotri */
1455 if (c2) {
1456 tcg_out_opc_rotri_w(s, a0, a1, (32 - a2) & 0x1f);
1457 } else {
1458 tcg_out_opc_sub_w(s, TCG_REG_TMP0, TCG_REG_ZERO, a2);
1459 tcg_out_opc_rotr_w(s, a0, a1, TCG_REG_TMP0);
1460 }
1461 break;
1462 case INDEX_op_rotl_i64:
1463 /* transform into equivalent rotr/rotri */
1464 if (c2) {
1465 tcg_out_opc_rotri_d(s, a0, a1, (64 - a2) & 0x3f);
1466 } else {
1467 tcg_out_opc_sub_w(s, TCG_REG_TMP0, TCG_REG_ZERO, a2);
1468 tcg_out_opc_rotr_d(s, a0, a1, TCG_REG_TMP0);
1469 }
1470 break;
1472 case INDEX_op_rotr_i32:
1473 if (c2) {
1474 tcg_out_opc_rotri_w(s, a0, a1, a2 & 0x1f);
1475 } else {
1476 tcg_out_opc_rotr_w(s, a0, a1, a2);
1477 }
1478 break;
1479 case INDEX_op_rotr_i64:
1480 if (c2) {
1481 tcg_out_opc_rotri_d(s, a0, a1, a2 & 0x3f);
1482 } else {
1483 tcg_out_opc_rotr_d(s, a0, a1, a2);
1484 }
1485 break;
1487 case INDEX_op_add_i32:
1488 if (c2) {
1489 tcg_out_addi(s, TCG_TYPE_I32, a0, a1, a2);
1490 } else {
1491 tcg_out_opc_add_w(s, a0, a1, a2);
1492 }
1493 break;
1494 case INDEX_op_add_i64:
1495 if (c2) {
1496 tcg_out_addi(s, TCG_TYPE_I64, a0, a1, a2);
1497 } else {
1498 tcg_out_opc_add_d(s, a0, a1, a2);
1499 }
1500 break;
1502 case INDEX_op_sub_i32:
1503 if (c2) {
1504 tcg_out_addi(s, TCG_TYPE_I32, a0, a1, -a2);
1505 } else {
1506 tcg_out_opc_sub_w(s, a0, a1, a2);
1507 }
1508 break;
1509 case INDEX_op_sub_i64:
1510 if (c2) {
1511 tcg_out_addi(s, TCG_TYPE_I64, a0, a1, -a2);
1512 } else {
1513 tcg_out_opc_sub_d(s, a0, a1, a2);
1514 }
1515 break;
1517 case INDEX_op_neg_i32:
1518 tcg_out_opc_sub_w(s, a0, TCG_REG_ZERO, a1);
1519 break;
1520 case INDEX_op_neg_i64:
1521 tcg_out_opc_sub_d(s, a0, TCG_REG_ZERO, a1);
1522 break;
1524 case INDEX_op_mul_i32:
1525 tcg_out_opc_mul_w(s, a0, a1, a2);
1526 break;
1527 case INDEX_op_mul_i64:
1528 tcg_out_opc_mul_d(s, a0, a1, a2);
1529 break;
1531 case INDEX_op_mulsh_i32:
1532 tcg_out_opc_mulh_w(s, a0, a1, a2);
1533 break;
1534 case INDEX_op_mulsh_i64:
1535 tcg_out_opc_mulh_d(s, a0, a1, a2);
1536 break;
1538 case INDEX_op_muluh_i32:
1539 tcg_out_opc_mulh_wu(s, a0, a1, a2);
1540 break;
1541 case INDEX_op_muluh_i64:
1542 tcg_out_opc_mulh_du(s, a0, a1, a2);
1543 break;
1545 case INDEX_op_div_i32:
1546 tcg_out_opc_div_w(s, a0, a1, a2);
1547 break;
1548 case INDEX_op_div_i64:
1549 tcg_out_opc_div_d(s, a0, a1, a2);
1550 break;
1552 case INDEX_op_divu_i32:
1553 tcg_out_opc_div_wu(s, a0, a1, a2);
1554 break;
1555 case INDEX_op_divu_i64:
1556 tcg_out_opc_div_du(s, a0, a1, a2);
1557 break;
1559 case INDEX_op_rem_i32:
1560 tcg_out_opc_mod_w(s, a0, a1, a2);
1561 break;
1562 case INDEX_op_rem_i64:
1563 tcg_out_opc_mod_d(s, a0, a1, a2);
1564 break;
1566 case INDEX_op_remu_i32:
1567 tcg_out_opc_mod_wu(s, a0, a1, a2);
1568 break;
1569 case INDEX_op_remu_i64:
1570 tcg_out_opc_mod_du(s, a0, a1, a2);
1571 break;
1573 case INDEX_op_setcond_i32:
1574 case INDEX_op_setcond_i64:
1575 tcg_out_setcond(s, args[3], a0, a1, a2, c2);
1576 break;
1578 case INDEX_op_movcond_i32:
1579 case INDEX_op_movcond_i64:
1580 tcg_out_movcond(s, args[5], a0, a1, a2, c2, args[3], args[4]);
1581 break;
1583 case INDEX_op_ld8s_i32:
1584 case INDEX_op_ld8s_i64:
1585 tcg_out_ldst(s, OPC_LD_B, a0, a1, a2);
1586 break;
1587 case INDEX_op_ld8u_i32:
1588 case INDEX_op_ld8u_i64:
1589 tcg_out_ldst(s, OPC_LD_BU, a0, a1, a2);
1590 break;
1591 case INDEX_op_ld16s_i32:
1592 case INDEX_op_ld16s_i64:
1593 tcg_out_ldst(s, OPC_LD_H, a0, a1, a2);
1594 break;
1595 case INDEX_op_ld16u_i32:
1596 case INDEX_op_ld16u_i64:
1597 tcg_out_ldst(s, OPC_LD_HU, a0, a1, a2);
1598 break;
1599 case INDEX_op_ld_i32:
1600 case INDEX_op_ld32s_i64:
1601 tcg_out_ldst(s, OPC_LD_W, a0, a1, a2);
1602 break;
1603 case INDEX_op_ld32u_i64:
1604 tcg_out_ldst(s, OPC_LD_WU, a0, a1, a2);
1605 break;
1606 case INDEX_op_ld_i64:
1607 tcg_out_ldst(s, OPC_LD_D, a0, a1, a2);
1608 break;
1610 case INDEX_op_st8_i32:
1611 case INDEX_op_st8_i64:
1612 tcg_out_ldst(s, OPC_ST_B, a0, a1, a2);
1613 break;
1614 case INDEX_op_st16_i32:
1615 case INDEX_op_st16_i64:
1616 tcg_out_ldst(s, OPC_ST_H, a0, a1, a2);
1617 break;
1618 case INDEX_op_st_i32:
1619 case INDEX_op_st32_i64:
1620 tcg_out_ldst(s, OPC_ST_W, a0, a1, a2);
1621 break;
1622 case INDEX_op_st_i64:
1623 tcg_out_ldst(s, OPC_ST_D, a0, a1, a2);
1624 break;
1626 case INDEX_op_qemu_ld_a32_i32:
1627 case INDEX_op_qemu_ld_a64_i32:
1628 tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32);
1629 break;
1630 case INDEX_op_qemu_ld_a32_i64:
1631 case INDEX_op_qemu_ld_a64_i64:
1632 tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64);
1633 break;
1634 case INDEX_op_qemu_ld_a32_i128:
1635 case INDEX_op_qemu_ld_a64_i128:
1636 tcg_out_qemu_ldst_i128(s, a0, a1, a2, a3, true);
1637 break;
1638 case INDEX_op_qemu_st_a32_i32:
1639 case INDEX_op_qemu_st_a64_i32:
1640 tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32);
1641 break;
1642 case INDEX_op_qemu_st_a32_i64:
1643 case INDEX_op_qemu_st_a64_i64:
1644 tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64);
1645 break;
1646 case INDEX_op_qemu_st_a32_i128:
1647 case INDEX_op_qemu_st_a64_i128:
1648 tcg_out_qemu_ldst_i128(s, a0, a1, a2, a3, false);
1649 break;
1651 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
1652 case INDEX_op_mov_i64:
1653 case INDEX_op_call: /* Always emitted via tcg_out_call. */
1654 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */
1655 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */
1656 case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */
1657 case INDEX_op_ext8s_i64:
1658 case INDEX_op_ext8u_i32:
1659 case INDEX_op_ext8u_i64:
1660 case INDEX_op_ext16s_i32:
1661 case INDEX_op_ext16s_i64:
1662 case INDEX_op_ext16u_i32:
1663 case INDEX_op_ext16u_i64:
1664 case INDEX_op_ext32s_i64:
1665 case INDEX_op_ext32u_i64:
1666 case INDEX_op_ext_i32_i64:
1667 case INDEX_op_extu_i32_i64:
1668 case INDEX_op_extrl_i64_i32:
1669 default:
1670 g_assert_not_reached();
1671 }
1672 }
1674 static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
1675 TCGReg rd, TCGReg rs)
1676 {
1677 switch (vece) {
1678 case MO_8:
1679 tcg_out_opc_vreplgr2vr_b(s, rd, rs);
1680 break;
1681 case MO_16:
1682 tcg_out_opc_vreplgr2vr_h(s, rd, rs);
1683 break;
1684 case MO_32:
1685 tcg_out_opc_vreplgr2vr_w(s, rd, rs);
1686 break;
1687 case MO_64:
1688 tcg_out_opc_vreplgr2vr_d(s, rd, rs);
1689 break;
1690 default:
1691 g_assert_not_reached();
1692 }
1693 return true;
1694 }
1696 static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
1697 TCGReg r, TCGReg base, intptr_t offset)
1698 {
1699 /* Handle imm overflow and division (vldrepl.d imm is divided by 8) */
1700 if (offset < -0x800 || offset > 0x7ff || \
1701 (offset & ((1 << vece) - 1)) != 0) {
1702 tcg_out_addi(s, TCG_TYPE_I64, TCG_REG_TMP0, base, offset);
1703 base = TCG_REG_TMP0;
1704 offset = 0;
1705 }
1706 offset >>= vece;
1708 switch (vece) {
1709 case MO_8:
1710 tcg_out_opc_vldrepl_b(s, r, base, offset);
1711 break;
1712 case MO_16:
1713 tcg_out_opc_vldrepl_h(s, r, base, offset);
1714 break;
1715 case MO_32:
1716 tcg_out_opc_vldrepl_w(s, r, base, offset);
1717 break;
1718 case MO_64:
1719 tcg_out_opc_vldrepl_d(s, r, base, offset);
1720 break;
1721 default:
1722 g_assert_not_reached();
1723 }
1724 return true;
1725 }
1727 static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
1728 TCGReg rd, int64_t v64)
1729 {
1730 /* Try vldi if imm can fit */
1731 int64_t value = sextract64(v64, 0, 8 << vece);
1732 if (-0x200 <= value && value <= 0x1FF) {
1733 uint32_t imm = (vece << 10) | ((uint32_t)v64 & 0x3FF);
1734 tcg_out_opc_vldi(s, rd, imm);
1735 return;
1736 }
1738 /* TODO: vldi patterns when imm 12 is set */
1740 /* Fallback to vreplgr2vr */
1741 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP0, value);
1742 switch (vece) {
1743 case MO_8:
1744 tcg_out_opc_vreplgr2vr_b(s, rd, TCG_REG_TMP0);
1745 break;
1746 case MO_16:
1747 tcg_out_opc_vreplgr2vr_h(s, rd, TCG_REG_TMP0);
1748 break;
1749 case MO_32:
1750 tcg_out_opc_vreplgr2vr_w(s, rd, TCG_REG_TMP0);
1751 break;
1752 case MO_64:
1753 tcg_out_opc_vreplgr2vr_d(s, rd, TCG_REG_TMP0);
1754 break;
1755 default:
1756 g_assert_not_reached();
1757 }
1758 }
1760 static void tcg_out_addsub_vec(TCGContext *s, unsigned vece, const TCGArg a0,
1761 const TCGArg a1, const TCGArg a2,
1762 bool a2_is_const, bool is_add)
1763 {
1764 static const LoongArchInsn add_vec_insn[4] = {
1765 OPC_VADD_B, OPC_VADD_H, OPC_VADD_W, OPC_VADD_D
1766 };
1767 static const LoongArchInsn add_vec_imm_insn[4] = {
1768 OPC_VADDI_BU, OPC_VADDI_HU, OPC_VADDI_WU, OPC_VADDI_DU
1769 };
1770 static const LoongArchInsn sub_vec_insn[4] = {
1771 OPC_VSUB_B, OPC_VSUB_H, OPC_VSUB_W, OPC_VSUB_D
1772 };
1773 static const LoongArchInsn sub_vec_imm_insn[4] = {
1774 OPC_VSUBI_BU, OPC_VSUBI_HU, OPC_VSUBI_WU, OPC_VSUBI_DU
1775 };
1777 if (a2_is_const) {
1778 int64_t value = sextract64(a2, 0, 8 << vece);
1779 if (!is_add) {
1780 value = -value;
1781 }
1783 /* Try vaddi/vsubi */
1784 if (0 <= value && value <= 0x1f) {
1785 tcg_out32(s, encode_vdvjuk5_insn(add_vec_imm_insn[vece], a0, \
1786 a1, value));
1787 return;
1788 } else if (-0x1f <= value && value < 0) {
1789 tcg_out32(s, encode_vdvjuk5_insn(sub_vec_imm_insn[vece], a0, \
1790 a1, -value));
1791 return;
1792 }
1794 /* constraint TCG_CT_CONST_VADD ensures unreachable */
1795 g_assert_not_reached();
1796 }
1798 if (is_add) {
1799 tcg_out32(s, encode_vdvjvk_insn(add_vec_insn[vece], a0, a1, a2));
1800 } else {
1801 tcg_out32(s, encode_vdvjvk_insn(sub_vec_insn[vece], a0, a1, a2));
1802 }
1803 }
1805 static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
1806 unsigned vecl, unsigned vece,
1807 const TCGArg args[TCG_MAX_OP_ARGS],
1808 const int const_args[TCG_MAX_OP_ARGS])
1809 {
1810 TCGType type = vecl + TCG_TYPE_V64;
1811 TCGArg a0, a1, a2, a3;
1812 TCGReg temp_vec = TCG_VEC_TMP0;
1814 static const LoongArchInsn cmp_vec_insn[16][4] = {
1815 [TCG_COND_EQ] = {OPC_VSEQ_B, OPC_VSEQ_H, OPC_VSEQ_W, OPC_VSEQ_D},
1816 [TCG_COND_LE] = {OPC_VSLE_B, OPC_VSLE_H, OPC_VSLE_W, OPC_VSLE_D},
1817 [TCG_COND_LEU] = {OPC_VSLE_BU, OPC_VSLE_HU, OPC_VSLE_WU, OPC_VSLE_DU},
1818 [TCG_COND_LT] = {OPC_VSLT_B, OPC_VSLT_H, OPC_VSLT_W, OPC_VSLT_D},
1819 [TCG_COND_LTU] = {OPC_VSLT_BU, OPC_VSLT_HU, OPC_VSLT_WU, OPC_VSLT_DU},
1820 };
1821 static const LoongArchInsn cmp_vec_imm_insn[16][4] = {
1822 [TCG_COND_EQ] = {OPC_VSEQI_B, OPC_VSEQI_H, OPC_VSEQI_W, OPC_VSEQI_D},
1823 [TCG_COND_LE] = {OPC_VSLEI_B, OPC_VSLEI_H, OPC_VSLEI_W, OPC_VSLEI_D},
1824 [TCG_COND_LEU] = {OPC_VSLEI_BU, OPC_VSLEI_HU, OPC_VSLEI_WU, OPC_VSLEI_DU},
1825 [TCG_COND_LT] = {OPC_VSLTI_B, OPC_VSLTI_H, OPC_VSLTI_W, OPC_VSLTI_D},
1826 [TCG_COND_LTU] = {OPC_VSLTI_BU, OPC_VSLTI_HU, OPC_VSLTI_WU, OPC_VSLTI_DU},
1827 };
1828 LoongArchInsn insn;
1829 static const LoongArchInsn neg_vec_insn[4] = {
1830 OPC_VNEG_B, OPC_VNEG_H, OPC_VNEG_W, OPC_VNEG_D
1831 };
1832 static const LoongArchInsn mul_vec_insn[4] = {
1833 OPC_VMUL_B, OPC_VMUL_H, OPC_VMUL_W, OPC_VMUL_D
1834 };
1835 static const LoongArchInsn smin_vec_insn[4] = {
1836 OPC_VMIN_B, OPC_VMIN_H, OPC_VMIN_W, OPC_VMIN_D
1837 };
1838 static const LoongArchInsn umin_vec_insn[4] = {
1839 OPC_VMIN_BU, OPC_VMIN_HU, OPC_VMIN_WU, OPC_VMIN_DU
1840 };
1841 static const LoongArchInsn smax_vec_insn[4] = {
1842 OPC_VMAX_B, OPC_VMAX_H, OPC_VMAX_W, OPC_VMAX_D
1843 };
1844 static const LoongArchInsn umax_vec_insn[4] = {
1845 OPC_VMAX_BU, OPC_VMAX_HU, OPC_VMAX_WU, OPC_VMAX_DU
1846 };
1847 static const LoongArchInsn ssadd_vec_insn[4] = {
1848 OPC_VSADD_B, OPC_VSADD_H, OPC_VSADD_W, OPC_VSADD_D
1849 };
1850 static const LoongArchInsn usadd_vec_insn[4] = {
1851 OPC_VSADD_BU, OPC_VSADD_HU, OPC_VSADD_WU, OPC_VSADD_DU
1852 };
1853 static const LoongArchInsn sssub_vec_insn[4] = {
1854 OPC_VSSUB_B, OPC_VSSUB_H, OPC_VSSUB_W, OPC_VSSUB_D
1855 };
1856 static const LoongArchInsn ussub_vec_insn[4] = {
1857 OPC_VSSUB_BU, OPC_VSSUB_HU, OPC_VSSUB_WU, OPC_VSSUB_DU
1858 };
1859 static const LoongArchInsn shlv_vec_insn[4] = {
1860 OPC_VSLL_B, OPC_VSLL_H, OPC_VSLL_W, OPC_VSLL_D
1861 };
1862 static const LoongArchInsn shrv_vec_insn[4] = {
1863 OPC_VSRL_B, OPC_VSRL_H, OPC_VSRL_W, OPC_VSRL_D
1864 };
1865 static const LoongArchInsn sarv_vec_insn[4] = {
1866 OPC_VSRA_B, OPC_VSRA_H, OPC_VSRA_W, OPC_VSRA_D
1867 };
1868 static const LoongArchInsn shli_vec_insn[4] = {
1869 OPC_VSLLI_B, OPC_VSLLI_H, OPC_VSLLI_W, OPC_VSLLI_D
1870 };
1871 static const LoongArchInsn shri_vec_insn[4] = {
1872 OPC_VSRLI_B, OPC_VSRLI_H, OPC_VSRLI_W, OPC_VSRLI_D
1873 };
1874 static const LoongArchInsn sari_vec_insn[4] = {
1875 OPC_VSRAI_B, OPC_VSRAI_H, OPC_VSRAI_W, OPC_VSRAI_D
1876 };
1877 static const LoongArchInsn rotrv_vec_insn[4] = {
1878 OPC_VROTR_B, OPC_VROTR_H, OPC_VROTR_W, OPC_VROTR_D
1879 };
1881 a0 = args[0];
1882 a1 = args[1];
1883 a2 = args[2];
1884 a3 = args[3];
1886 /* Currently only supports V64 & V128 */
1887 tcg_debug_assert(type == TCG_TYPE_V64 || type == TCG_TYPE_V128);
1889 switch (opc) {
1890 case INDEX_op_st_vec:
1891 tcg_out_st(s, type, a0, a1, a2);
1892 break;
1893 case INDEX_op_ld_vec:
1894 tcg_out_ld(s, type, a0, a1, a2);
1895 break;
1896 case INDEX_op_and_vec:
1897 tcg_out_opc_vand_v(s, a0, a1, a2);
1898 break;
1899 case INDEX_op_andc_vec:
1900 /*
1901 * vandn vd, vj, vk: vd = vk & ~vj
1902 * andc_vec vd, vj, vk: vd = vj & ~vk
1903 * vk and vk are swapped
1904 */
1905 tcg_out_opc_vandn_v(s, a0, a2, a1);
1906 break;
1907 case INDEX_op_or_vec:
1908 tcg_out_opc_vor_v(s, a0, a1, a2);
1909 break;
1910 case INDEX_op_orc_vec:
1911 tcg_out_opc_vorn_v(s, a0, a1, a2);
1912 break;
1913 case INDEX_op_xor_vec:
1914 tcg_out_opc_vxor_v(s, a0, a1, a2);
1915 break;
1916 case INDEX_op_nor_vec:
1917 tcg_out_opc_vnor_v(s, a0, a1, a2);
1918 break;
1919 case INDEX_op_not_vec:
1920 tcg_out_opc_vnor_v(s, a0, a1, a1);
1921 break;
1922 case INDEX_op_cmp_vec:
1923 {
1924 TCGCond cond = args[3];
1925 if (const_args[2]) {
1926 /*
1927 * cmp_vec dest, src, value
1928 * Try vseqi/vslei/vslti
1929 */
1930 int64_t value = sextract64(a2, 0, 8 << vece);
1931 if ((cond == TCG_COND_EQ || cond == TCG_COND_LE || \
1932 cond == TCG_COND_LT) && (-0x10 <= value && value <= 0x0f)) {
1933 tcg_out32(s, encode_vdvjsk5_insn(cmp_vec_imm_insn[cond][vece], \
1934 a0, a1, value));
1935 break;
1936 } else if ((cond == TCG_COND_LEU || cond == TCG_COND_LTU) &&
1937 (0x00 <= value && value <= 0x1f)) {
1938 tcg_out32(s, encode_vdvjuk5_insn(cmp_vec_imm_insn[cond][vece], \
1939 a0, a1, value));
1940 break;
1941 }
1943 /*
1944 * Fallback to:
1945 * dupi_vec temp, a2
1946 * cmp_vec a0, a1, temp, cond
1947 */
1948 tcg_out_dupi_vec(s, type, vece, temp_vec, a2);
1949 a2 = temp_vec;
1950 }
1952 insn = cmp_vec_insn[cond][vece];
1953 if (insn == 0) {
1954 TCGArg t;
1955 t = a1, a1 = a2, a2 = t;
1956 cond = tcg_swap_cond(cond);
1957 insn = cmp_vec_insn[cond][vece];
1958 tcg_debug_assert(insn != 0);
1959 }
1960 tcg_out32(s, encode_vdvjvk_insn(insn, a0, a1, a2));
1961 }
1962 break;
1963 case INDEX_op_add_vec:
1964 tcg_out_addsub_vec(s, vece, a0, a1, a2, const_args[2], true);
1965 break;
1966 case INDEX_op_sub_vec:
1967 tcg_out_addsub_vec(s, vece, a0, a1, a2, const_args[2], false);
1968 break;
1969 case INDEX_op_neg_vec:
1970 tcg_out32(s, encode_vdvj_insn(neg_vec_insn[vece], a0, a1));
1971 break;
1972 case INDEX_op_mul_vec:
1973 tcg_out32(s, encode_vdvjvk_insn(mul_vec_insn[vece], a0, a1, a2));
1974 break;
1975 case INDEX_op_smin_vec:
1976 tcg_out32(s, encode_vdvjvk_insn(smin_vec_insn[vece], a0, a1, a2));
1977 break;
1978 case INDEX_op_smax_vec:
1979 tcg_out32(s, encode_vdvjvk_insn(smax_vec_insn[vece], a0, a1, a2));
1980 break;
1981 case INDEX_op_umin_vec:
1982 tcg_out32(s, encode_vdvjvk_insn(umin_vec_insn[vece], a0, a1, a2));
1983 break;
1984 case INDEX_op_umax_vec:
1985 tcg_out32(s, encode_vdvjvk_insn(umax_vec_insn[vece], a0, a1, a2));
1986 break;
1987 case INDEX_op_ssadd_vec:
1988 tcg_out32(s, encode_vdvjvk_insn(ssadd_vec_insn[vece], a0, a1, a2));
1989 break;
1990 case INDEX_op_usadd_vec:
1991 tcg_out32(s, encode_vdvjvk_insn(usadd_vec_insn[vece], a0, a1, a2));
1992 break;
1993 case INDEX_op_sssub_vec:
1994 tcg_out32(s, encode_vdvjvk_insn(sssub_vec_insn[vece], a0, a1, a2));
1995 break;
1996 case INDEX_op_ussub_vec:
1997 tcg_out32(s, encode_vdvjvk_insn(ussub_vec_insn[vece], a0, a1, a2));
1998 break;
1999 case INDEX_op_shlv_vec:
2000 tcg_out32(s, encode_vdvjvk_insn(shlv_vec_insn[vece], a0, a1, a2));
2001 break;
2002 case INDEX_op_shrv_vec:
2003 tcg_out32(s, encode_vdvjvk_insn(shrv_vec_insn[vece], a0, a1, a2));
2004 break;
2005 case INDEX_op_sarv_vec:
2006 tcg_out32(s, encode_vdvjvk_insn(sarv_vec_insn[vece], a0, a1, a2));
2007 break;
2008 case INDEX_op_shli_vec:
2009 tcg_out32(s, encode_vdvjuk3_insn(shli_vec_insn[vece], a0, a1, a2));
2010 break;
2011 case INDEX_op_shri_vec:
2012 tcg_out32(s, encode_vdvjuk3_insn(shri_vec_insn[vece], a0, a1, a2));
2013 break;
2014 case INDEX_op_sari_vec:
2015 tcg_out32(s, encode_vdvjuk3_insn(sari_vec_insn[vece], a0, a1, a2));
2016 break;
2017 case INDEX_op_rotrv_vec:
2018 tcg_out32(s, encode_vdvjvk_insn(rotrv_vec_insn[vece], a0, a1, a2));
2019 break;
2020 case INDEX_op_rotlv_vec:
2021 /* rotlv_vec a1, a2 = rotrv_vec a1, -a2 */
2022 tcg_out32(s, encode_vdvj_insn(neg_vec_insn[vece], temp_vec, a2));
2023 tcg_out32(s, encode_vdvjvk_insn(rotrv_vec_insn[vece], a0, a1,
2024 temp_vec));
2025 break;
2026 case INDEX_op_rotli_vec:
2027 /* rotli_vec a1, a2 = rotri_vec a1, -a2 */
2028 a2 = extract32(-a2, 0, 3 + vece);
2029 switch (vece) {
2030 case MO_8:
2031 tcg_out_opc_vrotri_b(s, a0, a1, a2);
2032 break;
2033 case MO_16:
2034 tcg_out_opc_vrotri_h(s, a0, a1, a2);
2035 break;
2036 case MO_32:
2037 tcg_out_opc_vrotri_w(s, a0, a1, a2);
2038 break;
2039 case MO_64:
2040 tcg_out_opc_vrotri_d(s, a0, a1, a2);
2041 break;
2042 default:
2043 g_assert_not_reached();
2044 }
2045 break;
2046 case INDEX_op_bitsel_vec:
2047 /* vbitsel vd, vj, vk, va = bitsel_vec vd, va, vk, vj */
2048 tcg_out_opc_vbitsel_v(s, a0, a3, a2, a1);
2049 break;
2050 case INDEX_op_dupm_vec:
2051 tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
2052 break;
2053 default:
2054 g_assert_not_reached();
2055 }
2056 }
2058 int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
2059 {
2060 switch (opc) {
2061 case INDEX_op_ld_vec:
2062 case INDEX_op_st_vec:
2063 case INDEX_op_dup_vec:
2064 case INDEX_op_dupm_vec:
2065 case INDEX_op_cmp_vec:
2066 case INDEX_op_add_vec:
2067 case INDEX_op_sub_vec:
2068 case INDEX_op_and_vec:
2069 case INDEX_op_andc_vec:
2070 case INDEX_op_or_vec:
2071 case INDEX_op_orc_vec:
2072 case INDEX_op_xor_vec:
2073 case INDEX_op_nor_vec:
2074 case INDEX_op_not_vec:
2075 case INDEX_op_neg_vec:
2076 case INDEX_op_mul_vec:
2077 case INDEX_op_smin_vec:
2078 case INDEX_op_smax_vec:
2079 case INDEX_op_umin_vec:
2080 case INDEX_op_umax_vec:
2081 case INDEX_op_ssadd_vec:
2082 case INDEX_op_usadd_vec:
2083 case INDEX_op_sssub_vec:
2084 case INDEX_op_ussub_vec:
2085 case INDEX_op_shlv_vec:
2086 case INDEX_op_shrv_vec:
2087 case INDEX_op_sarv_vec:
2088 case INDEX_op_bitsel_vec:
2089 return 1;
2090 default:
2091 return 0;
2092 }
2093 }
2095 void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
2096 TCGArg a0, ...)
2097 {
2098 g_assert_not_reached();
2099 }
2101 static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
2102 {
2103 switch (op) {
2104 case INDEX_op_goto_ptr:
2105 return C_O0_I1(r);
2107 case INDEX_op_st8_i32:
2108 case INDEX_op_st8_i64:
2109 case INDEX_op_st16_i32:
2110 case INDEX_op_st16_i64:
2111 case INDEX_op_st32_i64:
2112 case INDEX_op_st_i32:
2113 case INDEX_op_st_i64:
2114 case INDEX_op_qemu_st_a32_i32:
2115 case INDEX_op_qemu_st_a64_i32:
2116 case INDEX_op_qemu_st_a32_i64:
2117 case INDEX_op_qemu_st_a64_i64:
2118 return C_O0_I2(rZ, r);
2120 case INDEX_op_qemu_ld_a32_i128:
2121 case INDEX_op_qemu_ld_a64_i128:
2122 return C_N2_I1(r, r, r);
2124 case INDEX_op_qemu_st_a32_i128:
2125 case INDEX_op_qemu_st_a64_i128:
2126 return C_O0_I3(r, r, r);
2128 case INDEX_op_brcond_i32:
2129 case INDEX_op_brcond_i64:
2130 return C_O0_I2(rZ, rZ);
2132 case INDEX_op_ext8s_i32:
2133 case INDEX_op_ext8s_i64:
2134 case INDEX_op_ext8u_i32:
2135 case INDEX_op_ext8u_i64:
2136 case INDEX_op_ext16s_i32:
2137 case INDEX_op_ext16s_i64:
2138 case INDEX_op_ext16u_i32:
2139 case INDEX_op_ext16u_i64:
2140 case INDEX_op_ext32s_i64:
2141 case INDEX_op_ext32u_i64:
2142 case INDEX_op_extu_i32_i64:
2143 case INDEX_op_extrl_i64_i32:
2144 case INDEX_op_extrh_i64_i32:
2145 case INDEX_op_ext_i32_i64:
2146 case INDEX_op_neg_i32:
2147 case INDEX_op_neg_i64:
2148 case INDEX_op_not_i32:
2149 case INDEX_op_not_i64:
2150 case INDEX_op_extract_i32:
2151 case INDEX_op_extract_i64:
2152 case INDEX_op_bswap16_i32:
2153 case INDEX_op_bswap16_i64:
2154 case INDEX_op_bswap32_i32:
2155 case INDEX_op_bswap32_i64:
2156 case INDEX_op_bswap64_i64:
2157 case INDEX_op_ld8s_i32:
2158 case INDEX_op_ld8s_i64:
2159 case INDEX_op_ld8u_i32:
2160 case INDEX_op_ld8u_i64:
2161 case INDEX_op_ld16s_i32:
2162 case INDEX_op_ld16s_i64:
2163 case INDEX_op_ld16u_i32:
2164 case INDEX_op_ld16u_i64:
2165 case INDEX_op_ld32s_i64:
2166 case INDEX_op_ld32u_i64:
2167 case INDEX_op_ld_i32:
2168 case INDEX_op_ld_i64:
2169 case INDEX_op_qemu_ld_a32_i32:
2170 case INDEX_op_qemu_ld_a64_i32:
2171 case INDEX_op_qemu_ld_a32_i64:
2172 case INDEX_op_qemu_ld_a64_i64:
2173 return C_O1_I1(r, r);
2175 case INDEX_op_andc_i32:
2176 case INDEX_op_andc_i64:
2177 case INDEX_op_orc_i32:
2178 case INDEX_op_orc_i64:
2179 /*
2180 * LoongArch insns for these ops don't have reg-imm forms, but we
2181 * can express using andi/ori if ~constant satisfies
2182 * TCG_CT_CONST_U12.
2183 */
2184 return C_O1_I2(r, r, rC);
2186 case INDEX_op_shl_i32:
2187 case INDEX_op_shl_i64:
2188 case INDEX_op_shr_i32:
2189 case INDEX_op_shr_i64:
2190 case INDEX_op_sar_i32:
2191 case INDEX_op_sar_i64:
2192 case INDEX_op_rotl_i32:
2193 case INDEX_op_rotl_i64:
2194 case INDEX_op_rotr_i32:
2195 case INDEX_op_rotr_i64:
2196 return C_O1_I2(r, r, ri);
2198 case INDEX_op_add_i32:
2199 return C_O1_I2(r, r, ri);
2200 case INDEX_op_add_i64:
2201 return C_O1_I2(r, r, rJ);
2203 case INDEX_op_and_i32:
2204 case INDEX_op_and_i64:
2205 case INDEX_op_nor_i32:
2206 case INDEX_op_nor_i64:
2207 case INDEX_op_or_i32:
2208 case INDEX_op_or_i64:
2209 case INDEX_op_xor_i32:
2210 case INDEX_op_xor_i64:
2211 /* LoongArch reg-imm bitops have their imms ZERO-extended */
2212 return C_O1_I2(r, r, rU);
2214 case INDEX_op_clz_i32:
2215 case INDEX_op_clz_i64:
2216 case INDEX_op_ctz_i32:
2217 case INDEX_op_ctz_i64:
2218 return C_O1_I2(r, r, rW);
2220 case INDEX_op_deposit_i32:
2221 case INDEX_op_deposit_i64:
2222 /* Must deposit into the same register as input */
2223 return C_O1_I2(r, 0, rZ);
2225 case INDEX_op_sub_i32:
2226 case INDEX_op_setcond_i32:
2227 return C_O1_I2(r, rZ, ri);
2228 case INDEX_op_sub_i64:
2229 case INDEX_op_setcond_i64:
2230 return C_O1_I2(r, rZ, rJ);
2232 case INDEX_op_mul_i32:
2233 case INDEX_op_mul_i64:
2234 case INDEX_op_mulsh_i32:
2235 case INDEX_op_mulsh_i64:
2236 case INDEX_op_muluh_i32:
2237 case INDEX_op_muluh_i64:
2238 case INDEX_op_div_i32:
2239 case INDEX_op_div_i64:
2240 case INDEX_op_divu_i32:
2241 case INDEX_op_divu_i64:
2242 case INDEX_op_rem_i32:
2243 case INDEX_op_rem_i64:
2244 case INDEX_op_remu_i32:
2245 case INDEX_op_remu_i64:
2246 return C_O1_I2(r, rZ, rZ);
2248 case INDEX_op_movcond_i32:
2249 case INDEX_op_movcond_i64:
2250 return C_O1_I4(r, rZ, rJ, rZ, rZ);
2252 case INDEX_op_ld_vec:
2253 case INDEX_op_dupm_vec:
2254 case INDEX_op_dup_vec:
2255 return C_O1_I1(w, r);
2257 case INDEX_op_st_vec:
2258 return C_O0_I2(w, r);
2260 case INDEX_op_cmp_vec:
2261 return C_O1_I2(w, w, wM);
2263 case INDEX_op_add_vec:
2264 case INDEX_op_sub_vec:
2265 return C_O1_I2(w, w, wA);
2267 case INDEX_op_and_vec:
2268 case INDEX_op_andc_vec:
2269 case INDEX_op_or_vec:
2270 case INDEX_op_orc_vec:
2271 case INDEX_op_xor_vec:
2272 case INDEX_op_nor_vec:
2273 case INDEX_op_mul_vec:
2274 case INDEX_op_smin_vec:
2275 case INDEX_op_smax_vec:
2276 case INDEX_op_umin_vec:
2277 case INDEX_op_umax_vec:
2278 case INDEX_op_ssadd_vec:
2279 case INDEX_op_usadd_vec:
2280 case INDEX_op_sssub_vec:
2281 case INDEX_op_ussub_vec:
2282 case INDEX_op_shlv_vec:
2283 case INDEX_op_shrv_vec:
2284 case INDEX_op_sarv_vec:
2285 case INDEX_op_rotrv_vec:
2286 case INDEX_op_rotlv_vec:
2287 return C_O1_I2(w, w, w);
2289 case INDEX_op_not_vec:
2290 case INDEX_op_neg_vec:
2291 case INDEX_op_shli_vec:
2292 case INDEX_op_shri_vec:
2293 case INDEX_op_sari_vec:
2294 case INDEX_op_rotli_vec:
2295 return C_O1_I1(w, w);
2297 case INDEX_op_bitsel_vec:
2298 return C_O1_I3(w, w, w, w);
2300 default:
2301 g_assert_not_reached();
2302 }
2303 }
2305 static const int tcg_target_callee_save_regs[] = {
2306 TCG_REG_S0, /* used for the global env (TCG_AREG0) */
2307 TCG_REG_S1,
2308 TCG_REG_S2,
2309 TCG_REG_S3,
2310 TCG_REG_S4,
2311 TCG_REG_S5,
2312 TCG_REG_S6,
2313 TCG_REG_S7,
2314 TCG_REG_S8,
2315 TCG_REG_S9,
2316 TCG_REG_RA, /* should be last for ABI compliance */
2317 };
2319 /* Stack frame parameters. */
2320 #define REG_SIZE (TCG_TARGET_REG_BITS / 8)
2321 #define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE)
2322 #define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
2323 #define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \
2324 + TCG_TARGET_STACK_ALIGN - 1) \
2325 & -TCG_TARGET_STACK_ALIGN)
2326 #define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE)
2328 /* We're expecting to be able to use an immediate for frame allocation. */
2329 QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7ff);
2331 /* Generate global QEMU prologue and epilogue code */
2332 static void tcg_target_qemu_prologue(TCGContext *s)
2333 {
2334 int i;
2336 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE);
2338 /* TB prologue */
2339 tcg_out_opc_addi_d(s, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE);
2340 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
2341 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
2342 TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
2343 }
2345 if (!tcg_use_softmmu && guest_base) {
2346 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
2347 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
2348 }
2350 /* Call generated code */
2351 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
2352 tcg_out_opc_jirl(s, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0);
2354 /* Return path for goto_ptr. Set return value to 0 */
2355 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr);
2356 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_A0, TCG_REG_ZERO);
2358 /* TB epilogue */
2359 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr);
2360 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
2361 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
2362 TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
2363 }
2365 tcg_out_opc_addi_d(s, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE);
2366 tcg_out_opc_jirl(s, TCG_REG_ZERO, TCG_REG_RA, 0);
2367 }
2369 static void tcg_out_tb_start(TCGContext *s)
2370 {
2371 /* nothing to do */
2372 }
2374 static void tcg_target_init(TCGContext *s)
2375 {
2376 unsigned long hwcap = qemu_getauxval(AT_HWCAP);
2378 /* Server and desktop class cpus have UAL; embedded cpus do not. */
2379 if (!(hwcap & HWCAP_LOONGARCH_UAL)) {
2380 error_report("TCG: unaligned access support required; exiting");
2381 exit(EXIT_FAILURE);
2382 }
2384 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;
2385 tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS;
2387 tcg_target_call_clobber_regs = ALL_GENERAL_REGS | ALL_VECTOR_REGS;
2388 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0);
2389 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S1);
2390 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S2);
2391 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S3);
2392 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S4);
2393 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S5);
2394 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S6);
2395 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S7);
2396 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S8);
2397 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S9);
2399 if (cpuinfo & CPUINFO_LSX) {
2400 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS;
2401 tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS;
2402 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V24);
2403 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V25);
2404 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V26);
2405 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V27);
2406 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V28);
2407 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V29);
2408 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V30);
2409 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V31);
2410 }
2412 s->reserved_regs = 0;
2413 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO);
2414 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP0);
2415 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1);
2416 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2);
2417 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP);
2418 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TP);
2419 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RESERVED);
2420 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP0);
2421 }
2423 typedef struct {
2424 DebugFrameHeader h;
2425 uint8_t fde_def_cfa[4];
2426 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2];
2427 } DebugFrame;
2429 #define ELF_HOST_MACHINE EM_LOONGARCH
2431 static const DebugFrame debug_frame = {
2432 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */
2433 .h.cie.id = -1,
2434 .h.cie.version = 1,
2435 .h.cie.code_align = 1,
2436 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */
2437 .h.cie.return_column = TCG_REG_RA,
2439 /* Total FDE size does not include the "len" member. */
2440 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
2442 .fde_def_cfa = {
2443 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */
2444 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2445 (FRAME_SIZE >> 7)
2446 },
2447 .fde_reg_ofs = {
2448 0x80 + 23, 11, /* DW_CFA_offset, s0, -88 */
2449 0x80 + 24, 10, /* DW_CFA_offset, s1, -80 */
2450 0x80 + 25, 9, /* DW_CFA_offset, s2, -72 */
2451 0x80 + 26, 8, /* DW_CFA_offset, s3, -64 */
2452 0x80 + 27, 7, /* DW_CFA_offset, s4, -56 */
2453 0x80 + 28, 6, /* DW_CFA_offset, s5, -48 */
2454 0x80 + 29, 5, /* DW_CFA_offset, s6, -40 */
2455 0x80 + 30, 4, /* DW_CFA_offset, s7, -32 */
2456 0x80 + 31, 3, /* DW_CFA_offset, s8, -24 */
2457 0x80 + 22, 2, /* DW_CFA_offset, s9, -16 */
2458 0x80 + 1 , 1, /* DW_CFA_offset, ra, -8 */
2459 }
2460 };
2462 void tcg_register_jit(const void *buf, size_t buf_size)
2463 {
2464 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
2465 }