4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
21 #include "qemu/osdep.h"
22 #include "qemu/qemu-print.h"
23 #include "qemu-common.h"
24 #include "target/arm/idau.h"
25 #include "qemu/module.h"
26 #include "qapi/error.h"
27 #include "qapi/visitor.h"
30 #include "hw/core/tcg-cpu-ops.h"
31 #endif /* CONFIG_TCG */
32 #include "internals.h"
33 #include "exec/exec-all.h"
34 #include "hw/qdev-properties.h"
35 #if !defined(CONFIG_USER_ONLY)
36 #include "hw/loader.h"
37 #include "hw/boards.h"
39 #include "sysemu/tcg.h"
40 #include "sysemu/hw_accel.h"
42 #include "disas/capstone.h"
43 #include "fpu/softfloat.h"
45 static void arm_cpu_set_pc(CPUState
*cs
, vaddr value
)
47 ARMCPU
*cpu
= ARM_CPU(cs
);
48 CPUARMState
*env
= &cpu
->env
;
54 env
->regs
[15] = value
& ~1;
55 env
->thumb
= value
& 1;
60 void arm_cpu_synchronize_from_tb(CPUState
*cs
,
61 const TranslationBlock
*tb
)
63 ARMCPU
*cpu
= ARM_CPU(cs
);
64 CPUARMState
*env
= &cpu
->env
;
67 * It's OK to look at env for the current mode here, because it's
68 * never possible for an AArch64 TB to chain to an AArch32 TB.
73 env
->regs
[15] = tb
->pc
;
76 #endif /* CONFIG_TCG */
78 static bool arm_cpu_has_work(CPUState
*cs
)
80 ARMCPU
*cpu
= ARM_CPU(cs
);
82 return (cpu
->power_state
!= PSCI_OFF
)
83 && cs
->interrupt_request
&
84 (CPU_INTERRUPT_FIQ
| CPU_INTERRUPT_HARD
85 | CPU_INTERRUPT_VFIQ
| CPU_INTERRUPT_VIRQ
86 | CPU_INTERRUPT_EXITTB
);
89 void arm_register_pre_el_change_hook(ARMCPU
*cpu
, ARMELChangeHookFn
*hook
,
92 ARMELChangeHook
*entry
= g_new0(ARMELChangeHook
, 1);
95 entry
->opaque
= opaque
;
97 QLIST_INSERT_HEAD(&cpu
->pre_el_change_hooks
, entry
, node
);
100 void arm_register_el_change_hook(ARMCPU
*cpu
, ARMELChangeHookFn
*hook
,
103 ARMELChangeHook
*entry
= g_new0(ARMELChangeHook
, 1);
106 entry
->opaque
= opaque
;
108 QLIST_INSERT_HEAD(&cpu
->el_change_hooks
, entry
, node
);
111 static void cp_reg_reset(gpointer key
, gpointer value
, gpointer opaque
)
113 /* Reset a single ARMCPRegInfo register */
114 ARMCPRegInfo
*ri
= value
;
115 ARMCPU
*cpu
= opaque
;
117 if (ri
->type
& (ARM_CP_SPECIAL
| ARM_CP_ALIAS
)) {
122 ri
->resetfn(&cpu
->env
, ri
);
126 /* A zero offset is never possible as it would be regs[0]
127 * so we use it to indicate that reset is being handled elsewhere.
128 * This is basically only used for fields in non-core coprocessors
129 * (like the pxa2xx ones).
131 if (!ri
->fieldoffset
) {
135 if (cpreg_field_is_64bit(ri
)) {
136 CPREG_FIELD64(&cpu
->env
, ri
) = ri
->resetvalue
;
138 CPREG_FIELD32(&cpu
->env
, ri
) = ri
->resetvalue
;
142 static void cp_reg_check_reset(gpointer key
, gpointer value
, gpointer opaque
)
144 /* Purely an assertion check: we've already done reset once,
145 * so now check that running the reset for the cpreg doesn't
146 * change its value. This traps bugs where two different cpregs
147 * both try to reset the same state field but to different values.
149 ARMCPRegInfo
*ri
= value
;
150 ARMCPU
*cpu
= opaque
;
151 uint64_t oldvalue
, newvalue
;
153 if (ri
->type
& (ARM_CP_SPECIAL
| ARM_CP_ALIAS
| ARM_CP_NO_RAW
)) {
157 oldvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
158 cp_reg_reset(key
, value
, opaque
);
159 newvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
160 assert(oldvalue
== newvalue
);
163 static void arm_cpu_reset(DeviceState
*dev
)
165 CPUState
*s
= CPU(dev
);
166 ARMCPU
*cpu
= ARM_CPU(s
);
167 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(cpu
);
168 CPUARMState
*env
= &cpu
->env
;
170 acc
->parent_reset(dev
);
172 memset(env
, 0, offsetof(CPUARMState
, end_reset_fields
));
174 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_reset
, cpu
);
175 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_check_reset
, cpu
);
177 env
->vfp
.xregs
[ARM_VFP_FPSID
] = cpu
->reset_fpsid
;
178 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = cpu
->isar
.mvfr0
;
179 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = cpu
->isar
.mvfr1
;
180 env
->vfp
.xregs
[ARM_VFP_MVFR2
] = cpu
->isar
.mvfr2
;
182 cpu
->power_state
= s
->start_powered_off
? PSCI_OFF
: PSCI_ON
;
184 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
185 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
188 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
189 /* 64 bit CPUs always start in 64 bit mode */
191 #if defined(CONFIG_USER_ONLY)
192 env
->pstate
= PSTATE_MODE_EL0t
;
193 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
194 env
->cp15
.sctlr_el
[1] |= SCTLR_UCT
| SCTLR_UCI
| SCTLR_DZE
;
195 /* Enable all PAC keys. */
196 env
->cp15
.sctlr_el
[1] |= (SCTLR_EnIA
| SCTLR_EnIB
|
197 SCTLR_EnDA
| SCTLR_EnDB
);
198 /* and to the FP/Neon instructions */
199 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 2, 3);
200 /* and to the SVE instructions */
201 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 16, 2, 3);
202 /* with reasonable vector length */
203 if (cpu_isar_feature(aa64_sve
, cpu
)) {
205 aarch64_sve_zcr_get_valid_len(cpu
, cpu
->sve_default_vq
- 1);
208 * Enable TBI0 but not TBI1.
209 * Note that this must match useronly_clean_ptr.
211 env
->cp15
.tcr_el
[1].raw_tcr
= (1ULL << 37);
214 if (cpu_isar_feature(aa64_mte
, cpu
)) {
215 /* Enable tag access, but leave TCF0 as No Effect (0). */
216 env
->cp15
.sctlr_el
[1] |= SCTLR_ATA0
;
218 * Exclude all tags, so that tag 0 is always used.
219 * This corresponds to Linux current->thread.gcr_incl = 0.
221 * Set RRND, so that helper_irg() will generate a seed later.
222 * Here in cpu_reset(), the crypto subsystem has not yet been
225 env
->cp15
.gcr_el1
= 0x1ffff;
228 /* Reset into the highest available EL */
229 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
230 env
->pstate
= PSTATE_MODE_EL3h
;
231 } else if (arm_feature(env
, ARM_FEATURE_EL2
)) {
232 env
->pstate
= PSTATE_MODE_EL2h
;
234 env
->pstate
= PSTATE_MODE_EL1h
;
236 env
->pc
= cpu
->rvbar
;
239 #if defined(CONFIG_USER_ONLY)
240 /* Userspace expects access to cp10 and cp11 for FP/Neon */
241 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 4, 0xf);
245 #if defined(CONFIG_USER_ONLY)
246 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
247 /* For user mode we must enable access to coprocessors */
248 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
249 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
250 env
->cp15
.c15_cpar
= 3;
251 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
252 env
->cp15
.c15_cpar
= 1;
257 * If the highest available EL is EL2, AArch32 will start in Hyp
258 * mode; otherwise it starts in SVC. Note that if we start in
259 * AArch64 then these values in the uncached_cpsr will be ignored.
261 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
262 !arm_feature(env
, ARM_FEATURE_EL3
)) {
263 env
->uncached_cpsr
= ARM_CPU_MODE_HYP
;
265 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
;
267 env
->daif
= PSTATE_D
| PSTATE_A
| PSTATE_I
| PSTATE_F
;
269 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
270 * executing as AArch32 then check if highvecs are enabled and
271 * adjust the PC accordingly.
273 if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
274 env
->regs
[15] = 0xFFFF0000;
277 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
280 if (arm_feature(env
, ARM_FEATURE_M
)) {
281 #ifndef CONFIG_USER_ONLY
282 uint32_t initial_msp
; /* Loaded from 0x0 */
283 uint32_t initial_pc
; /* Loaded from 0x4 */
288 if (cpu_isar_feature(aa32_lob
, cpu
)) {
290 * LTPSIZE is constant 4 if MVE not implemented, and resets
291 * to an UNKNOWN value if MVE is implemented. We choose to
294 env
->v7m
.ltpsize
= 4;
295 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */
296 env
->v7m
.fpdscr
[M_REG_NS
] = 4 << FPCR_LTPSIZE_SHIFT
;
297 env
->v7m
.fpdscr
[M_REG_S
] = 4 << FPCR_LTPSIZE_SHIFT
;
300 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
301 env
->v7m
.secure
= true;
303 /* This bit resets to 0 if security is supported, but 1 if
304 * it is not. The bit is not present in v7M, but we set it
305 * here so we can avoid having to make checks on it conditional
306 * on ARM_FEATURE_V8 (we don't let the guest see the bit).
308 env
->v7m
.aircr
= R_V7M_AIRCR_BFHFNMINS_MASK
;
310 * Set NSACR to indicate "NS access permitted to everything";
311 * this avoids having to have all the tests of it being
312 * conditional on ARM_FEATURE_M_SECURITY. Note also that from
313 * v8.1M the guest-visible value of NSACR in a CPU without the
314 * Security Extension is 0xcff.
316 env
->v7m
.nsacr
= 0xcff;
319 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends
320 * that it resets to 1, so QEMU always does that rather than making
321 * it dependent on CPU model. In v8M it is RES1.
323 env
->v7m
.ccr
[M_REG_NS
] = R_V7M_CCR_STKALIGN_MASK
;
324 env
->v7m
.ccr
[M_REG_S
] = R_V7M_CCR_STKALIGN_MASK
;
325 if (arm_feature(env
, ARM_FEATURE_V8
)) {
326 /* in v8M the NONBASETHRDENA bit [0] is RES1 */
327 env
->v7m
.ccr
[M_REG_NS
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
328 env
->v7m
.ccr
[M_REG_S
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
330 if (!arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
331 env
->v7m
.ccr
[M_REG_NS
] |= R_V7M_CCR_UNALIGN_TRP_MASK
;
332 env
->v7m
.ccr
[M_REG_S
] |= R_V7M_CCR_UNALIGN_TRP_MASK
;
335 if (cpu_isar_feature(aa32_vfp_simd
, cpu
)) {
336 env
->v7m
.fpccr
[M_REG_NS
] = R_V7M_FPCCR_ASPEN_MASK
;
337 env
->v7m
.fpccr
[M_REG_S
] = R_V7M_FPCCR_ASPEN_MASK
|
338 R_V7M_FPCCR_LSPEN_MASK
| R_V7M_FPCCR_S_MASK
;
341 #ifndef CONFIG_USER_ONLY
342 /* Unlike A/R profile, M profile defines the reset LR value */
343 env
->regs
[14] = 0xffffffff;
345 env
->v7m
.vecbase
[M_REG_S
] = cpu
->init_svtor
& 0xffffff80;
346 env
->v7m
.vecbase
[M_REG_NS
] = cpu
->init_nsvtor
& 0xffffff80;
348 /* Load the initial SP and PC from offset 0 and 4 in the vector table */
349 vecbase
= env
->v7m
.vecbase
[env
->v7m
.secure
];
350 rom
= rom_ptr_for_as(s
->as
, vecbase
, 8);
352 /* Address zero is covered by ROM which hasn't yet been
353 * copied into physical memory.
355 initial_msp
= ldl_p(rom
);
356 initial_pc
= ldl_p(rom
+ 4);
358 /* Address zero not covered by a ROM blob, or the ROM blob
359 * is in non-modifiable memory and this is a second reset after
360 * it got copied into memory. In the latter case, rom_ptr
361 * will return a NULL pointer and we should use ldl_phys instead.
363 initial_msp
= ldl_phys(s
->as
, vecbase
);
364 initial_pc
= ldl_phys(s
->as
, vecbase
+ 4);
367 env
->regs
[13] = initial_msp
& 0xFFFFFFFC;
368 env
->regs
[15] = initial_pc
& ~1;
369 env
->thumb
= initial_pc
& 1;
372 * For user mode we run non-secure and with access to the FPU.
373 * The FPU context is active (ie does not need further setup)
374 * and is owned by non-secure.
376 env
->v7m
.secure
= false;
377 env
->v7m
.nsacr
= 0xcff;
378 env
->v7m
.cpacr
[M_REG_NS
] = 0xf0ffff;
379 env
->v7m
.fpccr
[M_REG_S
] &=
380 ~(R_V7M_FPCCR_LSPEN_MASK
| R_V7M_FPCCR_S_MASK
);
381 env
->v7m
.control
[M_REG_S
] |= R_V7M_CONTROL_FPCA_MASK
;
385 /* M profile requires that reset clears the exclusive monitor;
386 * A profile does not, but clearing it makes more sense than having it
387 * set with an exclusive access on address zero.
389 arm_clear_exclusive(env
);
391 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
392 if (cpu
->pmsav7_dregion
> 0) {
393 if (arm_feature(env
, ARM_FEATURE_V8
)) {
394 memset(env
->pmsav8
.rbar
[M_REG_NS
], 0,
395 sizeof(*env
->pmsav8
.rbar
[M_REG_NS
])
396 * cpu
->pmsav7_dregion
);
397 memset(env
->pmsav8
.rlar
[M_REG_NS
], 0,
398 sizeof(*env
->pmsav8
.rlar
[M_REG_NS
])
399 * cpu
->pmsav7_dregion
);
400 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
401 memset(env
->pmsav8
.rbar
[M_REG_S
], 0,
402 sizeof(*env
->pmsav8
.rbar
[M_REG_S
])
403 * cpu
->pmsav7_dregion
);
404 memset(env
->pmsav8
.rlar
[M_REG_S
], 0,
405 sizeof(*env
->pmsav8
.rlar
[M_REG_S
])
406 * cpu
->pmsav7_dregion
);
408 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
409 memset(env
->pmsav7
.drbar
, 0,
410 sizeof(*env
->pmsav7
.drbar
) * cpu
->pmsav7_dregion
);
411 memset(env
->pmsav7
.drsr
, 0,
412 sizeof(*env
->pmsav7
.drsr
) * cpu
->pmsav7_dregion
);
413 memset(env
->pmsav7
.dracr
, 0,
414 sizeof(*env
->pmsav7
.dracr
) * cpu
->pmsav7_dregion
);
417 env
->pmsav7
.rnr
[M_REG_NS
] = 0;
418 env
->pmsav7
.rnr
[M_REG_S
] = 0;
419 env
->pmsav8
.mair0
[M_REG_NS
] = 0;
420 env
->pmsav8
.mair0
[M_REG_S
] = 0;
421 env
->pmsav8
.mair1
[M_REG_NS
] = 0;
422 env
->pmsav8
.mair1
[M_REG_S
] = 0;
425 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
426 if (cpu
->sau_sregion
> 0) {
427 memset(env
->sau
.rbar
, 0, sizeof(*env
->sau
.rbar
) * cpu
->sau_sregion
);
428 memset(env
->sau
.rlar
, 0, sizeof(*env
->sau
.rlar
) * cpu
->sau_sregion
);
431 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what
432 * the Cortex-M33 does.
437 set_flush_to_zero(1, &env
->vfp
.standard_fp_status
);
438 set_flush_inputs_to_zero(1, &env
->vfp
.standard_fp_status
);
439 set_default_nan_mode(1, &env
->vfp
.standard_fp_status
);
440 set_default_nan_mode(1, &env
->vfp
.standard_fp_status_f16
);
441 set_float_detect_tininess(float_tininess_before_rounding
,
442 &env
->vfp
.fp_status
);
443 set_float_detect_tininess(float_tininess_before_rounding
,
444 &env
->vfp
.standard_fp_status
);
445 set_float_detect_tininess(float_tininess_before_rounding
,
446 &env
->vfp
.fp_status_f16
);
447 set_float_detect_tininess(float_tininess_before_rounding
,
448 &env
->vfp
.standard_fp_status_f16
);
449 #ifndef CONFIG_USER_ONLY
451 kvm_arm_reset_vcpu(cpu
);
455 hw_breakpoint_update_all(cpu
);
456 hw_watchpoint_update_all(cpu
);
457 arm_rebuild_hflags(env
);
460 #ifndef CONFIG_USER_ONLY
462 static inline bool arm_excp_unmasked(CPUState
*cs
, unsigned int excp_idx
,
463 unsigned int target_el
,
464 unsigned int cur_el
, bool secure
,
467 CPUARMState
*env
= cs
->env_ptr
;
468 bool pstate_unmasked
;
469 bool unmasked
= false;
472 * Don't take exceptions if they target a lower EL.
473 * This check should catch any exceptions that would not be taken
476 if (cur_el
> target_el
) {
482 pstate_unmasked
= !(env
->daif
& PSTATE_F
);
486 pstate_unmasked
= !(env
->daif
& PSTATE_I
);
490 if (!(hcr_el2
& HCR_FMO
) || (hcr_el2
& HCR_TGE
)) {
491 /* VFIQs are only taken when hypervized. */
494 return !(env
->daif
& PSTATE_F
);
496 if (!(hcr_el2
& HCR_IMO
) || (hcr_el2
& HCR_TGE
)) {
497 /* VIRQs are only taken when hypervized. */
500 return !(env
->daif
& PSTATE_I
);
502 g_assert_not_reached();
506 * Use the target EL, current execution state and SCR/HCR settings to
507 * determine whether the corresponding CPSR bit is used to mask the
510 if ((target_el
> cur_el
) && (target_el
!= 1)) {
511 /* Exceptions targeting a higher EL may not be maskable */
512 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
514 * 64-bit masking rules are simple: exceptions to EL3
515 * can't be masked, and exceptions to EL2 can only be
516 * masked from Secure state. The HCR and SCR settings
517 * don't affect the masking logic, only the interrupt routing.
519 if (target_el
== 3 || !secure
|| (env
->cp15
.scr_el3
& SCR_EEL2
)) {
524 * The old 32-bit-only environment has a more complicated
525 * masking setup. HCR and SCR bits not only affect interrupt
526 * routing but also change the behaviour of masking.
533 * If FIQs are routed to EL3 or EL2 then there are cases where
534 * we override the CPSR.F in determining if the exception is
535 * masked or not. If neither of these are set then we fall back
536 * to the CPSR.F setting otherwise we further assess the state
539 hcr
= hcr_el2
& HCR_FMO
;
540 scr
= (env
->cp15
.scr_el3
& SCR_FIQ
);
543 * When EL3 is 32-bit, the SCR.FW bit controls whether the
544 * CPSR.F bit masks FIQ interrupts when taken in non-secure
545 * state. If SCR.FW is set then FIQs can be masked by CPSR.F
546 * when non-secure but only when FIQs are only routed to EL3.
548 scr
= scr
&& !((env
->cp15
.scr_el3
& SCR_FW
) && !hcr
);
552 * When EL3 execution state is 32-bit, if HCR.IMO is set then
553 * we may override the CPSR.I masking when in non-secure state.
554 * The SCR.IRQ setting has already been taken into consideration
555 * when setting the target EL, so it does not have a further
558 hcr
= hcr_el2
& HCR_IMO
;
562 g_assert_not_reached();
565 if ((scr
|| hcr
) && !secure
) {
572 * The PSTATE bits only mask the interrupt if we have not overriden the
575 return unmasked
|| pstate_unmasked
;
578 static bool arm_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
580 CPUClass
*cc
= CPU_GET_CLASS(cs
);
581 CPUARMState
*env
= cs
->env_ptr
;
582 uint32_t cur_el
= arm_current_el(env
);
583 bool secure
= arm_is_secure(env
);
584 uint64_t hcr_el2
= arm_hcr_el2_eff(env
);
588 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */
590 if (interrupt_request
& CPU_INTERRUPT_FIQ
) {
592 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
593 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
594 cur_el
, secure
, hcr_el2
)) {
598 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
600 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
601 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
602 cur_el
, secure
, hcr_el2
)) {
606 if (interrupt_request
& CPU_INTERRUPT_VIRQ
) {
607 excp_idx
= EXCP_VIRQ
;
609 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
610 cur_el
, secure
, hcr_el2
)) {
614 if (interrupt_request
& CPU_INTERRUPT_VFIQ
) {
615 excp_idx
= EXCP_VFIQ
;
617 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
618 cur_el
, secure
, hcr_el2
)) {
625 cs
->exception_index
= excp_idx
;
626 env
->exception
.target_el
= target_el
;
627 cc
->tcg_ops
->do_interrupt(cs
);
630 #endif /* !CONFIG_USER_ONLY */
632 void arm_cpu_update_virq(ARMCPU
*cpu
)
635 * Update the interrupt level for VIRQ, which is the logical OR of
636 * the HCR_EL2.VI bit and the input line level from the GIC.
638 CPUARMState
*env
= &cpu
->env
;
639 CPUState
*cs
= CPU(cpu
);
641 bool new_state
= (env
->cp15
.hcr_el2
& HCR_VI
) ||
642 (env
->irq_line_state
& CPU_INTERRUPT_VIRQ
);
644 if (new_state
!= ((cs
->interrupt_request
& CPU_INTERRUPT_VIRQ
) != 0)) {
646 cpu_interrupt(cs
, CPU_INTERRUPT_VIRQ
);
648 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VIRQ
);
653 void arm_cpu_update_vfiq(ARMCPU
*cpu
)
656 * Update the interrupt level for VFIQ, which is the logical OR of
657 * the HCR_EL2.VF bit and the input line level from the GIC.
659 CPUARMState
*env
= &cpu
->env
;
660 CPUState
*cs
= CPU(cpu
);
662 bool new_state
= (env
->cp15
.hcr_el2
& HCR_VF
) ||
663 (env
->irq_line_state
& CPU_INTERRUPT_VFIQ
);
665 if (new_state
!= ((cs
->interrupt_request
& CPU_INTERRUPT_VFIQ
) != 0)) {
667 cpu_interrupt(cs
, CPU_INTERRUPT_VFIQ
);
669 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VFIQ
);
674 #ifndef CONFIG_USER_ONLY
675 static void arm_cpu_set_irq(void *opaque
, int irq
, int level
)
677 ARMCPU
*cpu
= opaque
;
678 CPUARMState
*env
= &cpu
->env
;
679 CPUState
*cs
= CPU(cpu
);
680 static const int mask
[] = {
681 [ARM_CPU_IRQ
] = CPU_INTERRUPT_HARD
,
682 [ARM_CPU_FIQ
] = CPU_INTERRUPT_FIQ
,
683 [ARM_CPU_VIRQ
] = CPU_INTERRUPT_VIRQ
,
684 [ARM_CPU_VFIQ
] = CPU_INTERRUPT_VFIQ
688 env
->irq_line_state
|= mask
[irq
];
690 env
->irq_line_state
&= ~mask
[irq
];
695 assert(arm_feature(env
, ARM_FEATURE_EL2
));
696 arm_cpu_update_virq(cpu
);
699 assert(arm_feature(env
, ARM_FEATURE_EL2
));
700 arm_cpu_update_vfiq(cpu
);
705 cpu_interrupt(cs
, mask
[irq
]);
707 cpu_reset_interrupt(cs
, mask
[irq
]);
711 g_assert_not_reached();
715 static void arm_cpu_kvm_set_irq(void *opaque
, int irq
, int level
)
718 ARMCPU
*cpu
= opaque
;
719 CPUARMState
*env
= &cpu
->env
;
720 CPUState
*cs
= CPU(cpu
);
721 uint32_t linestate_bit
;
726 irq_id
= KVM_ARM_IRQ_CPU_IRQ
;
727 linestate_bit
= CPU_INTERRUPT_HARD
;
730 irq_id
= KVM_ARM_IRQ_CPU_FIQ
;
731 linestate_bit
= CPU_INTERRUPT_FIQ
;
734 g_assert_not_reached();
738 env
->irq_line_state
|= linestate_bit
;
740 env
->irq_line_state
&= ~linestate_bit
;
742 kvm_arm_set_irq(cs
->cpu_index
, KVM_ARM_IRQ_TYPE_CPU
, irq_id
, !!level
);
746 static bool arm_cpu_virtio_is_big_endian(CPUState
*cs
)
748 ARMCPU
*cpu
= ARM_CPU(cs
);
749 CPUARMState
*env
= &cpu
->env
;
751 cpu_synchronize_state(cs
);
752 return arm_cpu_data_is_big_endian(env
);
758 print_insn_thumb1(bfd_vma pc
, disassemble_info
*info
)
760 return print_insn_arm(pc
| 1, info
);
763 static void arm_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
765 ARMCPU
*ac
= ARM_CPU(cpu
);
766 CPUARMState
*env
= &ac
->env
;
770 /* We might not be compiled with the A64 disassembler
771 * because it needs a C++ compiler. Leave print_insn
772 * unset in this case to use the caller default behaviour.
774 #if defined(CONFIG_ARM_A64_DIS)
775 info
->print_insn
= print_insn_arm_a64
;
777 info
->cap_arch
= CS_ARCH_ARM64
;
778 info
->cap_insn_unit
= 4;
779 info
->cap_insn_split
= 4;
783 info
->print_insn
= print_insn_thumb1
;
784 info
->cap_insn_unit
= 2;
785 info
->cap_insn_split
= 4;
786 cap_mode
= CS_MODE_THUMB
;
788 info
->print_insn
= print_insn_arm
;
789 info
->cap_insn_unit
= 4;
790 info
->cap_insn_split
= 4;
791 cap_mode
= CS_MODE_ARM
;
793 if (arm_feature(env
, ARM_FEATURE_V8
)) {
794 cap_mode
|= CS_MODE_V8
;
796 if (arm_feature(env
, ARM_FEATURE_M
)) {
797 cap_mode
|= CS_MODE_MCLASS
;
799 info
->cap_arch
= CS_ARCH_ARM
;
800 info
->cap_mode
= cap_mode
;
803 sctlr_b
= arm_sctlr_b(env
);
804 if (bswap_code(sctlr_b
)) {
805 #ifdef TARGET_WORDS_BIGENDIAN
806 info
->endian
= BFD_ENDIAN_LITTLE
;
808 info
->endian
= BFD_ENDIAN_BIG
;
811 info
->flags
&= ~INSN_ARM_BE32
;
812 #ifndef CONFIG_USER_ONLY
814 info
->flags
|= INSN_ARM_BE32
;
819 #ifdef TARGET_AARCH64
821 static void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
823 ARMCPU
*cpu
= ARM_CPU(cs
);
824 CPUARMState
*env
= &cpu
->env
;
825 uint32_t psr
= pstate_read(env
);
827 int el
= arm_current_el(env
);
828 const char *ns_status
;
830 qemu_fprintf(f
, " PC=%016" PRIx64
" ", env
->pc
);
831 for (i
= 0; i
< 32; i
++) {
833 qemu_fprintf(f
, " SP=%016" PRIx64
"\n", env
->xregs
[i
]);
835 qemu_fprintf(f
, "X%02d=%016" PRIx64
"%s", i
, env
->xregs
[i
],
836 (i
+ 2) % 3 ? " " : "\n");
840 if (arm_feature(env
, ARM_FEATURE_EL3
) && el
!= 3) {
841 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
845 qemu_fprintf(f
, "PSTATE=%08x %c%c%c%c %sEL%d%c",
847 psr
& PSTATE_N
? 'N' : '-',
848 psr
& PSTATE_Z
? 'Z' : '-',
849 psr
& PSTATE_C
? 'C' : '-',
850 psr
& PSTATE_V
? 'V' : '-',
853 psr
& PSTATE_SP
? 'h' : 't');
855 if (cpu_isar_feature(aa64_bti
, cpu
)) {
856 qemu_fprintf(f
, " BTYPE=%d", (psr
& PSTATE_BTYPE
) >> 10);
858 if (!(flags
& CPU_DUMP_FPU
)) {
859 qemu_fprintf(f
, "\n");
862 if (fp_exception_el(env
, el
) != 0) {
863 qemu_fprintf(f
, " FPU disabled\n");
866 qemu_fprintf(f
, " FPCR=%08x FPSR=%08x\n",
867 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
869 if (cpu_isar_feature(aa64_sve
, cpu
) && sve_exception_el(env
, el
) == 0) {
870 int j
, zcr_len
= sve_zcr_len_for_el(env
, el
);
872 for (i
= 0; i
<= FFR_PRED_NUM
; i
++) {
874 if (i
== FFR_PRED_NUM
) {
875 qemu_fprintf(f
, "FFR=");
876 /* It's last, so end the line. */
879 qemu_fprintf(f
, "P%02d=", i
);
892 /* More than one quadword per predicate. */
897 for (j
= zcr_len
/ 4; j
>= 0; j
--) {
899 if (j
* 4 + 4 <= zcr_len
+ 1) {
902 digits
= (zcr_len
% 4 + 1) * 4;
904 qemu_fprintf(f
, "%0*" PRIx64
"%s", digits
,
905 env
->vfp
.pregs
[i
].p
[j
],
906 j
? ":" : eol
? "\n" : " ");
910 for (i
= 0; i
< 32; i
++) {
912 qemu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
"%s",
913 i
, env
->vfp
.zregs
[i
].d
[1],
914 env
->vfp
.zregs
[i
].d
[0], i
& 1 ? "\n" : " ");
915 } else if (zcr_len
== 1) {
916 qemu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
917 ":%016" PRIx64
":%016" PRIx64
"\n",
918 i
, env
->vfp
.zregs
[i
].d
[3], env
->vfp
.zregs
[i
].d
[2],
919 env
->vfp
.zregs
[i
].d
[1], env
->vfp
.zregs
[i
].d
[0]);
921 for (j
= zcr_len
; j
>= 0; j
--) {
922 bool odd
= (zcr_len
- j
) % 2 != 0;
924 qemu_fprintf(f
, "Z%02d[%x-%x]=", i
, j
, j
- 1);
927 qemu_fprintf(f
, " [%x-%x]=", j
, j
- 1);
929 qemu_fprintf(f
, " [%x]=", j
);
932 qemu_fprintf(f
, "%016" PRIx64
":%016" PRIx64
"%s",
933 env
->vfp
.zregs
[i
].d
[j
* 2 + 1],
934 env
->vfp
.zregs
[i
].d
[j
* 2],
935 odd
|| j
== 0 ? "\n" : ":");
940 for (i
= 0; i
< 32; i
++) {
941 uint64_t *q
= aa64_vfp_qreg(env
, i
);
942 qemu_fprintf(f
, "Q%02d=%016" PRIx64
":%016" PRIx64
"%s",
943 i
, q
[1], q
[0], (i
& 1 ? "\n" : " "));
950 static inline void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
952 g_assert_not_reached();
957 static void arm_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
959 ARMCPU
*cpu
= ARM_CPU(cs
);
960 CPUARMState
*env
= &cpu
->env
;
964 aarch64_cpu_dump_state(cs
, f
, flags
);
968 for (i
= 0; i
< 16; i
++) {
969 qemu_fprintf(f
, "R%02d=%08x", i
, env
->regs
[i
]);
971 qemu_fprintf(f
, "\n");
973 qemu_fprintf(f
, " ");
977 if (arm_feature(env
, ARM_FEATURE_M
)) {
978 uint32_t xpsr
= xpsr_read(env
);
980 const char *ns_status
= "";
982 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
983 ns_status
= env
->v7m
.secure
? "S " : "NS ";
986 if (xpsr
& XPSR_EXCP
) {
989 if (env
->v7m
.control
[env
->v7m
.secure
] & R_V7M_CONTROL_NPRIV_MASK
) {
990 mode
= "unpriv-thread";
992 mode
= "priv-thread";
996 qemu_fprintf(f
, "XPSR=%08x %c%c%c%c %c %s%s\n",
998 xpsr
& XPSR_N
? 'N' : '-',
999 xpsr
& XPSR_Z
? 'Z' : '-',
1000 xpsr
& XPSR_C
? 'C' : '-',
1001 xpsr
& XPSR_V
? 'V' : '-',
1002 xpsr
& XPSR_T
? 'T' : 'A',
1006 uint32_t psr
= cpsr_read(env
);
1007 const char *ns_status
= "";
1009 if (arm_feature(env
, ARM_FEATURE_EL3
) &&
1010 (psr
& CPSR_M
) != ARM_CPU_MODE_MON
) {
1011 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
1014 qemu_fprintf(f
, "PSR=%08x %c%c%c%c %c %s%s%d\n",
1016 psr
& CPSR_N
? 'N' : '-',
1017 psr
& CPSR_Z
? 'Z' : '-',
1018 psr
& CPSR_C
? 'C' : '-',
1019 psr
& CPSR_V
? 'V' : '-',
1020 psr
& CPSR_T
? 'T' : 'A',
1022 aarch32_mode_name(psr
), (psr
& 0x10) ? 32 : 26);
1025 if (flags
& CPU_DUMP_FPU
) {
1027 if (cpu_isar_feature(aa32_simd_r32
, cpu
)) {
1029 } else if (cpu_isar_feature(aa32_vfp_simd
, cpu
)) {
1032 for (i
= 0; i
< numvfpregs
; i
++) {
1033 uint64_t v
= *aa32_vfp_dreg(env
, i
);
1034 qemu_fprintf(f
, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64
"\n",
1036 i
* 2 + 1, (uint32_t)(v
>> 32),
1039 qemu_fprintf(f
, "FPSCR: %08x\n", vfp_get_fpscr(env
));
1040 if (cpu_isar_feature(aa32_mve
, cpu
)) {
1041 qemu_fprintf(f
, "VPR: %08x\n", env
->v7m
.vpr
);
1046 uint64_t arm_cpu_mp_affinity(int idx
, uint8_t clustersz
)
1048 uint32_t Aff1
= idx
/ clustersz
;
1049 uint32_t Aff0
= idx
% clustersz
;
1050 return (Aff1
<< ARM_AFF1_SHIFT
) | Aff0
;
1053 static void cpreg_hashtable_data_destroy(gpointer data
)
1056 * Destroy function for cpu->cp_regs hashtable data entries.
1057 * We must free the name string because it was g_strdup()ed in
1058 * add_cpreg_to_hashtable(). It's OK to cast away the 'const'
1059 * from r->name because we know we definitely allocated it.
1061 ARMCPRegInfo
*r
= data
;
1063 g_free((void *)r
->name
);
1067 static void arm_cpu_initfn(Object
*obj
)
1069 ARMCPU
*cpu
= ARM_CPU(obj
);
1071 cpu_set_cpustate_pointers(cpu
);
1072 cpu
->cp_regs
= g_hash_table_new_full(g_int_hash
, g_int_equal
,
1073 g_free
, cpreg_hashtable_data_destroy
);
1075 QLIST_INIT(&cpu
->pre_el_change_hooks
);
1076 QLIST_INIT(&cpu
->el_change_hooks
);
1078 #ifdef CONFIG_USER_ONLY
1079 # ifdef TARGET_AARCH64
1081 * The linux kernel defaults to 512-bit vectors, when sve is supported.
1082 * See documentation for /proc/sys/abi/sve_default_vector_length, and
1083 * our corresponding sve-default-vector-length cpu property.
1085 cpu
->sve_default_vq
= 4;
1088 /* Our inbound IRQ and FIQ lines */
1089 if (kvm_enabled()) {
1090 /* VIRQ and VFIQ are unused with KVM but we add them to maintain
1091 * the same interface as non-KVM CPUs.
1093 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_kvm_set_irq
, 4);
1095 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_set_irq
, 4);
1098 qdev_init_gpio_out(DEVICE(cpu
), cpu
->gt_timer_outputs
,
1099 ARRAY_SIZE(cpu
->gt_timer_outputs
));
1101 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->gicv3_maintenance_interrupt
,
1102 "gicv3-maintenance-interrupt", 1);
1103 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->pmu_interrupt
,
1104 "pmu-interrupt", 1);
1107 /* DTB consumers generally don't in fact care what the 'compatible'
1108 * string is, so always provide some string and trust that a hypothetical
1109 * picky DTB consumer will also provide a helpful error message.
1111 cpu
->dtb_compatible
= "qemu,unknown";
1112 cpu
->psci_version
= 1; /* By default assume PSCI v0.1 */
1113 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_NONE
;
1115 if (tcg_enabled()) {
1116 cpu
->psci_version
= 2; /* TCG implements PSCI 0.2 */
1120 static Property arm_cpu_gt_cntfrq_property
=
1121 DEFINE_PROP_UINT64("cntfrq", ARMCPU
, gt_cntfrq_hz
,
1122 NANOSECONDS_PER_SECOND
/ GTIMER_SCALE
);
1124 static Property arm_cpu_reset_cbar_property
=
1125 DEFINE_PROP_UINT64("reset-cbar", ARMCPU
, reset_cbar
, 0);
1127 static Property arm_cpu_reset_hivecs_property
=
1128 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU
, reset_hivecs
, false);
1130 static Property arm_cpu_rvbar_property
=
1131 DEFINE_PROP_UINT64("rvbar", ARMCPU
, rvbar
, 0);
1133 #ifndef CONFIG_USER_ONLY
1134 static Property arm_cpu_has_el2_property
=
1135 DEFINE_PROP_BOOL("has_el2", ARMCPU
, has_el2
, true);
1137 static Property arm_cpu_has_el3_property
=
1138 DEFINE_PROP_BOOL("has_el3", ARMCPU
, has_el3
, true);
1141 static Property arm_cpu_cfgend_property
=
1142 DEFINE_PROP_BOOL("cfgend", ARMCPU
, cfgend
, false);
1144 static Property arm_cpu_has_vfp_property
=
1145 DEFINE_PROP_BOOL("vfp", ARMCPU
, has_vfp
, true);
1147 static Property arm_cpu_has_neon_property
=
1148 DEFINE_PROP_BOOL("neon", ARMCPU
, has_neon
, true);
1150 static Property arm_cpu_has_dsp_property
=
1151 DEFINE_PROP_BOOL("dsp", ARMCPU
, has_dsp
, true);
1153 static Property arm_cpu_has_mpu_property
=
1154 DEFINE_PROP_BOOL("has-mpu", ARMCPU
, has_mpu
, true);
1156 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value,
1157 * because the CPU initfn will have already set cpu->pmsav7_dregion to
1158 * the right value for that particular CPU type, and we don't want
1159 * to override that with an incorrect constant value.
1161 static Property arm_cpu_pmsav7_dregion_property
=
1162 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU
,
1164 qdev_prop_uint32
, uint32_t);
1166 static bool arm_get_pmu(Object
*obj
, Error
**errp
)
1168 ARMCPU
*cpu
= ARM_CPU(obj
);
1170 return cpu
->has_pmu
;
1173 static void arm_set_pmu(Object
*obj
, bool value
, Error
**errp
)
1175 ARMCPU
*cpu
= ARM_CPU(obj
);
1178 if (kvm_enabled() && !kvm_arm_pmu_supported()) {
1179 error_setg(errp
, "'pmu' feature not supported by KVM on this host");
1182 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
1184 unset_feature(&cpu
->env
, ARM_FEATURE_PMU
);
1186 cpu
->has_pmu
= value
;
1189 unsigned int gt_cntfrq_period_ns(ARMCPU
*cpu
)
1192 * The exact approach to calculating guest ticks is:
1194 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz,
1195 * NANOSECONDS_PER_SECOND);
1197 * We don't do that. Rather we intentionally use integer division
1198 * truncation below and in the caller for the conversion of host monotonic
1199 * time to guest ticks to provide the exact inverse for the semantics of
1200 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so
1201 * it loses precision when representing frequencies where
1202 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to
1203 * provide an exact inverse leads to scheduling timers with negative
1204 * periods, which in turn leads to sticky behaviour in the guest.
1206 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor
1207 * cannot become zero.
1209 return NANOSECONDS_PER_SECOND
> cpu
->gt_cntfrq_hz
?
1210 NANOSECONDS_PER_SECOND
/ cpu
->gt_cntfrq_hz
: 1;
1213 void arm_cpu_post_init(Object
*obj
)
1215 ARMCPU
*cpu
= ARM_CPU(obj
);
1217 /* M profile implies PMSA. We have to do this here rather than
1218 * in realize with the other feature-implication checks because
1219 * we look at the PMSA bit to see if we should add some properties.
1221 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
1222 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
1225 if (arm_feature(&cpu
->env
, ARM_FEATURE_CBAR
) ||
1226 arm_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
)) {
1227 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_cbar_property
);
1230 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
1231 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_hivecs_property
);
1234 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1235 qdev_property_add_static(DEVICE(obj
), &arm_cpu_rvbar_property
);
1238 #ifndef CONFIG_USER_ONLY
1239 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL3
)) {
1240 /* Add the has_el3 state CPU property only if EL3 is allowed. This will
1241 * prevent "has_el3" from existing on CPUs which cannot support EL3.
1243 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el3_property
);
1245 object_property_add_link(obj
, "secure-memory",
1247 (Object
**)&cpu
->secure_memory
,
1248 qdev_prop_allow_set_link_before_realize
,
1249 OBJ_PROP_LINK_STRONG
);
1252 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL2
)) {
1253 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el2_property
);
1257 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMU
)) {
1258 cpu
->has_pmu
= true;
1259 object_property_add_bool(obj
, "pmu", arm_get_pmu
, arm_set_pmu
);
1263 * Allow user to turn off VFP and Neon support, but only for TCG --
1264 * KVM does not currently allow us to lie to the guest about its
1265 * ID/feature registers, so the guest always sees what the host has.
1267 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)
1268 ? cpu_isar_feature(aa64_fp_simd
, cpu
)
1269 : cpu_isar_feature(aa32_vfp
, cpu
)) {
1270 cpu
->has_vfp
= true;
1271 if (!kvm_enabled()) {
1272 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_vfp_property
);
1276 if (arm_feature(&cpu
->env
, ARM_FEATURE_NEON
)) {
1277 cpu
->has_neon
= true;
1278 if (!kvm_enabled()) {
1279 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_neon_property
);
1283 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
) &&
1284 arm_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
)) {
1285 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_dsp_property
);
1288 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMSA
)) {
1289 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_mpu_property
);
1290 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
1291 qdev_property_add_static(DEVICE(obj
),
1292 &arm_cpu_pmsav7_dregion_property
);
1296 if (arm_feature(&cpu
->env
, ARM_FEATURE_M_SECURITY
)) {
1297 object_property_add_link(obj
, "idau", TYPE_IDAU_INTERFACE
, &cpu
->idau
,
1298 qdev_prop_allow_set_link_before_realize
,
1299 OBJ_PROP_LINK_STRONG
);
1301 * M profile: initial value of the Secure VTOR. We can't just use
1302 * a simple DEFINE_PROP_UINT32 for this because we want to permit
1303 * the property to be set after realize.
1305 object_property_add_uint32_ptr(obj
, "init-svtor",
1307 OBJ_PROP_FLAG_READWRITE
);
1309 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
1311 * Initial value of the NS VTOR (for cores without the Security
1312 * extension, this is the only VTOR)
1314 object_property_add_uint32_ptr(obj
, "init-nsvtor",
1316 OBJ_PROP_FLAG_READWRITE
);
1319 qdev_property_add_static(DEVICE(obj
), &arm_cpu_cfgend_property
);
1321 if (arm_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
)) {
1322 qdev_property_add_static(DEVICE(cpu
), &arm_cpu_gt_cntfrq_property
);
1325 if (kvm_enabled()) {
1326 kvm_arm_add_vcpu_properties(obj
);
1329 #ifndef CONFIG_USER_ONLY
1330 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
) &&
1331 cpu_isar_feature(aa64_mte
, cpu
)) {
1332 object_property_add_link(obj
, "tag-memory",
1334 (Object
**)&cpu
->tag_memory
,
1335 qdev_prop_allow_set_link_before_realize
,
1336 OBJ_PROP_LINK_STRONG
);
1338 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL3
)) {
1339 object_property_add_link(obj
, "secure-tag-memory",
1341 (Object
**)&cpu
->secure_tag_memory
,
1342 qdev_prop_allow_set_link_before_realize
,
1343 OBJ_PROP_LINK_STRONG
);
1349 static void arm_cpu_finalizefn(Object
*obj
)
1351 ARMCPU
*cpu
= ARM_CPU(obj
);
1352 ARMELChangeHook
*hook
, *next
;
1354 g_hash_table_destroy(cpu
->cp_regs
);
1356 QLIST_FOREACH_SAFE(hook
, &cpu
->pre_el_change_hooks
, node
, next
) {
1357 QLIST_REMOVE(hook
, node
);
1360 QLIST_FOREACH_SAFE(hook
, &cpu
->el_change_hooks
, node
, next
) {
1361 QLIST_REMOVE(hook
, node
);
1364 #ifndef CONFIG_USER_ONLY
1365 if (cpu
->pmu_timer
) {
1366 timer_free(cpu
->pmu_timer
);
1371 void arm_cpu_finalize_features(ARMCPU
*cpu
, Error
**errp
)
1373 Error
*local_err
= NULL
;
1375 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1376 arm_cpu_sve_finalize(cpu
, &local_err
);
1377 if (local_err
!= NULL
) {
1378 error_propagate(errp
, local_err
);
1383 * KVM does not support modifications to this feature.
1384 * We have not registered the cpu properties when KVM
1385 * is in use, so the user will not be able to set them.
1387 if (!kvm_enabled()) {
1388 arm_cpu_pauth_finalize(cpu
, &local_err
);
1389 if (local_err
!= NULL
) {
1390 error_propagate(errp
, local_err
);
1396 if (kvm_enabled()) {
1397 kvm_arm_steal_time_finalize(cpu
, &local_err
);
1398 if (local_err
!= NULL
) {
1399 error_propagate(errp
, local_err
);
1405 static void arm_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
1407 CPUState
*cs
= CPU(dev
);
1408 ARMCPU
*cpu
= ARM_CPU(dev
);
1409 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(dev
);
1410 CPUARMState
*env
= &cpu
->env
;
1412 Error
*local_err
= NULL
;
1413 bool no_aa32
= false;
1415 /* If we needed to query the host kernel for the CPU features
1416 * then it's possible that might have failed in the initfn, but
1417 * this is the first point where we can report it.
1419 if (cpu
->host_cpu_probe_failed
) {
1420 if (!kvm_enabled()) {
1421 error_setg(errp
, "The 'host' CPU type can only be used with KVM");
1423 error_setg(errp
, "Failed to retrieve host CPU features");
1428 #ifndef CONFIG_USER_ONLY
1429 /* The NVIC and M-profile CPU are two halves of a single piece of
1430 * hardware; trying to use one without the other is a command line
1431 * error and will result in segfaults if not caught here.
1433 if (arm_feature(env
, ARM_FEATURE_M
)) {
1435 error_setg(errp
, "This board cannot be used with Cortex-M CPUs");
1440 error_setg(errp
, "This board can only be used with Cortex-M CPUs");
1445 if (kvm_enabled()) {
1447 * Catch all the cases which might cause us to create more than one
1448 * address space for the CPU (otherwise we will assert() later in
1449 * cpu_address_space_init()).
1451 if (arm_feature(env
, ARM_FEATURE_M
)) {
1453 "Cannot enable KVM when using an M-profile guest CPU");
1458 "Cannot enable KVM when guest CPU has EL3 enabled");
1461 if (cpu
->tag_memory
) {
1463 "Cannot enable KVM when guest CPUs has MTE enabled");
1471 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
1472 if (!cpu
->gt_cntfrq_hz
) {
1473 error_setg(errp
, "Invalid CNTFRQ: %"PRId64
"Hz",
1477 scale
= gt_cntfrq_period_ns(cpu
);
1479 scale
= GTIMER_SCALE
;
1482 cpu
->gt_timer
[GTIMER_PHYS
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1483 arm_gt_ptimer_cb
, cpu
);
1484 cpu
->gt_timer
[GTIMER_VIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1485 arm_gt_vtimer_cb
, cpu
);
1486 cpu
->gt_timer
[GTIMER_HYP
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1487 arm_gt_htimer_cb
, cpu
);
1488 cpu
->gt_timer
[GTIMER_SEC
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1489 arm_gt_stimer_cb
, cpu
);
1490 cpu
->gt_timer
[GTIMER_HYPVIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1491 arm_gt_hvtimer_cb
, cpu
);
1495 cpu_exec_realizefn(cs
, &local_err
);
1496 if (local_err
!= NULL
) {
1497 error_propagate(errp
, local_err
);
1501 arm_cpu_finalize_features(cpu
, &local_err
);
1502 if (local_err
!= NULL
) {
1503 error_propagate(errp
, local_err
);
1507 if (arm_feature(env
, ARM_FEATURE_AARCH64
) &&
1508 cpu
->has_vfp
!= cpu
->has_neon
) {
1510 * This is an architectural requirement for AArch64; AArch32 is
1511 * more flexible and permits VFP-no-Neon and Neon-no-VFP.
1514 "AArch64 CPUs must have both VFP and Neon or neither");
1518 if (!cpu
->has_vfp
) {
1522 t
= cpu
->isar
.id_aa64isar1
;
1523 t
= FIELD_DP64(t
, ID_AA64ISAR1
, JSCVT
, 0);
1524 cpu
->isar
.id_aa64isar1
= t
;
1526 t
= cpu
->isar
.id_aa64pfr0
;
1527 t
= FIELD_DP64(t
, ID_AA64PFR0
, FP
, 0xf);
1528 cpu
->isar
.id_aa64pfr0
= t
;
1530 u
= cpu
->isar
.id_isar6
;
1531 u
= FIELD_DP32(u
, ID_ISAR6
, JSCVT
, 0);
1532 u
= FIELD_DP32(u
, ID_ISAR6
, BF16
, 0);
1533 cpu
->isar
.id_isar6
= u
;
1535 u
= cpu
->isar
.mvfr0
;
1536 u
= FIELD_DP32(u
, MVFR0
, FPSP
, 0);
1537 u
= FIELD_DP32(u
, MVFR0
, FPDP
, 0);
1538 u
= FIELD_DP32(u
, MVFR0
, FPDIVIDE
, 0);
1539 u
= FIELD_DP32(u
, MVFR0
, FPSQRT
, 0);
1540 u
= FIELD_DP32(u
, MVFR0
, FPROUND
, 0);
1541 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1542 u
= FIELD_DP32(u
, MVFR0
, FPTRAP
, 0);
1543 u
= FIELD_DP32(u
, MVFR0
, FPSHVEC
, 0);
1545 cpu
->isar
.mvfr0
= u
;
1547 u
= cpu
->isar
.mvfr1
;
1548 u
= FIELD_DP32(u
, MVFR1
, FPFTZ
, 0);
1549 u
= FIELD_DP32(u
, MVFR1
, FPDNAN
, 0);
1550 u
= FIELD_DP32(u
, MVFR1
, FPHP
, 0);
1551 if (arm_feature(env
, ARM_FEATURE_M
)) {
1552 u
= FIELD_DP32(u
, MVFR1
, FP16
, 0);
1554 cpu
->isar
.mvfr1
= u
;
1556 u
= cpu
->isar
.mvfr2
;
1557 u
= FIELD_DP32(u
, MVFR2
, FPMISC
, 0);
1558 cpu
->isar
.mvfr2
= u
;
1561 if (!cpu
->has_neon
) {
1565 unset_feature(env
, ARM_FEATURE_NEON
);
1567 t
= cpu
->isar
.id_aa64isar0
;
1568 t
= FIELD_DP64(t
, ID_AA64ISAR0
, DP
, 0);
1569 cpu
->isar
.id_aa64isar0
= t
;
1571 t
= cpu
->isar
.id_aa64isar1
;
1572 t
= FIELD_DP64(t
, ID_AA64ISAR1
, FCMA
, 0);
1573 t
= FIELD_DP64(t
, ID_AA64ISAR1
, BF16
, 0);
1574 t
= FIELD_DP64(t
, ID_AA64ISAR1
, I8MM
, 0);
1575 cpu
->isar
.id_aa64isar1
= t
;
1577 t
= cpu
->isar
.id_aa64pfr0
;
1578 t
= FIELD_DP64(t
, ID_AA64PFR0
, ADVSIMD
, 0xf);
1579 cpu
->isar
.id_aa64pfr0
= t
;
1581 u
= cpu
->isar
.id_isar5
;
1582 u
= FIELD_DP32(u
, ID_ISAR5
, RDM
, 0);
1583 u
= FIELD_DP32(u
, ID_ISAR5
, VCMA
, 0);
1584 cpu
->isar
.id_isar5
= u
;
1586 u
= cpu
->isar
.id_isar6
;
1587 u
= FIELD_DP32(u
, ID_ISAR6
, DP
, 0);
1588 u
= FIELD_DP32(u
, ID_ISAR6
, FHM
, 0);
1589 u
= FIELD_DP32(u
, ID_ISAR6
, BF16
, 0);
1590 u
= FIELD_DP32(u
, ID_ISAR6
, I8MM
, 0);
1591 cpu
->isar
.id_isar6
= u
;
1593 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1594 u
= cpu
->isar
.mvfr1
;
1595 u
= FIELD_DP32(u
, MVFR1
, SIMDLS
, 0);
1596 u
= FIELD_DP32(u
, MVFR1
, SIMDINT
, 0);
1597 u
= FIELD_DP32(u
, MVFR1
, SIMDSP
, 0);
1598 u
= FIELD_DP32(u
, MVFR1
, SIMDHP
, 0);
1599 cpu
->isar
.mvfr1
= u
;
1601 u
= cpu
->isar
.mvfr2
;
1602 u
= FIELD_DP32(u
, MVFR2
, SIMDMISC
, 0);
1603 cpu
->isar
.mvfr2
= u
;
1607 if (!cpu
->has_neon
&& !cpu
->has_vfp
) {
1611 t
= cpu
->isar
.id_aa64isar0
;
1612 t
= FIELD_DP64(t
, ID_AA64ISAR0
, FHM
, 0);
1613 cpu
->isar
.id_aa64isar0
= t
;
1615 t
= cpu
->isar
.id_aa64isar1
;
1616 t
= FIELD_DP64(t
, ID_AA64ISAR1
, FRINTTS
, 0);
1617 cpu
->isar
.id_aa64isar1
= t
;
1619 u
= cpu
->isar
.mvfr0
;
1620 u
= FIELD_DP32(u
, MVFR0
, SIMDREG
, 0);
1621 cpu
->isar
.mvfr0
= u
;
1623 /* Despite the name, this field covers both VFP and Neon */
1624 u
= cpu
->isar
.mvfr1
;
1625 u
= FIELD_DP32(u
, MVFR1
, SIMDFMAC
, 0);
1626 cpu
->isar
.mvfr1
= u
;
1629 if (arm_feature(env
, ARM_FEATURE_M
) && !cpu
->has_dsp
) {
1632 unset_feature(env
, ARM_FEATURE_THUMB_DSP
);
1634 u
= cpu
->isar
.id_isar1
;
1635 u
= FIELD_DP32(u
, ID_ISAR1
, EXTEND
, 1);
1636 cpu
->isar
.id_isar1
= u
;
1638 u
= cpu
->isar
.id_isar2
;
1639 u
= FIELD_DP32(u
, ID_ISAR2
, MULTU
, 1);
1640 u
= FIELD_DP32(u
, ID_ISAR2
, MULTS
, 1);
1641 cpu
->isar
.id_isar2
= u
;
1643 u
= cpu
->isar
.id_isar3
;
1644 u
= FIELD_DP32(u
, ID_ISAR3
, SIMD
, 1);
1645 u
= FIELD_DP32(u
, ID_ISAR3
, SATURATE
, 0);
1646 cpu
->isar
.id_isar3
= u
;
1649 /* Some features automatically imply others: */
1650 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1651 if (arm_feature(env
, ARM_FEATURE_M
)) {
1652 set_feature(env
, ARM_FEATURE_V7
);
1654 set_feature(env
, ARM_FEATURE_V7VE
);
1659 * There exist AArch64 cpus without AArch32 support. When KVM
1660 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
1661 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
1662 * As a general principle, we also do not make ID register
1663 * consistency checks anywhere unless using TCG, because only
1664 * for TCG would a consistency-check failure be a QEMU bug.
1666 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1667 no_aa32
= !cpu_isar_feature(aa64_aa32
, cpu
);
1670 if (arm_feature(env
, ARM_FEATURE_V7VE
)) {
1671 /* v7 Virtualization Extensions. In real hardware this implies
1672 * EL2 and also the presence of the Security Extensions.
1673 * For QEMU, for backwards-compatibility we implement some
1674 * CPUs or CPU configs which have no actual EL2 or EL3 but do
1675 * include the various other features that V7VE implies.
1676 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
1677 * Security Extensions is ARM_FEATURE_EL3.
1679 assert(!tcg_enabled() || no_aa32
||
1680 cpu_isar_feature(aa32_arm_div
, cpu
));
1681 set_feature(env
, ARM_FEATURE_LPAE
);
1682 set_feature(env
, ARM_FEATURE_V7
);
1684 if (arm_feature(env
, ARM_FEATURE_V7
)) {
1685 set_feature(env
, ARM_FEATURE_VAPA
);
1686 set_feature(env
, ARM_FEATURE_THUMB2
);
1687 set_feature(env
, ARM_FEATURE_MPIDR
);
1688 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1689 set_feature(env
, ARM_FEATURE_V6K
);
1691 set_feature(env
, ARM_FEATURE_V6
);
1694 /* Always define VBAR for V7 CPUs even if it doesn't exist in
1695 * non-EL3 configs. This is needed by some legacy boards.
1697 set_feature(env
, ARM_FEATURE_VBAR
);
1699 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
1700 set_feature(env
, ARM_FEATURE_V6
);
1701 set_feature(env
, ARM_FEATURE_MVFR
);
1703 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1704 set_feature(env
, ARM_FEATURE_V5
);
1705 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1706 assert(!tcg_enabled() || no_aa32
||
1707 cpu_isar_feature(aa32_jazelle
, cpu
));
1708 set_feature(env
, ARM_FEATURE_AUXCR
);
1711 if (arm_feature(env
, ARM_FEATURE_V5
)) {
1712 set_feature(env
, ARM_FEATURE_V4T
);
1714 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
1715 set_feature(env
, ARM_FEATURE_V7MP
);
1717 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
1718 set_feature(env
, ARM_FEATURE_CBAR
);
1720 if (arm_feature(env
, ARM_FEATURE_THUMB2
) &&
1721 !arm_feature(env
, ARM_FEATURE_M
)) {
1722 set_feature(env
, ARM_FEATURE_THUMB_DSP
);
1726 * We rely on no XScale CPU having VFP so we can use the same bits in the
1727 * TB flags field for VECSTRIDE and XSCALE_CPAR.
1729 assert(arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
) ||
1730 !cpu_isar_feature(aa32_vfp_simd
, cpu
) ||
1731 !arm_feature(env
, ARM_FEATURE_XSCALE
));
1733 if (arm_feature(env
, ARM_FEATURE_V7
) &&
1734 !arm_feature(env
, ARM_FEATURE_M
) &&
1735 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
1736 /* v7VMSA drops support for the old ARMv5 tiny pages, so we
1741 /* For CPUs which might have tiny 1K pages, or which have an
1742 * MPU and might have small region sizes, stick with 1K pages.
1746 if (!set_preferred_target_page_bits(pagebits
)) {
1747 /* This can only ever happen for hotplugging a CPU, or if
1748 * the board code incorrectly creates a CPU which it has
1749 * promised via minimum_page_size that it will not.
1751 error_setg(errp
, "This CPU requires a smaller page size than the "
1756 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
1757 * We don't support setting cluster ID ([16..23]) (known as Aff2
1758 * in later ARM ARM versions), or any of the higher affinity level fields,
1759 * so these bits always RAZ.
1761 if (cpu
->mp_affinity
== ARM64_AFFINITY_INVALID
) {
1762 cpu
->mp_affinity
= arm_cpu_mp_affinity(cs
->cpu_index
,
1763 ARM_DEFAULT_CPUS_PER_CLUSTER
);
1766 if (cpu
->reset_hivecs
) {
1767 cpu
->reset_sctlr
|= (1 << 13);
1771 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
1772 cpu
->reset_sctlr
|= SCTLR_EE
;
1774 cpu
->reset_sctlr
|= SCTLR_B
;
1778 if (!arm_feature(env
, ARM_FEATURE_M
) && !cpu
->has_el3
) {
1779 /* If the has_el3 CPU property is disabled then we need to disable the
1782 unset_feature(env
, ARM_FEATURE_EL3
);
1784 /* Disable the security extension feature bits in the processor feature
1785 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
1787 cpu
->isar
.id_pfr1
&= ~0xf0;
1788 cpu
->isar
.id_aa64pfr0
&= ~0xf000;
1791 if (!cpu
->has_el2
) {
1792 unset_feature(env
, ARM_FEATURE_EL2
);
1795 if (!cpu
->has_pmu
) {
1796 unset_feature(env
, ARM_FEATURE_PMU
);
1798 if (arm_feature(env
, ARM_FEATURE_PMU
)) {
1801 if (!kvm_enabled()) {
1802 arm_register_pre_el_change_hook(cpu
, &pmu_pre_el_change
, 0);
1803 arm_register_el_change_hook(cpu
, &pmu_post_el_change
, 0);
1806 #ifndef CONFIG_USER_ONLY
1807 cpu
->pmu_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, arm_pmu_timer_cb
,
1811 cpu
->isar
.id_aa64dfr0
=
1812 FIELD_DP64(cpu
->isar
.id_aa64dfr0
, ID_AA64DFR0
, PMUVER
, 0);
1813 cpu
->isar
.id_dfr0
= FIELD_DP32(cpu
->isar
.id_dfr0
, ID_DFR0
, PERFMON
, 0);
1818 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
1819 /* Disable the hypervisor feature bits in the processor feature
1820 * registers if we don't have EL2. These are id_pfr1[15:12] and
1821 * id_aa64pfr0_el1[11:8].
1823 cpu
->isar
.id_aa64pfr0
&= ~0xf00;
1824 cpu
->isar
.id_pfr1
&= ~0xf000;
1827 #ifndef CONFIG_USER_ONLY
1828 if (cpu
->tag_memory
== NULL
&& cpu_isar_feature(aa64_mte
, cpu
)) {
1830 * Disable the MTE feature bits if we do not have tag-memory
1831 * provided by the machine.
1833 cpu
->isar
.id_aa64pfr1
=
1834 FIELD_DP64(cpu
->isar
.id_aa64pfr1
, ID_AA64PFR1
, MTE
, 0);
1838 /* MPU can be configured out of a PMSA CPU either by setting has-mpu
1839 * to false or by setting pmsav7-dregion to 0.
1841 if (!cpu
->has_mpu
) {
1842 cpu
->pmsav7_dregion
= 0;
1844 if (cpu
->pmsav7_dregion
== 0) {
1845 cpu
->has_mpu
= false;
1848 if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
1849 arm_feature(env
, ARM_FEATURE_V7
)) {
1850 uint32_t nr
= cpu
->pmsav7_dregion
;
1853 error_setg(errp
, "PMSAv7 MPU #regions invalid %" PRIu32
, nr
);
1858 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1860 env
->pmsav8
.rbar
[M_REG_NS
] = g_new0(uint32_t, nr
);
1861 env
->pmsav8
.rlar
[M_REG_NS
] = g_new0(uint32_t, nr
);
1862 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1863 env
->pmsav8
.rbar
[M_REG_S
] = g_new0(uint32_t, nr
);
1864 env
->pmsav8
.rlar
[M_REG_S
] = g_new0(uint32_t, nr
);
1867 env
->pmsav7
.drbar
= g_new0(uint32_t, nr
);
1868 env
->pmsav7
.drsr
= g_new0(uint32_t, nr
);
1869 env
->pmsav7
.dracr
= g_new0(uint32_t, nr
);
1874 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1875 uint32_t nr
= cpu
->sau_sregion
;
1878 error_setg(errp
, "v8M SAU #regions invalid %" PRIu32
, nr
);
1883 env
->sau
.rbar
= g_new0(uint32_t, nr
);
1884 env
->sau
.rlar
= g_new0(uint32_t, nr
);
1888 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
1889 set_feature(env
, ARM_FEATURE_VBAR
);
1892 register_cp_regs_for_features(cpu
);
1893 arm_cpu_register_gdb_regs_for_features(cpu
);
1895 init_cpreg_list(cpu
);
1897 #ifndef CONFIG_USER_ONLY
1898 MachineState
*ms
= MACHINE(qdev_get_machine());
1899 unsigned int smp_cpus
= ms
->smp
.cpus
;
1900 bool has_secure
= cpu
->has_el3
|| arm_feature(env
, ARM_FEATURE_M_SECURITY
);
1903 * We must set cs->num_ases to the final value before
1904 * the first call to cpu_address_space_init.
1906 if (cpu
->tag_memory
!= NULL
) {
1907 cs
->num_ases
= 3 + has_secure
;
1909 cs
->num_ases
= 1 + has_secure
;
1913 if (!cpu
->secure_memory
) {
1914 cpu
->secure_memory
= cs
->memory
;
1916 cpu_address_space_init(cs
, ARMASIdx_S
, "cpu-secure-memory",
1917 cpu
->secure_memory
);
1920 if (cpu
->tag_memory
!= NULL
) {
1921 cpu_address_space_init(cs
, ARMASIdx_TagNS
, "cpu-tag-memory",
1924 cpu_address_space_init(cs
, ARMASIdx_TagS
, "cpu-tag-memory",
1925 cpu
->secure_tag_memory
);
1929 cpu_address_space_init(cs
, ARMASIdx_NS
, "cpu-memory", cs
->memory
);
1931 /* No core_count specified, default to smp_cpus. */
1932 if (cpu
->core_count
== -1) {
1933 cpu
->core_count
= smp_cpus
;
1937 if (tcg_enabled()) {
1938 int dcz_blocklen
= 4 << cpu
->dcz_blocksize
;
1941 * We only support DCZ blocklen that fits on one page.
1943 * Architectually this is always true. However TARGET_PAGE_SIZE
1944 * is variable and, for compatibility with -machine virt-2.7,
1945 * is only 1KiB, as an artifact of legacy ARMv5 subpage support.
1946 * But even then, while the largest architectural DCZ blocklen
1947 * is 2KiB, no cpu actually uses such a large blocklen.
1949 assert(dcz_blocklen
<= TARGET_PAGE_SIZE
);
1952 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say
1953 * both nibbles of each byte storing tag data may be written at once.
1954 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32.
1956 if (cpu_isar_feature(aa64_mte
, cpu
)) {
1957 assert(dcz_blocklen
>= 2 * TAG_GRANULE
);
1964 acc
->parent_realize(dev
, errp
);
1967 static ObjectClass
*arm_cpu_class_by_name(const char *cpu_model
)
1972 const char *cpunamestr
;
1974 cpuname
= g_strsplit(cpu_model
, ",", 1);
1975 cpunamestr
= cpuname
[0];
1976 #ifdef CONFIG_USER_ONLY
1977 /* For backwards compatibility usermode emulation allows "-cpu any",
1978 * which has the same semantics as "-cpu max".
1980 if (!strcmp(cpunamestr
, "any")) {
1984 typename
= g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr
);
1985 oc
= object_class_by_name(typename
);
1986 g_strfreev(cpuname
);
1988 if (!oc
|| !object_class_dynamic_cast(oc
, TYPE_ARM_CPU
) ||
1989 object_class_is_abstract(oc
)) {
1995 static Property arm_cpu_properties
[] = {
1996 DEFINE_PROP_UINT32("psci-conduit", ARMCPU
, psci_conduit
, 0),
1997 DEFINE_PROP_UINT64("midr", ARMCPU
, midr
, 0),
1998 DEFINE_PROP_UINT64("mp-affinity", ARMCPU
,
1999 mp_affinity
, ARM64_AFFINITY_INVALID
),
2000 DEFINE_PROP_INT32("node-id", ARMCPU
, node_id
, CPU_UNSET_NUMA_NODE_ID
),
2001 DEFINE_PROP_INT32("core-count", ARMCPU
, core_count
, -1),
2002 DEFINE_PROP_END_OF_LIST()
2005 static gchar
*arm_gdb_arch_name(CPUState
*cs
)
2007 ARMCPU
*cpu
= ARM_CPU(cs
);
2008 CPUARMState
*env
= &cpu
->env
;
2010 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
2011 return g_strdup("iwmmxt");
2013 return g_strdup("arm");
2016 #ifndef CONFIG_USER_ONLY
2017 #include "hw/core/sysemu-cpu-ops.h"
2019 static const struct SysemuCPUOps arm_sysemu_ops
= {
2020 .get_phys_page_attrs_debug
= arm_cpu_get_phys_page_attrs_debug
,
2021 .asidx_from_attrs
= arm_asidx_from_attrs
,
2022 .write_elf32_note
= arm_cpu_write_elf32_note
,
2023 .write_elf64_note
= arm_cpu_write_elf64_note
,
2024 .virtio_is_big_endian
= arm_cpu_virtio_is_big_endian
,
2025 .legacy_vmsd
= &vmstate_arm_cpu
,
2030 static const struct TCGCPUOps arm_tcg_ops
= {
2031 .initialize
= arm_translate_init
,
2032 .synchronize_from_tb
= arm_cpu_synchronize_from_tb
,
2033 .tlb_fill
= arm_cpu_tlb_fill
,
2034 .debug_excp_handler
= arm_debug_excp_handler
,
2036 #if !defined(CONFIG_USER_ONLY)
2037 .cpu_exec_interrupt
= arm_cpu_exec_interrupt
,
2038 .do_interrupt
= arm_cpu_do_interrupt
,
2039 .do_transaction_failed
= arm_cpu_do_transaction_failed
,
2040 .do_unaligned_access
= arm_cpu_do_unaligned_access
,
2041 .adjust_watchpoint_address
= arm_adjust_watchpoint_address
,
2042 .debug_check_watchpoint
= arm_debug_check_watchpoint
,
2043 .debug_check_breakpoint
= arm_debug_check_breakpoint
,
2044 #endif /* !CONFIG_USER_ONLY */
2046 #endif /* CONFIG_TCG */
2048 static void arm_cpu_class_init(ObjectClass
*oc
, void *data
)
2050 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
2051 CPUClass
*cc
= CPU_CLASS(acc
);
2052 DeviceClass
*dc
= DEVICE_CLASS(oc
);
2054 device_class_set_parent_realize(dc
, arm_cpu_realizefn
,
2055 &acc
->parent_realize
);
2057 device_class_set_props(dc
, arm_cpu_properties
);
2058 device_class_set_parent_reset(dc
, arm_cpu_reset
, &acc
->parent_reset
);
2060 cc
->class_by_name
= arm_cpu_class_by_name
;
2061 cc
->has_work
= arm_cpu_has_work
;
2062 cc
->dump_state
= arm_cpu_dump_state
;
2063 cc
->set_pc
= arm_cpu_set_pc
;
2064 cc
->gdb_read_register
= arm_cpu_gdb_read_register
;
2065 cc
->gdb_write_register
= arm_cpu_gdb_write_register
;
2066 #ifndef CONFIG_USER_ONLY
2067 cc
->sysemu_ops
= &arm_sysemu_ops
;
2069 cc
->gdb_num_core_regs
= 26;
2070 cc
->gdb_core_xml_file
= "arm-core.xml";
2071 cc
->gdb_arch_name
= arm_gdb_arch_name
;
2072 cc
->gdb_get_dynamic_xml
= arm_gdb_get_dynamic_xml
;
2073 cc
->gdb_stop_before_watchpoint
= true;
2074 cc
->disas_set_info
= arm_disas_set_info
;
2077 cc
->tcg_ops
= &arm_tcg_ops
;
2078 #endif /* CONFIG_TCG */
2082 static void arm_host_initfn(Object
*obj
)
2084 ARMCPU
*cpu
= ARM_CPU(obj
);
2086 kvm_arm_set_cpu_features_from_host(cpu
);
2087 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
2088 aarch64_add_sve_properties(obj
);
2090 arm_cpu_post_init(obj
);
2093 static const TypeInfo host_arm_cpu_type_info
= {
2094 .name
= TYPE_ARM_HOST_CPU
,
2095 .parent
= TYPE_AARCH64_CPU
,
2096 .instance_init
= arm_host_initfn
,
2101 static void arm_cpu_instance_init(Object
*obj
)
2103 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(obj
);
2105 acc
->info
->initfn(obj
);
2106 arm_cpu_post_init(obj
);
2109 static void cpu_register_class_init(ObjectClass
*oc
, void *data
)
2111 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
2116 void arm_cpu_register(const ARMCPUInfo
*info
)
2118 TypeInfo type_info
= {
2119 .parent
= TYPE_ARM_CPU
,
2120 .instance_size
= sizeof(ARMCPU
),
2121 .instance_align
= __alignof__(ARMCPU
),
2122 .instance_init
= arm_cpu_instance_init
,
2123 .class_size
= sizeof(ARMCPUClass
),
2124 .class_init
= info
->class_init
?: cpu_register_class_init
,
2125 .class_data
= (void *)info
,
2128 type_info
.name
= g_strdup_printf("%s-" TYPE_ARM_CPU
, info
->name
);
2129 type_register(&type_info
);
2130 g_free((void *)type_info
.name
);
2133 static const TypeInfo arm_cpu_type_info
= {
2134 .name
= TYPE_ARM_CPU
,
2136 .instance_size
= sizeof(ARMCPU
),
2137 .instance_align
= __alignof__(ARMCPU
),
2138 .instance_init
= arm_cpu_initfn
,
2139 .instance_finalize
= arm_cpu_finalizefn
,
2141 .class_size
= sizeof(ARMCPUClass
),
2142 .class_init
= arm_cpu_class_init
,
2145 static void arm_cpu_register_types(void)
2147 type_register_static(&arm_cpu_type_info
);
2150 type_register_static(&host_arm_cpu_type_info
);
2154 type_init(arm_cpu_register_types
)