2 * s390 PCI instructions
4 * Copyright 2014 IBM Corp.
5 * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com>
6 * Hong Bo Li <lihbbj@cn.ibm.com>
7 * Yi Min Zhao <zyimin@cn.ibm.com>
9 * This work is licensed under the terms of the GNU GPL, version 2 or (at
10 * your option) any later version. See the COPYING file in the top-level
14 #include "qemu/osdep.h"
15 #include "qemu-common.h"
17 #include "s390-pci-inst.h"
18 #include "s390-pci-bus.h"
19 #include "exec/memory-internal.h"
20 #include "qemu/error-report.h"
21 #include "sysemu/hw_accel.h"
23 #ifndef DEBUG_S390PCI_INST
24 #define DEBUG_S390PCI_INST 0
27 #define DPRINTF(fmt, ...) \
29 if (DEBUG_S390PCI_INST) { \
30 fprintf(stderr, "s390pci-inst: " fmt, ## __VA_ARGS__); \
34 static void s390_set_status_code(CPUS390XState
*env
,
35 uint8_t r
, uint64_t status_code
)
37 env
->regs
[r
] &= ~0xff000000ULL
;
38 env
->regs
[r
] |= (status_code
& 0xff) << 24;
41 static int list_pci(ClpReqRspListPci
*rrb
, uint8_t *cc
)
43 S390PCIBusDevice
*pbdev
= NULL
;
44 S390pciState
*s
= s390_get_phb();
45 uint32_t res_code
, initial_l2
, g_l2
;
47 uint64_t resume_token
;
50 if (lduw_p(&rrb
->request
.hdr
.len
) != 32) {
51 res_code
= CLP_RC_LEN
;
56 if ((ldl_p(&rrb
->request
.fmt
) & CLP_MASK_FMT
) != 0) {
57 res_code
= CLP_RC_FMT
;
62 if ((ldl_p(&rrb
->request
.fmt
) & ~CLP_MASK_FMT
) != 0 ||
63 ldq_p(&rrb
->request
.reserved1
) != 0) {
64 res_code
= CLP_RC_RESNOT0
;
69 resume_token
= ldq_p(&rrb
->request
.resume_token
);
72 pbdev
= s390_pci_find_dev_by_idx(s
, resume_token
);
74 res_code
= CLP_RC_LISTPCI_BADRT
;
79 pbdev
= s390_pci_find_next_avail_dev(s
, NULL
);
82 if (lduw_p(&rrb
->response
.hdr
.len
) < 48) {
88 initial_l2
= lduw_p(&rrb
->response
.hdr
.len
);
89 if ((initial_l2
- LIST_PCI_HDR_LEN
) % sizeof(ClpFhListEntry
)
91 res_code
= CLP_RC_LEN
;
97 stl_p(&rrb
->response
.fmt
, 0);
98 stq_p(&rrb
->response
.reserved1
, 0);
99 stl_p(&rrb
->response
.mdd
, FH_MASK_SHM
);
100 stw_p(&rrb
->response
.max_fn
, PCI_MAX_FUNCTIONS
);
101 rrb
->response
.flags
= UID_CHECKING_ENABLED
;
102 rrb
->response
.entry_size
= sizeof(ClpFhListEntry
);
105 g_l2
= LIST_PCI_HDR_LEN
;
106 while (g_l2
< initial_l2
&& pbdev
) {
107 stw_p(&rrb
->response
.fh_list
[i
].device_id
,
108 pci_get_word(pbdev
->pdev
->config
+ PCI_DEVICE_ID
));
109 stw_p(&rrb
->response
.fh_list
[i
].vendor_id
,
110 pci_get_word(pbdev
->pdev
->config
+ PCI_VENDOR_ID
));
111 /* Ignore RESERVED devices. */
112 stl_p(&rrb
->response
.fh_list
[i
].config
,
113 pbdev
->state
== ZPCI_FS_STANDBY
? 0 : 1 << 31);
114 stl_p(&rrb
->response
.fh_list
[i
].fid
, pbdev
->fid
);
115 stl_p(&rrb
->response
.fh_list
[i
].fh
, pbdev
->fh
);
117 g_l2
+= sizeof(ClpFhListEntry
);
118 /* Add endian check for DPRINTF? */
119 DPRINTF("g_l2 %d vendor id 0x%x device id 0x%x fid 0x%x fh 0x%x\n",
121 lduw_p(&rrb
->response
.fh_list
[i
].vendor_id
),
122 lduw_p(&rrb
->response
.fh_list
[i
].device_id
),
123 ldl_p(&rrb
->response
.fh_list
[i
].fid
),
124 ldl_p(&rrb
->response
.fh_list
[i
].fh
));
125 pbdev
= s390_pci_find_next_avail_dev(s
, pbdev
);
132 resume_token
= pbdev
->fh
& FH_MASK_INDEX
;
134 stq_p(&rrb
->response
.resume_token
, resume_token
);
135 stw_p(&rrb
->response
.hdr
.len
, g_l2
);
136 stw_p(&rrb
->response
.hdr
.rsp
, CLP_RC_OK
);
139 DPRINTF("list pci failed rc 0x%x\n", rc
);
140 stw_p(&rrb
->response
.hdr
.rsp
, res_code
);
145 int clp_service_call(S390CPU
*cpu
, uint8_t r2
, uintptr_t ra
)
149 S390PCIBusDevice
*pbdev
;
152 uint8_t buffer
[4096 * 2];
154 CPUS390XState
*env
= &cpu
->env
;
155 S390pciState
*s
= s390_get_phb();
158 cpu_synchronize_state(CPU(cpu
));
160 if (env
->psw
.mask
& PSW_MASK_PSTATE
) {
161 s390_program_interrupt(env
, PGM_PRIVILEGED
, 4, ra
);
165 if (s390_cpu_virt_mem_read(cpu
, env
->regs
[r2
], r2
, buffer
, sizeof(*reqh
))) {
166 s390_cpu_virt_mem_handle_exc(cpu
, ra
);
169 reqh
= (ClpReqHdr
*)buffer
;
170 req_len
= lduw_p(&reqh
->len
);
171 if (req_len
< 16 || req_len
> 8184 || (req_len
% 8 != 0)) {
172 s390_program_interrupt(env
, PGM_OPERAND
, 4, ra
);
176 if (s390_cpu_virt_mem_read(cpu
, env
->regs
[r2
], r2
, buffer
,
177 req_len
+ sizeof(*resh
))) {
178 s390_cpu_virt_mem_handle_exc(cpu
, ra
);
181 resh
= (ClpRspHdr
*)(buffer
+ req_len
);
182 res_len
= lduw_p(&resh
->len
);
183 if (res_len
< 8 || res_len
> 8176 || (res_len
% 8 != 0)) {
184 s390_program_interrupt(env
, PGM_OPERAND
, 4, ra
);
187 if ((req_len
+ res_len
) > 8192) {
188 s390_program_interrupt(env
, PGM_OPERAND
, 4, ra
);
192 if (s390_cpu_virt_mem_read(cpu
, env
->regs
[r2
], r2
, buffer
,
193 req_len
+ res_len
)) {
194 s390_cpu_virt_mem_handle_exc(cpu
, ra
);
199 stw_p(&resh
->rsp
, CLP_RC_LEN
);
203 switch (lduw_p(&reqh
->cmd
)) {
205 ClpReqRspListPci
*rrb
= (ClpReqRspListPci
*)buffer
;
209 case CLP_SET_PCI_FN
: {
210 ClpReqSetPci
*reqsetpci
= (ClpReqSetPci
*)reqh
;
211 ClpRspSetPci
*ressetpci
= (ClpRspSetPci
*)resh
;
213 pbdev
= s390_pci_find_dev_by_fh(s
, ldl_p(&reqsetpci
->fh
));
215 stw_p(&ressetpci
->hdr
.rsp
, CLP_RC_SETPCIFN_FH
);
219 switch (reqsetpci
->oc
) {
220 case CLP_SET_ENABLE_PCI_FN
:
221 switch (reqsetpci
->ndas
) {
223 stw_p(&ressetpci
->hdr
.rsp
, CLP_RC_SETPCIFN_DMAAS
);
228 stw_p(&ressetpci
->hdr
.rsp
, CLP_RC_SETPCIFN_RES
);
232 if (pbdev
->fh
& FH_MASK_ENABLE
) {
233 stw_p(&ressetpci
->hdr
.rsp
, CLP_RC_SETPCIFN_FHOP
);
237 pbdev
->fh
|= FH_MASK_ENABLE
;
238 pbdev
->state
= ZPCI_FS_ENABLED
;
239 stl_p(&ressetpci
->fh
, pbdev
->fh
);
240 stw_p(&ressetpci
->hdr
.rsp
, CLP_RC_OK
);
242 case CLP_SET_DISABLE_PCI_FN
:
243 if (!(pbdev
->fh
& FH_MASK_ENABLE
)) {
244 stw_p(&ressetpci
->hdr
.rsp
, CLP_RC_SETPCIFN_FHOP
);
247 device_reset(DEVICE(pbdev
));
248 pbdev
->fh
&= ~FH_MASK_ENABLE
;
249 pbdev
->state
= ZPCI_FS_DISABLED
;
250 stl_p(&ressetpci
->fh
, pbdev
->fh
);
251 stw_p(&ressetpci
->hdr
.rsp
, CLP_RC_OK
);
254 DPRINTF("unknown set pci command\n");
255 stw_p(&ressetpci
->hdr
.rsp
, CLP_RC_SETPCIFN_FHOP
);
260 case CLP_QUERY_PCI_FN
: {
261 ClpReqQueryPci
*reqquery
= (ClpReqQueryPci
*)reqh
;
262 ClpRspQueryPci
*resquery
= (ClpRspQueryPci
*)resh
;
264 pbdev
= s390_pci_find_dev_by_fh(s
, ldl_p(&reqquery
->fh
));
266 DPRINTF("query pci no pci dev\n");
267 stw_p(&resquery
->hdr
.rsp
, CLP_RC_SETPCIFN_FH
);
271 for (i
= 0; i
< PCI_BAR_COUNT
; i
++) {
272 uint32_t data
= pci_get_long(pbdev
->pdev
->config
+
273 PCI_BASE_ADDRESS_0
+ (i
* 4));
275 stl_p(&resquery
->bar
[i
], data
);
276 resquery
->bar_size
[i
] = pbdev
->pdev
->io_regions
[i
].size
?
277 ctz64(pbdev
->pdev
->io_regions
[i
].size
) : 0;
278 DPRINTF("bar %d addr 0x%x size 0x%" PRIx64
"barsize 0x%x\n", i
,
279 ldl_p(&resquery
->bar
[i
]),
280 pbdev
->pdev
->io_regions
[i
].size
,
281 resquery
->bar_size
[i
]);
284 stq_p(&resquery
->sdma
, ZPCI_SDMA_ADDR
);
285 stq_p(&resquery
->edma
, ZPCI_EDMA_ADDR
);
286 stl_p(&resquery
->fid
, pbdev
->fid
);
287 stw_p(&resquery
->pchid
, 0);
288 stw_p(&resquery
->ug
, 1);
289 stl_p(&resquery
->uid
, pbdev
->uid
);
290 stw_p(&resquery
->hdr
.rsp
, CLP_RC_OK
);
293 case CLP_QUERY_PCI_FNGRP
: {
294 ClpRspQueryPciGrp
*resgrp
= (ClpRspQueryPciGrp
*)resh
;
296 stq_p(&resgrp
->dasm
, 0);
297 stq_p(&resgrp
->msia
, ZPCI_MSI_ADDR
);
298 stw_p(&resgrp
->mui
, 0);
299 stw_p(&resgrp
->i
, 128);
300 stw_p(&resgrp
->maxstbl
, 128);
303 stw_p(&resgrp
->hdr
.rsp
, CLP_RC_OK
);
307 DPRINTF("unknown clp command\n");
308 stw_p(&resh
->rsp
, CLP_RC_CMD
);
313 if (s390_cpu_virt_mem_write(cpu
, env
->regs
[r2
], r2
, buffer
,
314 req_len
+ res_len
)) {
315 s390_cpu_virt_mem_handle_exc(cpu
, ra
);
323 * Swap data contained in s390x big endian registers to little endian
326 * @ptr: a pointer to a uint64_t data field
327 * @len: the length of the valid data, must be 1,2,4 or 8
329 static int zpci_endian_swap(uint64_t *ptr
, uint8_t len
)
331 uint64_t data
= *ptr
;
337 data
= bswap16(data
);
340 data
= bswap32(data
);
343 data
= bswap64(data
);
352 int pcilg_service_call(S390CPU
*cpu
, uint8_t r1
, uint8_t r2
, uintptr_t ra
)
354 CPUS390XState
*env
= &cpu
->env
;
355 S390PCIBusDevice
*pbdev
;
364 cpu_synchronize_state(CPU(cpu
));
366 if (env
->psw
.mask
& PSW_MASK_PSTATE
) {
367 s390_program_interrupt(env
, PGM_PRIVILEGED
, 4, ra
);
372 s390_program_interrupt(env
, PGM_SPECIFICATION
, 4, ra
);
376 fh
= env
->regs
[r2
] >> 32;
377 pcias
= (env
->regs
[r2
] >> 16) & 0xf;
378 len
= env
->regs
[r2
] & 0xf;
379 offset
= env
->regs
[r2
+ 1];
381 if (!(fh
& FH_MASK_ENABLE
)) {
382 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
386 pbdev
= s390_pci_find_dev_by_fh(s390_get_phb(), fh
);
388 DPRINTF("pcilg no pci dev\n");
389 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
393 switch (pbdev
->state
) {
394 case ZPCI_FS_PERMANENT_ERROR
:
396 setcc(cpu
, ZPCI_PCI_LS_ERR
);
397 s390_set_status_code(env
, r2
, ZPCI_PCI_ST_BLOCKED
);
404 case ZPCI_IO_BAR_MIN
...ZPCI_IO_BAR_MAX
:
405 if (!len
|| (len
> (8 - (offset
& 0x7)))) {
406 s390_program_interrupt(env
, PGM_OPERAND
, 4, ra
);
409 mr
= pbdev
->pdev
->io_regions
[pcias
].memory
;
410 result
= memory_region_dispatch_read(mr
, offset
, &data
, len
,
411 MEMTXATTRS_UNSPECIFIED
);
412 if (result
!= MEMTX_OK
) {
413 s390_program_interrupt(env
, PGM_OPERAND
, 4, ra
);
417 case ZPCI_CONFIG_BAR
:
418 if (!len
|| (len
> (4 - (offset
& 0x3))) || len
== 3) {
419 s390_program_interrupt(env
, PGM_OPERAND
, 4, ra
);
422 data
= pci_host_config_read_common(
423 pbdev
->pdev
, offset
, pci_config_size(pbdev
->pdev
), len
);
425 if (zpci_endian_swap(&data
, len
)) {
426 s390_program_interrupt(env
, PGM_OPERAND
, 4, ra
);
431 DPRINTF("pcilg invalid space\n");
432 setcc(cpu
, ZPCI_PCI_LS_ERR
);
433 s390_set_status_code(env
, r2
, ZPCI_PCI_ST_INVAL_AS
);
437 env
->regs
[r1
] = data
;
438 setcc(cpu
, ZPCI_PCI_LS_OK
);
442 static int trap_msix(S390PCIBusDevice
*pbdev
, uint64_t offset
, uint8_t pcias
)
444 if (pbdev
->msix
.available
&& pbdev
->msix
.table_bar
== pcias
&&
445 offset
>= pbdev
->msix
.table_offset
&&
446 offset
< (pbdev
->msix
.table_offset
+
447 pbdev
->msix
.entries
* PCI_MSIX_ENTRY_SIZE
)) {
454 int pcistg_service_call(S390CPU
*cpu
, uint8_t r1
, uint8_t r2
, uintptr_t ra
)
456 CPUS390XState
*env
= &cpu
->env
;
457 uint64_t offset
, data
;
458 S390PCIBusDevice
*pbdev
;
465 cpu_synchronize_state(CPU(cpu
));
467 if (env
->psw
.mask
& PSW_MASK_PSTATE
) {
468 s390_program_interrupt(env
, PGM_PRIVILEGED
, 4, ra
);
473 s390_program_interrupt(env
, PGM_SPECIFICATION
, 4, ra
);
477 fh
= env
->regs
[r2
] >> 32;
478 pcias
= (env
->regs
[r2
] >> 16) & 0xf;
479 len
= env
->regs
[r2
] & 0xf;
480 offset
= env
->regs
[r2
+ 1];
481 data
= env
->regs
[r1
];
483 if (!(fh
& FH_MASK_ENABLE
)) {
484 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
488 pbdev
= s390_pci_find_dev_by_fh(s390_get_phb(), fh
);
490 DPRINTF("pcistg no pci dev\n");
491 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
495 switch (pbdev
->state
) {
496 /* ZPCI_FS_RESERVED, ZPCI_FS_STANDBY and ZPCI_FS_DISABLED
497 * are already covered by the FH_MASK_ENABLE check above
499 case ZPCI_FS_PERMANENT_ERROR
:
501 setcc(cpu
, ZPCI_PCI_LS_ERR
);
502 s390_set_status_code(env
, r2
, ZPCI_PCI_ST_BLOCKED
);
509 /* A ZPCI PCI card may use any BAR from BAR 0 to BAR 5 */
510 case ZPCI_IO_BAR_MIN
...ZPCI_IO_BAR_MAX
:
512 * A length of 0 is invalid and length should not cross a double word
514 if (!len
|| (len
> (8 - (offset
& 0x7)))) {
515 s390_program_interrupt(env
, PGM_OPERAND
, 4, ra
);
519 if (trap_msix(pbdev
, offset
, pcias
)) {
520 offset
= offset
- pbdev
->msix
.table_offset
;
521 mr
= &pbdev
->pdev
->msix_table_mmio
;
523 mr
= pbdev
->pdev
->io_regions
[pcias
].memory
;
526 result
= memory_region_dispatch_write(mr
, offset
, data
, len
,
527 MEMTXATTRS_UNSPECIFIED
);
528 if (result
!= MEMTX_OK
) {
529 s390_program_interrupt(env
, PGM_OPERAND
, 4, ra
);
533 case ZPCI_CONFIG_BAR
:
534 /* ZPCI uses the pseudo BAR number 15 as configuration space */
535 /* possible access lengths are 1,2,4 and must not cross a word */
536 if (!len
|| (len
> (4 - (offset
& 0x3))) || len
== 3) {
537 s390_program_interrupt(env
, PGM_OPERAND
, 4, ra
);
540 /* len = 1,2,4 so we do not need to test */
541 zpci_endian_swap(&data
, len
);
542 pci_host_config_write_common(pbdev
->pdev
, offset
,
543 pci_config_size(pbdev
->pdev
),
547 DPRINTF("pcistg invalid space\n");
548 setcc(cpu
, ZPCI_PCI_LS_ERR
);
549 s390_set_status_code(env
, r2
, ZPCI_PCI_ST_INVAL_AS
);
553 setcc(cpu
, ZPCI_PCI_LS_OK
);
557 int rpcit_service_call(S390CPU
*cpu
, uint8_t r1
, uint8_t r2
, uintptr_t ra
)
559 CPUS390XState
*env
= &cpu
->env
;
561 S390PCIBusDevice
*pbdev
;
565 IOMMUMemoryRegion
*iommu_mr
;
566 IOMMUMemoryRegionClass
*imrc
;
568 cpu_synchronize_state(CPU(cpu
));
570 if (env
->psw
.mask
& PSW_MASK_PSTATE
) {
571 s390_program_interrupt(env
, PGM_PRIVILEGED
, 4, ra
);
576 s390_program_interrupt(env
, PGM_SPECIFICATION
, 4, ra
);
580 fh
= env
->regs
[r1
] >> 32;
581 start
= env
->regs
[r2
];
582 end
= start
+ env
->regs
[r2
+ 1];
584 pbdev
= s390_pci_find_dev_by_fh(s390_get_phb(), fh
);
586 DPRINTF("rpcit no pci dev\n");
587 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
591 switch (pbdev
->state
) {
592 case ZPCI_FS_RESERVED
:
593 case ZPCI_FS_STANDBY
:
594 case ZPCI_FS_DISABLED
:
595 case ZPCI_FS_PERMANENT_ERROR
:
596 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
599 setcc(cpu
, ZPCI_PCI_LS_ERR
);
600 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_ERROR_RECOVER
);
606 iommu
= pbdev
->iommu
;
607 if (!iommu
->g_iota
) {
608 pbdev
->state
= ZPCI_FS_ERROR
;
609 setcc(cpu
, ZPCI_PCI_LS_ERR
);
610 s390_set_status_code(env
, r1
, ZPCI_PCI_ST_INSUF_RES
);
611 s390_pci_generate_error_event(ERR_EVENT_INVALAS
, pbdev
->fh
, pbdev
->fid
,
616 if (end
< iommu
->pba
|| start
> iommu
->pal
) {
617 pbdev
->state
= ZPCI_FS_ERROR
;
618 setcc(cpu
, ZPCI_PCI_LS_ERR
);
619 s390_set_status_code(env
, r1
, ZPCI_PCI_ST_INSUF_RES
);
620 s390_pci_generate_error_event(ERR_EVENT_OORANGE
, pbdev
->fh
, pbdev
->fid
,
625 iommu_mr
= &iommu
->iommu_mr
;
626 imrc
= IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr
);
628 while (start
< end
) {
629 entry
= imrc
->translate(iommu_mr
, start
, IOMMU_NONE
);
631 if (!entry
.translated_addr
) {
632 pbdev
->state
= ZPCI_FS_ERROR
;
633 setcc(cpu
, ZPCI_PCI_LS_ERR
);
634 s390_set_status_code(env
, r1
, ZPCI_PCI_ST_INSUF_RES
);
635 s390_pci_generate_error_event(ERR_EVENT_SERR
, pbdev
->fh
, pbdev
->fid
,
636 start
, ERR_EVENT_Q_BIT
);
640 memory_region_notify_iommu(iommu_mr
, entry
);
641 start
+= entry
.addr_mask
+ 1;
644 setcc(cpu
, ZPCI_PCI_LS_OK
);
649 int pcistb_service_call(S390CPU
*cpu
, uint8_t r1
, uint8_t r3
, uint64_t gaddr
,
650 uint8_t ar
, uintptr_t ra
)
652 CPUS390XState
*env
= &cpu
->env
;
653 S390PCIBusDevice
*pbdev
;
663 if (env
->psw
.mask
& PSW_MASK_PSTATE
) {
664 s390_program_interrupt(env
, PGM_PRIVILEGED
, 6, ra
);
668 fh
= env
->regs
[r1
] >> 32;
669 pcias
= (env
->regs
[r1
] >> 16) & 0xf;
670 len
= env
->regs
[r1
] & 0xff;
671 offset
= env
->regs
[r3
];
673 if (!(fh
& FH_MASK_ENABLE
)) {
674 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
678 pbdev
= s390_pci_find_dev_by_fh(s390_get_phb(), fh
);
680 DPRINTF("pcistb no pci dev fh 0x%x\n", fh
);
681 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
685 switch (pbdev
->state
) {
686 case ZPCI_FS_PERMANENT_ERROR
:
688 setcc(cpu
, ZPCI_PCI_LS_ERR
);
689 s390_set_status_code(env
, r1
, ZPCI_PCI_ST_BLOCKED
);
695 if (pcias
> ZPCI_IO_BAR_MAX
) {
696 DPRINTF("pcistb invalid space\n");
697 setcc(cpu
, ZPCI_PCI_LS_ERR
);
698 s390_set_status_code(env
, r1
, ZPCI_PCI_ST_INVAL_AS
);
702 /* Verify the address, offset and length */
703 /* offset must be a multiple of 8 */
705 goto specification_error
;
707 /* Length must be greater than 8, a multiple of 8 */
708 /* and not greater than maxstbl */
709 if ((len
<= 8) || (len
% 8) || (len
> pbdev
->maxstbl
)) {
710 goto specification_error
;
712 /* Do not cross a 4K-byte boundary */
713 if (((offset
& 0xfff) + len
) > 0x1000) {
714 goto specification_error
;
716 /* Guest address must be double word aligned */
717 if (gaddr
& 0x07UL
) {
718 goto specification_error
;
721 mr
= pbdev
->pdev
->io_regions
[pcias
].memory
;
722 if (!memory_region_access_valid(mr
, offset
, len
, true)) {
723 s390_program_interrupt(env
, PGM_OPERAND
, 6, ra
);
727 if (s390_cpu_virt_mem_read(cpu
, gaddr
, ar
, buffer
, len
)) {
728 s390_cpu_virt_mem_handle_exc(cpu
, ra
);
732 for (i
= 0; i
< len
/ 8; i
++) {
733 result
= memory_region_dispatch_write(mr
, offset
+ i
* 8,
734 ldq_p(buffer
+ i
* 8), 8,
735 MEMTXATTRS_UNSPECIFIED
);
736 if (result
!= MEMTX_OK
) {
737 s390_program_interrupt(env
, PGM_OPERAND
, 6, ra
);
742 setcc(cpu
, ZPCI_PCI_LS_OK
);
746 s390_program_interrupt(env
, PGM_SPECIFICATION
, 6, ra
);
750 static int reg_irqs(CPUS390XState
*env
, S390PCIBusDevice
*pbdev
, ZpciFib fib
)
753 uint8_t isc
= FIB_DATA_ISC(ldl_p(&fib
.data
));
755 pbdev
->routes
.adapter
.adapter_id
= css_get_adapter_id(
756 CSS_IO_ADAPTER_PCI
, isc
);
757 pbdev
->summary_ind
= get_indicator(ldq_p(&fib
.aisb
), sizeof(uint64_t));
758 len
= BITS_TO_LONGS(FIB_DATA_NOI(ldl_p(&fib
.data
))) * sizeof(unsigned long);
759 pbdev
->indicator
= get_indicator(ldq_p(&fib
.aibv
), len
);
761 ret
= map_indicator(&pbdev
->routes
.adapter
, pbdev
->summary_ind
);
766 ret
= map_indicator(&pbdev
->routes
.adapter
, pbdev
->indicator
);
771 pbdev
->routes
.adapter
.summary_addr
= ldq_p(&fib
.aisb
);
772 pbdev
->routes
.adapter
.summary_offset
= FIB_DATA_AISBO(ldl_p(&fib
.data
));
773 pbdev
->routes
.adapter
.ind_addr
= ldq_p(&fib
.aibv
);
774 pbdev
->routes
.adapter
.ind_offset
= FIB_DATA_AIBVO(ldl_p(&fib
.data
));
776 pbdev
->noi
= FIB_DATA_NOI(ldl_p(&fib
.data
));
777 pbdev
->sum
= FIB_DATA_SUM(ldl_p(&fib
.data
));
779 DPRINTF("reg_irqs adapter id %d\n", pbdev
->routes
.adapter
.adapter_id
);
782 release_indicator(&pbdev
->routes
.adapter
, pbdev
->summary_ind
);
783 release_indicator(&pbdev
->routes
.adapter
, pbdev
->indicator
);
784 pbdev
->summary_ind
= NULL
;
785 pbdev
->indicator
= NULL
;
789 int pci_dereg_irqs(S390PCIBusDevice
*pbdev
)
791 release_indicator(&pbdev
->routes
.adapter
, pbdev
->summary_ind
);
792 release_indicator(&pbdev
->routes
.adapter
, pbdev
->indicator
);
794 pbdev
->summary_ind
= NULL
;
795 pbdev
->indicator
= NULL
;
796 pbdev
->routes
.adapter
.summary_addr
= 0;
797 pbdev
->routes
.adapter
.summary_offset
= 0;
798 pbdev
->routes
.adapter
.ind_addr
= 0;
799 pbdev
->routes
.adapter
.ind_offset
= 0;
804 DPRINTF("dereg_irqs adapter id %d\n", pbdev
->routes
.adapter
.adapter_id
);
808 static int reg_ioat(CPUS390XState
*env
, S390PCIIOMMU
*iommu
, ZpciFib fib
,
811 uint64_t pba
= ldq_p(&fib
.pba
);
812 uint64_t pal
= ldq_p(&fib
.pal
);
813 uint64_t g_iota
= ldq_p(&fib
.iota
);
814 uint8_t dt
= (g_iota
>> 2) & 0x7;
815 uint8_t t
= (g_iota
>> 11) & 0x1;
817 if (pba
> pal
|| pba
< ZPCI_SDMA_ADDR
|| pal
> ZPCI_EDMA_ADDR
) {
818 s390_program_interrupt(env
, PGM_OPERAND
, 6, ra
);
822 /* currently we only support designation type 1 with translation */
823 if (!(dt
== ZPCI_IOTA_RTTO
&& t
)) {
824 error_report("unsupported ioat dt %d t %d", dt
, t
);
825 s390_program_interrupt(env
, PGM_OPERAND
, 6, ra
);
831 iommu
->g_iota
= g_iota
;
833 s390_pci_iommu_enable(iommu
);
838 void pci_dereg_ioat(S390PCIIOMMU
*iommu
)
840 s390_pci_iommu_disable(iommu
);
846 int mpcifc_service_call(S390CPU
*cpu
, uint8_t r1
, uint64_t fiba
, uint8_t ar
,
849 CPUS390XState
*env
= &cpu
->env
;
853 S390PCIBusDevice
*pbdev
;
854 uint64_t cc
= ZPCI_PCI_LS_OK
;
856 if (env
->psw
.mask
& PSW_MASK_PSTATE
) {
857 s390_program_interrupt(env
, PGM_PRIVILEGED
, 6, ra
);
861 oc
= env
->regs
[r1
] & 0xff;
862 dmaas
= (env
->regs
[r1
] >> 16) & 0xff;
863 fh
= env
->regs
[r1
] >> 32;
866 s390_program_interrupt(env
, PGM_SPECIFICATION
, 6, ra
);
870 pbdev
= s390_pci_find_dev_by_fh(s390_get_phb(), fh
);
872 DPRINTF("mpcifc no pci dev fh 0x%x\n", fh
);
873 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
877 switch (pbdev
->state
) {
878 case ZPCI_FS_RESERVED
:
879 case ZPCI_FS_STANDBY
:
880 case ZPCI_FS_DISABLED
:
881 case ZPCI_FS_PERMANENT_ERROR
:
882 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
888 if (s390_cpu_virt_mem_read(cpu
, fiba
, ar
, (uint8_t *)&fib
, sizeof(fib
))) {
889 s390_cpu_virt_mem_handle_exc(cpu
, ra
);
894 s390_program_interrupt(env
, PGM_OPERAND
, 6, ra
);
899 case ZPCI_MOD_FC_REG_INT
:
900 if (pbdev
->summary_ind
) {
901 cc
= ZPCI_PCI_LS_ERR
;
902 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_SEQUENCE
);
903 } else if (reg_irqs(env
, pbdev
, fib
)) {
904 cc
= ZPCI_PCI_LS_ERR
;
905 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_RES_NOT_AVAIL
);
908 case ZPCI_MOD_FC_DEREG_INT
:
909 if (!pbdev
->summary_ind
) {
910 cc
= ZPCI_PCI_LS_ERR
;
911 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_SEQUENCE
);
913 pci_dereg_irqs(pbdev
);
916 case ZPCI_MOD_FC_REG_IOAT
:
918 cc
= ZPCI_PCI_LS_ERR
;
919 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_DMAAS_INVAL
);
920 } else if (pbdev
->iommu
->enabled
) {
921 cc
= ZPCI_PCI_LS_ERR
;
922 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_SEQUENCE
);
923 } else if (reg_ioat(env
, pbdev
->iommu
, fib
, ra
)) {
924 cc
= ZPCI_PCI_LS_ERR
;
925 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_INSUF_RES
);
928 case ZPCI_MOD_FC_DEREG_IOAT
:
930 cc
= ZPCI_PCI_LS_ERR
;
931 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_DMAAS_INVAL
);
932 } else if (!pbdev
->iommu
->enabled
) {
933 cc
= ZPCI_PCI_LS_ERR
;
934 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_SEQUENCE
);
936 pci_dereg_ioat(pbdev
->iommu
);
939 case ZPCI_MOD_FC_REREG_IOAT
:
941 cc
= ZPCI_PCI_LS_ERR
;
942 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_DMAAS_INVAL
);
943 } else if (!pbdev
->iommu
->enabled
) {
944 cc
= ZPCI_PCI_LS_ERR
;
945 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_SEQUENCE
);
947 pci_dereg_ioat(pbdev
->iommu
);
948 if (reg_ioat(env
, pbdev
->iommu
, fib
, ra
)) {
949 cc
= ZPCI_PCI_LS_ERR
;
950 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_INSUF_RES
);
954 case ZPCI_MOD_FC_RESET_ERROR
:
955 switch (pbdev
->state
) {
956 case ZPCI_FS_BLOCKED
:
958 pbdev
->state
= ZPCI_FS_ENABLED
;
961 cc
= ZPCI_PCI_LS_ERR
;
962 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_SEQUENCE
);
965 case ZPCI_MOD_FC_RESET_BLOCK
:
966 switch (pbdev
->state
) {
968 pbdev
->state
= ZPCI_FS_BLOCKED
;
971 cc
= ZPCI_PCI_LS_ERR
;
972 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_SEQUENCE
);
975 case ZPCI_MOD_FC_SET_MEASURE
:
976 pbdev
->fmb_addr
= ldq_p(&fib
.fmb_addr
);
979 s390_program_interrupt(&cpu
->env
, PGM_OPERAND
, 6, ra
);
980 cc
= ZPCI_PCI_LS_ERR
;
987 int stpcifc_service_call(S390CPU
*cpu
, uint8_t r1
, uint64_t fiba
, uint8_t ar
,
990 CPUS390XState
*env
= &cpu
->env
;
994 S390PCIBusDevice
*pbdev
;
996 uint64_t cc
= ZPCI_PCI_LS_OK
;
998 if (env
->psw
.mask
& PSW_MASK_PSTATE
) {
999 s390_program_interrupt(env
, PGM_PRIVILEGED
, 6, ra
);
1003 fh
= env
->regs
[r1
] >> 32;
1004 dmaas
= (env
->regs
[r1
] >> 16) & 0xff;
1007 setcc(cpu
, ZPCI_PCI_LS_ERR
);
1008 s390_set_status_code(env
, r1
, ZPCI_STPCIFC_ST_INVAL_DMAAS
);
1013 s390_program_interrupt(env
, PGM_SPECIFICATION
, 6, ra
);
1017 pbdev
= s390_pci_find_dev_by_idx(s390_get_phb(), fh
& FH_MASK_INDEX
);
1019 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
1023 memset(&fib
, 0, sizeof(fib
));
1025 switch (pbdev
->state
) {
1026 case ZPCI_FS_RESERVED
:
1027 case ZPCI_FS_STANDBY
:
1028 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
1030 case ZPCI_FS_DISABLED
:
1031 if (fh
& FH_MASK_ENABLE
) {
1032 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
1036 /* BLOCKED bit is set to one coincident with the setting of ERROR bit.
1037 * FH Enabled bit is set to one in states of ENABLED, BLOCKED or ERROR. */
1040 case ZPCI_FS_BLOCKED
:
1042 case ZPCI_FS_ENABLED
:
1044 if (pbdev
->iommu
->enabled
) {
1047 if (!(fh
& FH_MASK_ENABLE
)) {
1048 env
->regs
[r1
] |= 1ULL << 63;
1051 case ZPCI_FS_PERMANENT_ERROR
:
1052 setcc(cpu
, ZPCI_PCI_LS_ERR
);
1053 s390_set_status_code(env
, r1
, ZPCI_STPCIFC_ST_PERM_ERROR
);
1057 stq_p(&fib
.pba
, pbdev
->iommu
->pba
);
1058 stq_p(&fib
.pal
, pbdev
->iommu
->pal
);
1059 stq_p(&fib
.iota
, pbdev
->iommu
->g_iota
);
1060 stq_p(&fib
.aibv
, pbdev
->routes
.adapter
.ind_addr
);
1061 stq_p(&fib
.aisb
, pbdev
->routes
.adapter
.summary_addr
);
1062 stq_p(&fib
.fmb_addr
, pbdev
->fmb_addr
);
1064 data
= ((uint32_t)pbdev
->isc
<< 28) | ((uint32_t)pbdev
->noi
<< 16) |
1065 ((uint32_t)pbdev
->routes
.adapter
.ind_offset
<< 8) |
1066 ((uint32_t)pbdev
->sum
<< 7) | pbdev
->routes
.adapter
.summary_offset
;
1067 stl_p(&fib
.data
, data
);
1070 if (s390_cpu_virt_mem_write(cpu
, fiba
, ar
, (uint8_t *)&fib
, sizeof(fib
))) {
1071 s390_cpu_virt_mem_handle_exc(cpu
, ra
);