linux-user/ppc/signal.c

   1 /*
   2  *  Emulation of Linux signals
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *  GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "qemu/osdep.h"
  20 #include "qemu.h"
  21 #include "user-internals.h"
  22 #include "signal-common.h"
  23 #include "linux-user/trace.h"
  24
  25 /* Size of dummy stack frame allocated when calling signal handler.
  26    See arch/powerpc/include/asm/ptrace.h.  */
  27 #if defined(TARGET_PPC64)
  28 #define SIGNAL_FRAMESIZE 128
  29 #else
  30 #define SIGNAL_FRAMESIZE 64
  31 #endif
  32
  33 /* See arch/powerpc/include/asm/ucontext.h.  Only used for 32-bit PPC;
  34    on 64-bit PPC, sigcontext and mcontext are one and the same.  */
  35 struct target_mcontext {
  36     target_ulong mc_gregs[48];
  37     /* Includes fpscr.  */
  38     uint64_t mc_fregs[33];
  39
  40 #if defined(TARGET_PPC64)
  41     /* Pointer to the vector regs */
  42     target_ulong v_regs;
  43     /*
  44      * On ppc64, this mcontext structure is naturally *unaligned*,
  45      * or rather it is aligned on a 8 bytes boundary but not on
  46      * a 16 byte boundary.  This pad fixes it up.  This is why we
  47      * cannot use ppc_avr_t, which would force alignment.  This is
  48      * also why the vector regs are referenced in the ABI by the
  49      * v_regs pointer above so any amount of padding can be added here.
  50      */
  51     target_ulong pad;
  52     /* VSCR and VRSAVE are saved separately.  Also reserve space for VSX. */
  53     struct {
  54         uint64_t altivec[34 + 16][2];
  55     } mc_vregs;
  56 #else
  57     target_ulong mc_pad[2];
  58
  59     /* We need to handle Altivec and SPE at the same time, which no
  60        kernel needs to do.  Fortunately, the kernel defines this bit to
  61        be Altivec-register-large all the time, rather than trying to
  62        twiddle it based on the specific platform.  */
  63     union {
  64         /* SPE vector registers.  One extra for SPEFSCR.  */
  65         uint32_t spe[33];
  66         /*
  67          * Altivec vector registers.  One extra for VRSAVE.
  68          * On ppc32, we are already aligned to 16 bytes.  We could
  69          * use ppc_avr_t, but choose to share the same type as ppc64.
  70          */
  71         uint64_t altivec[33][2];
  72     } mc_vregs;
  73 #endif
  74 };
  75
  76 /* See arch/powerpc/include/asm/sigcontext.h.  */
  77 struct target_sigcontext {
  78     target_ulong _unused[4];
  79     int32_t signal;
  80 #if defined(TARGET_PPC64)
  81     int32_t pad0;
  82 #endif
  83     target_ulong handler;
  84     target_ulong oldmask;
  85     target_ulong regs;      /* struct pt_regs __user * */
  86 #if defined(TARGET_PPC64)
  87     struct target_mcontext mcontext;
  88 #endif
  89 };
  90
  91 /* Indices for target_mcontext.mc_gregs, below.
  92    See arch/powerpc/include/asm/ptrace.h for details.  */
  93 enum {
  94     TARGET_PT_R0 = 0,
  95     TARGET_PT_R1 = 1,
  96     TARGET_PT_R2 = 2,
  97     TARGET_PT_R3 = 3,
  98     TARGET_PT_R4 = 4,
  99     TARGET_PT_R5 = 5,
 100     TARGET_PT_R6 = 6,
 101     TARGET_PT_R7 = 7,
 102     TARGET_PT_R8 = 8,
 103     TARGET_PT_R9 = 9,
 104     TARGET_PT_R10 = 10,
 105     TARGET_PT_R11 = 11,
 106     TARGET_PT_R12 = 12,
 107     TARGET_PT_R13 = 13,
 108     TARGET_PT_R14 = 14,
 109     TARGET_PT_R15 = 15,
 110     TARGET_PT_R16 = 16,
 111     TARGET_PT_R17 = 17,
 112     TARGET_PT_R18 = 18,
 113     TARGET_PT_R19 = 19,
 114     TARGET_PT_R20 = 20,
 115     TARGET_PT_R21 = 21,
 116     TARGET_PT_R22 = 22,
 117     TARGET_PT_R23 = 23,
 118     TARGET_PT_R24 = 24,
 119     TARGET_PT_R25 = 25,
 120     TARGET_PT_R26 = 26,
 121     TARGET_PT_R27 = 27,
 122     TARGET_PT_R28 = 28,
 123     TARGET_PT_R29 = 29,
 124     TARGET_PT_R30 = 30,
 125     TARGET_PT_R31 = 31,
 126     TARGET_PT_NIP = 32,
 127     TARGET_PT_MSR = 33,
 128     TARGET_PT_ORIG_R3 = 34,
 129     TARGET_PT_CTR = 35,
 130     TARGET_PT_LNK = 36,
 131     TARGET_PT_XER = 37,
 132     TARGET_PT_CCR = 38,
 133     /* Yes, there are two registers with #39.  One is 64-bit only.  */
 134     TARGET_PT_MQ = 39,
 135     TARGET_PT_SOFTE = 39,
 136     TARGET_PT_TRAP = 40,
 137     TARGET_PT_DAR = 41,
 138     TARGET_PT_DSISR = 42,
 139     TARGET_PT_RESULT = 43,
 140     TARGET_PT_REGS_COUNT = 44
 141 };
 142
 143
 144 struct target_ucontext {
 145     target_ulong tuc_flags;
 146     target_ulong tuc_link;    /* ucontext_t __user * */
 147     struct target_sigaltstack tuc_stack;
 148 #if !defined(TARGET_PPC64)
 149     int32_t tuc_pad[7];
 150     target_ulong tuc_regs;    /* struct mcontext __user *
 151                                 points to uc_mcontext field */
 152 #endif
 153     target_sigset_t tuc_sigmask;
 154 #if defined(TARGET_PPC64)
 155     target_sigset_t unused[15]; /* Allow for uc_sigmask growth */
 156     struct target_sigcontext tuc_sigcontext;
 157 #else
 158     int32_t tuc_maskext[30];
 159     int32_t tuc_pad2[3];
 160     struct target_mcontext tuc_mcontext;
 161 #endif
 162 };
 163
 164 /* See arch/powerpc/kernel/signal_32.c.  */
 165 struct target_sigframe {
 166     struct target_sigcontext sctx;
 167     struct target_mcontext mctx;
 168     int32_t abigap[56];
 169 };
 170
 171 #if defined(TARGET_PPC64)
 172
 173 #define TARGET_TRAMP_SIZE 6
 174
 175 struct target_rt_sigframe {
 176     /* sys_rt_sigreturn requires the ucontext be the first field */
 177     struct target_ucontext uc;
 178     target_ulong  _unused[2];
 179     uint32_t trampoline[TARGET_TRAMP_SIZE];
 180     target_ulong pinfo; /* struct siginfo __user * */
 181     target_ulong puc; /* void __user * */
 182     struct target_siginfo info;
 183     /* 64 bit ABI allows for 288 bytes below sp before decrementing it. */
 184     char abigap[288];
 185 } __attribute__((aligned(16)));
 186
 187 #else
 188
 189 struct target_rt_sigframe {
 190     struct target_siginfo info;
 191     struct target_ucontext uc;
 192     int32_t abigap[56];
 193 };
 194
 195 #endif
 196
 197 #if defined(TARGET_PPC64)
 198
 199 struct target_func_ptr {
 200     target_ulong entry;
 201     target_ulong toc;
 202 };
 203
 204 #endif
 205
 206 /* See arch/powerpc/kernel/signal.c.  */
 207 static target_ulong get_sigframe(struct target_sigaction *ka,
 208                                  CPUPPCState *env,
 209                                  int frame_size)
 210 {
 211     target_ulong oldsp;
 212
 213     oldsp = target_sigsp(get_sp_from_cpustate(env), ka);
 214
 215     return (oldsp - frame_size) & ~0xFUL;
 216 }
 217
 218 #if TARGET_BIG_ENDIAN == HOST_BIG_ENDIAN
 219 #define PPC_VEC_HI      0
 220 #define PPC_VEC_LO      1
 221 #else
 222 #define PPC_VEC_HI      1
 223 #define PPC_VEC_LO      0
 224 #endif
 225
 226
 227 static void save_user_regs(CPUPPCState *env, struct target_mcontext *frame)
 228 {
 229     target_ulong msr = env->msr;
 230     int i;
 231     uint32_t ccr = 0;
 232
 233     /* In general, the kernel attempts to be intelligent about what it
 234        needs to save for Altivec/FP/SPE registers.  We don't care that
 235        much, so we just go ahead and save everything.  */
 236
 237     /* Save general registers.  */
 238     for (i = 0; i < ARRAY_SIZE(env->gpr); i++) {
 239         __put_user(env->gpr[i], &frame->mc_gregs[i]);
 240     }
 241     __put_user(env->nip, &frame->mc_gregs[TARGET_PT_NIP]);
 242     __put_user(env->ctr, &frame->mc_gregs[TARGET_PT_CTR]);
 243     __put_user(env->lr, &frame->mc_gregs[TARGET_PT_LNK]);
 244     __put_user(cpu_read_xer(env), &frame->mc_gregs[TARGET_PT_XER]);
 245
 246     ccr = ppc_get_cr(env);
 247     __put_user(ccr, &frame->mc_gregs[TARGET_PT_CCR]);
 248
 249     /* Save Altivec registers if necessary.  */
 250     if (env->insns_flags & PPC_ALTIVEC) {
 251         uint32_t *vrsave;
 252         for (i = 0; i < 32; i++) {
 253             ppc_avr_t *avr = cpu_avr_ptr(env, i);
 254             ppc_avr_t *vreg = (ppc_avr_t *)&frame->mc_vregs.altivec[i];
 255
 256             __put_user(avr->u64[PPC_VEC_HI], &vreg->u64[0]);
 257             __put_user(avr->u64[PPC_VEC_LO], &vreg->u64[1]);
 258         }
 259 #if defined(TARGET_PPC64)
 260         vrsave = (uint32_t *)&frame->mc_vregs.altivec[33];
 261         /* 64-bit needs to put a pointer to the vectors in the frame */
 262         __put_user(h2g(frame->mc_vregs.altivec), &frame->v_regs);
 263 #else
 264         vrsave = (uint32_t *)&frame->mc_vregs.altivec[32];
 265 #endif
 266         __put_user((uint32_t)env->spr[SPR_VRSAVE], vrsave);
 267     }
 268
 269 #if defined(TARGET_PPC64)
 270     /* Save VSX second halves */
 271     if (env->insns_flags2 & PPC2_VSX) {
 272         uint64_t *vsregs = (uint64_t *)&frame->mc_vregs.altivec[34];
 273         for (i = 0; i < 32; i++) {
 274             uint64_t *vsrl = cpu_vsrl_ptr(env, i);
 275             __put_user(*vsrl, &vsregs[i]);
 276         }
 277     }
 278 #endif
 279
 280     /* Save floating point registers.  */
 281     if (env->insns_flags & PPC_FLOAT) {
 282         for (i = 0; i < 32; i++) {
 283             uint64_t *fpr = cpu_fpr_ptr(env, i);
 284             __put_user(*fpr, &frame->mc_fregs[i]);
 285         }
 286         __put_user((uint64_t) env->fpscr, &frame->mc_fregs[32]);
 287     }
 288
 289 #if !defined(TARGET_PPC64)
 290     /* Save SPE registers.  The kernel only saves the high half.  */
 291     if (env->insns_flags & PPC_SPE) {
 292         for (i = 0; i < ARRAY_SIZE(env->gprh); i++) {
 293             __put_user(env->gprh[i], &frame->mc_vregs.spe[i]);
 294         }
 295         __put_user(env->spe_fscr, &frame->mc_vregs.spe[32]);
 296     }
 297 #endif
 298
 299     /* Store MSR.  */
 300     __put_user(msr, &frame->mc_gregs[TARGET_PT_MSR]);
 301 }
 302
 303 static void encode_trampoline(int sigret, uint32_t *tramp)
 304 {
 305     /* Set up the sigreturn trampoline: li r0,sigret; sc.  */
 306     __put_user(0x38000000 | sigret, &tramp[0]);
 307     __put_user(0x44000002, &tramp[1]);
 308 }
 309
 310 static void restore_user_regs(CPUPPCState *env,
 311                               struct target_mcontext *frame, int sig)
 312 {
 313     target_ulong save_r2 = 0;
 314     target_ulong msr;
 315     target_ulong xer;
 316     target_ulong ccr;
 317
 318     int i;
 319
 320     if (!sig) {
 321         save_r2 = env->gpr[2];
 322     }
 323
 324     /* Restore general registers.  */
 325     for (i = 0; i < ARRAY_SIZE(env->gpr); i++) {
 326         __get_user(env->gpr[i], &frame->mc_gregs[i]);
 327     }
 328     __get_user(env->nip, &frame->mc_gregs[TARGET_PT_NIP]);
 329     __get_user(env->ctr, &frame->mc_gregs[TARGET_PT_CTR]);
 330     __get_user(env->lr, &frame->mc_gregs[TARGET_PT_LNK]);
 331
 332     __get_user(xer, &frame->mc_gregs[TARGET_PT_XER]);
 333     cpu_write_xer(env, xer);
 334
 335     __get_user(ccr, &frame->mc_gregs[TARGET_PT_CCR]);
 336     ppc_set_cr(env, ccr);
 337     if (!sig) {
 338         env->gpr[2] = save_r2;
 339     }
 340     /* Restore MSR.  */
 341     __get_user(msr, &frame->mc_gregs[TARGET_PT_MSR]);
 342
 343     /* If doing signal return, restore the previous little-endian mode.  */
 344     if (sig) {
 345         ppc_store_msr(env, ((env->msr & ~(1ull << MSR_LE)) |
 346                             (msr & (1ull << MSR_LE))));
 347     }
 348
 349     /* Restore Altivec registers if necessary.  */
 350     if (env->insns_flags & PPC_ALTIVEC) {
 351         ppc_avr_t *v_regs;
 352         uint32_t *vrsave;
 353 #if defined(TARGET_PPC64)
 354         uint64_t v_addr;
 355         /* 64-bit needs to recover the pointer to the vectors from the frame */
 356         __get_user(v_addr, &frame->v_regs);
 357         v_regs = g2h(env_cpu(env), v_addr);
 358 #else
 359         v_regs = (ppc_avr_t *)frame->mc_vregs.altivec;
 360 #endif
 361         for (i = 0; i < 32; i++) {
 362             ppc_avr_t *avr = cpu_avr_ptr(env, i);
 363             ppc_avr_t *vreg = &v_regs[i];
 364
 365             __get_user(avr->u64[PPC_VEC_HI], &vreg->u64[0]);
 366             __get_user(avr->u64[PPC_VEC_LO], &vreg->u64[1]);
 367         }
 368 #if defined(TARGET_PPC64)
 369         vrsave = (uint32_t *)&v_regs[33];
 370 #else
 371         vrsave = (uint32_t *)&v_regs[32];
 372 #endif
 373         __get_user(env->spr[SPR_VRSAVE], vrsave);
 374     }
 375
 376 #if defined(TARGET_PPC64)
 377     /* Restore VSX second halves */
 378     if (env->insns_flags2 & PPC2_VSX) {
 379         uint64_t *vsregs = (uint64_t *)&frame->mc_vregs.altivec[34];
 380         for (i = 0; i < 32; i++) {
 381             uint64_t *vsrl = cpu_vsrl_ptr(env, i);
 382             __get_user(*vsrl, &vsregs[i]);
 383         }
 384     }
 385 #endif
 386
 387     /* Restore floating point registers.  */
 388     if (env->insns_flags & PPC_FLOAT) {
 389         uint64_t fpscr;
 390         for (i = 0; i < 32; i++) {
 391             uint64_t *fpr = cpu_fpr_ptr(env, i);
 392             __get_user(*fpr, &frame->mc_fregs[i]);
 393         }
 394         __get_user(fpscr, &frame->mc_fregs[32]);
 395         env->fpscr = (uint32_t) fpscr;
 396     }
 397
 398 #if !defined(TARGET_PPC64)
 399     /* Save SPE registers.  The kernel only saves the high half.  */
 400     if (env->insns_flags & PPC_SPE) {
 401         for (i = 0; i < ARRAY_SIZE(env->gprh); i++) {
 402             __get_user(env->gprh[i], &frame->mc_vregs.spe[i]);
 403         }
 404         __get_user(env->spe_fscr, &frame->mc_vregs.spe[32]);
 405     }
 406 #endif
 407 }
 408
 409 #if !defined(TARGET_PPC64)
 410 void setup_frame(int sig, struct target_sigaction *ka,
 411                  target_sigset_t *set, CPUPPCState *env)
 412 {
 413     struct target_sigframe *frame;
 414     struct target_sigcontext *sc;
 415     target_ulong frame_addr, newsp;
 416     int err = 0;
 417
 418     frame_addr = get_sigframe(ka, env, sizeof(*frame));
 419     trace_user_setup_frame(env, frame_addr);
 420     if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 1))
 421         goto sigsegv;
 422     sc = &frame->sctx;
 423
 424     __put_user(ka->_sa_handler, &sc->handler);
 425     __put_user(set->sig[0], &sc->oldmask);
 426     __put_user(set->sig[1], &sc->_unused[3]);
 427     __put_user(h2g(&frame->mctx), &sc->regs);
 428     __put_user(sig, &sc->signal);
 429
 430     /* Save user regs.  */
 431     save_user_regs(env, &frame->mctx);
 432
 433     env->lr = default_sigreturn;
 434
 435     /* Turn off all fp exceptions.  */
 436     env->fpscr = 0;
 437
 438     /* Create a stack frame for the caller of the handler.  */
 439     newsp = frame_addr - SIGNAL_FRAMESIZE;
 440     err |= put_user(env->gpr[1], newsp, target_ulong);
 441
 442     if (err)
 443         goto sigsegv;
 444
 445     /* Set up registers for signal handler.  */
 446     env->gpr[1] = newsp;
 447     env->gpr[3] = sig;
 448     env->gpr[4] = frame_addr + offsetof(struct target_sigframe, sctx);
 449
 450     env->nip = (target_ulong) ka->_sa_handler;
 451
 452     /* Signal handlers are entered in big-endian mode.  */
 453     ppc_store_msr(env, env->msr & ~(1ull << MSR_LE));
 454
 455     unlock_user_struct(frame, frame_addr, 1);
 456     return;
 457
 458 sigsegv:
 459     unlock_user_struct(frame, frame_addr, 1);
 460     force_sigsegv(sig);
 461 }
 462 #endif /* !defined(TARGET_PPC64) */
 463
 464 void setup_rt_frame(int sig, struct target_sigaction *ka,
 465                     target_siginfo_t *info,
 466                     target_sigset_t *set, CPUPPCState *env)
 467 {
 468     struct target_rt_sigframe *rt_sf;
 469     struct target_mcontext *mctx = 0;
 470     target_ulong rt_sf_addr, newsp = 0;
 471     int i, err = 0;
 472 #if defined(TARGET_PPC64)
 473     struct target_sigcontext *sc = 0;
 474     struct image_info *image = ((TaskState *)thread_cpu->opaque)->info;
 475 #endif
 476
 477     rt_sf_addr = get_sigframe(ka, env, sizeof(*rt_sf));
 478     if (!lock_user_struct(VERIFY_WRITE, rt_sf, rt_sf_addr, 1))
 479         goto sigsegv;
 480
 481     tswap_siginfo(&rt_sf->info, info);
 482
 483     __put_user(0, &rt_sf->uc.tuc_flags);
 484     __put_user(0, &rt_sf->uc.tuc_link);
 485     target_save_altstack(&rt_sf->uc.tuc_stack, env);
 486 #if !defined(TARGET_PPC64)
 487     __put_user(h2g (&rt_sf->uc.tuc_mcontext),
 488                &rt_sf->uc.tuc_regs);
 489 #endif
 490     for(i = 0; i < TARGET_NSIG_WORDS; i++) {
 491         __put_user(set->sig[i], &rt_sf->uc.tuc_sigmask.sig[i]);
 492     }
 493
 494 #if defined(TARGET_PPC64)
 495     mctx = &rt_sf->uc.tuc_sigcontext.mcontext;
 496
 497     sc = &rt_sf->uc.tuc_sigcontext;
 498     __put_user(h2g(mctx), &sc->regs);
 499     __put_user(sig, &sc->signal);
 500 #else
 501     mctx = &rt_sf->uc.tuc_mcontext;
 502 #endif
 503
 504     save_user_regs(env, mctx);
 505
 506     env->lr = default_rt_sigreturn;
 507
 508     /* Turn off all fp exceptions.  */
 509     env->fpscr = 0;
 510
 511     /* Create a stack frame for the caller of the handler.  */
 512     newsp = rt_sf_addr - (SIGNAL_FRAMESIZE + 16);
 513     err |= put_user(env->gpr[1], newsp, target_ulong);
 514
 515     if (err)
 516         goto sigsegv;
 517
 518     /* Set up registers for signal handler.  */
 519     env->gpr[1] = newsp;
 520     env->gpr[3] = (target_ulong) sig;
 521     env->gpr[4] = (target_ulong) h2g(&rt_sf->info);
 522     env->gpr[5] = (target_ulong) h2g(&rt_sf->uc);
 523     env->gpr[6] = (target_ulong) h2g(rt_sf);
 524
 525 #if defined(TARGET_PPC64)
 526     if (get_ppc64_abi(image) < 2) {
 527         /* ELFv1 PPC64 function pointers are pointers to OPD entries. */
 528         struct target_func_ptr *handler =
 529             (struct target_func_ptr *)g2h(env_cpu(env), ka->_sa_handler);
 530         env->nip = tswapl(handler->entry);
 531         env->gpr[2] = tswapl(handler->toc);
 532     } else {
 533         /* ELFv2 PPC64 function pointers are entry points. R12 must also be set. */
 534         env->gpr[12] = env->nip = ka->_sa_handler;
 535     }
 536 #else
 537     env->nip = (target_ulong) ka->_sa_handler;
 538 #endif
 539
 540 #if TARGET_BIG_ENDIAN
 541     /* Signal handlers are entered in big-endian mode.  */
 542     ppc_store_msr(env, env->msr & ~(1ull << MSR_LE));
 543 #else
 544     /* Signal handlers are entered in little-endian mode.  */
 545     ppc_store_msr(env, env->msr | (1ull << MSR_LE));
 546 #endif
 547
 548     unlock_user_struct(rt_sf, rt_sf_addr, 1);
 549     return;
 550
 551 sigsegv:
 552     unlock_user_struct(rt_sf, rt_sf_addr, 1);
 553     force_sigsegv(sig);
 554
 555 }
 556
 557 #if !defined(TARGET_PPC64)
 558 long do_sigreturn(CPUPPCState *env)
 559 {
 560     struct target_sigcontext *sc = NULL;
 561     struct target_mcontext *sr = NULL;
 562     target_ulong sr_addr = 0, sc_addr;
 563     sigset_t blocked;
 564     target_sigset_t set;
 565
 566     sc_addr = env->gpr[1] + SIGNAL_FRAMESIZE;
 567     if (!lock_user_struct(VERIFY_READ, sc, sc_addr, 1))
 568         goto sigsegv;
 569
 570     __get_user(set.sig[0], &sc->oldmask);
 571     __get_user(set.sig[1], &sc->_unused[3]);
 572
 573     target_to_host_sigset_internal(&blocked, &set);
 574     set_sigmask(&blocked);
 575
 576     __get_user(sr_addr, &sc->regs);
 577     if (!lock_user_struct(VERIFY_READ, sr, sr_addr, 1))
 578         goto sigsegv;
 579     restore_user_regs(env, sr, 1);
 580
 581     unlock_user_struct(sr, sr_addr, 1);
 582     unlock_user_struct(sc, sc_addr, 1);
 583     return -QEMU_ESIGRETURN;
 584
 585 sigsegv:
 586     unlock_user_struct(sr, sr_addr, 1);
 587     unlock_user_struct(sc, sc_addr, 1);
 588     force_sig(TARGET_SIGSEGV);
 589     return -QEMU_ESIGRETURN;
 590 }
 591 #endif /* !defined(TARGET_PPC64) */
 592
 593 /* See arch/powerpc/kernel/signal_32.c.  */
 594 static int do_setcontext(struct target_ucontext *ucp, CPUPPCState *env, int sig)
 595 {
 596     struct target_mcontext *mcp;
 597     target_ulong mcp_addr;
 598     sigset_t blocked;
 599     target_sigset_t set;
 600
 601     if (copy_from_user(&set, h2g(ucp) + offsetof(struct target_ucontext, tuc_sigmask),
 602                        sizeof (set)))
 603         return 1;
 604
 605 #if defined(TARGET_PPC64)
 606     mcp_addr = h2g(ucp) +
 607         offsetof(struct target_ucontext, tuc_sigcontext.mcontext);
 608 #else
 609     __get_user(mcp_addr, &ucp->tuc_regs);
 610 #endif
 611
 612     if (!lock_user_struct(VERIFY_READ, mcp, mcp_addr, 1))
 613         return 1;
 614
 615     target_to_host_sigset_internal(&blocked, &set);
 616     set_sigmask(&blocked);
 617     restore_user_regs(env, mcp, sig);
 618
 619     unlock_user_struct(mcp, mcp_addr, 1);
 620     return 0;
 621 }
 622
 623 long do_rt_sigreturn(CPUPPCState *env)
 624 {
 625     struct target_rt_sigframe *rt_sf = NULL;
 626     target_ulong rt_sf_addr;
 627
 628     rt_sf_addr = env->gpr[1] + SIGNAL_FRAMESIZE + 16;
 629     if (!lock_user_struct(VERIFY_READ, rt_sf, rt_sf_addr, 1))
 630         goto sigsegv;
 631
 632     if (do_setcontext(&rt_sf->uc, env, 1))
 633         goto sigsegv;
 634
 635     target_restore_altstack(&rt_sf->uc.tuc_stack, env);
 636
 637     unlock_user_struct(rt_sf, rt_sf_addr, 1);
 638     return -QEMU_ESIGRETURN;
 639
 640 sigsegv:
 641     unlock_user_struct(rt_sf, rt_sf_addr, 1);
 642     force_sig(TARGET_SIGSEGV);
 643     return -QEMU_ESIGRETURN;
 644 }
 645
 646 /* This syscall implements {get,set,swap}context for userland.  */
 647 abi_long do_swapcontext(CPUArchState *env, abi_ulong uold_ctx,
 648                         abi_ulong unew_ctx, abi_long ctx_size)
 649 {
 650     struct target_ucontext *uctx;
 651     struct target_mcontext *mctx;
 652
 653     /* For ppc32, ctx_size is "reserved for future use".
 654      * For ppc64, we do not yet support the VSX extension.
 655      */
 656     if (ctx_size < sizeof(struct target_ucontext)) {
 657         return -TARGET_EINVAL;
 658     }
 659
 660     if (uold_ctx) {
 661         TaskState *ts = (TaskState *)thread_cpu->opaque;
 662
 663         if (!lock_user_struct(VERIFY_WRITE, uctx, uold_ctx, 1)) {
 664             return -TARGET_EFAULT;
 665         }
 666
 667 #ifdef TARGET_PPC64
 668         mctx = &uctx->tuc_sigcontext.mcontext;
 669 #else
 670         /* ??? The kernel aligns the pointer down here into padding, but
 671          * in setup_rt_frame we don't.  Be self-compatible for now.
 672          */
 673         mctx = &uctx->tuc_mcontext;
 674         __put_user(h2g(mctx), &uctx->tuc_regs);
 675 #endif
 676
 677         save_user_regs(env, mctx);
 678         host_to_target_sigset(&uctx->tuc_sigmask, &ts->signal_mask);
 679
 680         unlock_user_struct(uctx, uold_ctx, 1);
 681     }
 682
 683     if (unew_ctx) {
 684         int err;
 685
 686         if (!lock_user_struct(VERIFY_READ, uctx, unew_ctx, 1)) {
 687             return -TARGET_EFAULT;
 688         }
 689         err = do_setcontext(uctx, env, 0);
 690         unlock_user_struct(uctx, unew_ctx, 1);
 691
 692         if (err) {
 693             /* We cannot return to a partially updated context.  */
 694             force_sig(TARGET_SIGSEGV);
 695         }
 696         return -QEMU_ESIGRETURN;
 697     }
 698
 699     return 0;
 700 }
 701
 702 void setup_sigtramp(abi_ulong sigtramp_page)
 703 {
 704     uint32_t *tramp = lock_user(VERIFY_WRITE, sigtramp_page, 2 * 8, 0);
 705     assert(tramp != NULL);
 706
 707 #ifdef TARGET_ARCH_HAS_SETUP_FRAME
 708     default_sigreturn = sigtramp_page;
 709     encode_trampoline(TARGET_NR_sigreturn, tramp + 0);
 710 #endif
 711
 712     default_rt_sigreturn = sigtramp_page + 8;
 713     encode_trampoline(TARGET_NR_rt_sigreturn, tramp + 2);
 714
 715     unlock_user(tramp, sigtramp_page, 2 * 8);
 716 }