target/riscv/tcg/tcg-cpu.c

   1 /*
   2  * riscv TCG cpu class initialization
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2017-2018 SiFive, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2 or later, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "exec/exec-all.h"
  22 #include "tcg-cpu.h"
  23 #include "cpu.h"
  24 #include "pmu.h"
  25 #include "time_helper.h"
  26 #include "qapi/error.h"
  27 #include "qapi/visitor.h"
  28 #include "qemu/accel.h"
  29 #include "qemu/error-report.h"
  30 #include "qemu/log.h"
  31 #include "hw/core/accel-cpu.h"
  32 #include "hw/core/tcg-cpu-ops.h"
  33 #include "tcg/tcg.h"
  34
  35 /* Hash that stores user set extensions */
  36 static GHashTable *multi_ext_user_opts;
  37
  38 static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
  39 {
  40     return g_hash_table_contains(multi_ext_user_opts,
  41                                  GUINT_TO_POINTER(ext_offset));
  42 }
  43
  44 static void riscv_cpu_synchronize_from_tb(CPUState *cs,
  45                                           const TranslationBlock *tb)
  46 {
  47     if (!(tb_cflags(tb) & CF_PCREL)) {
  48         RISCVCPU *cpu = RISCV_CPU(cs);
  49         CPURISCVState *env = &cpu->env;
  50         RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
  51
  52         tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
  53
  54         if (xl == MXL_RV32) {
  55             env->pc = (int32_t) tb->pc;
  56         } else {
  57             env->pc = tb->pc;
  58         }
  59     }
  60 }
  61
  62 static void riscv_restore_state_to_opc(CPUState *cs,
  63                                        const TranslationBlock *tb,
  64                                        const uint64_t *data)
  65 {
  66     RISCVCPU *cpu = RISCV_CPU(cs);
  67     CPURISCVState *env = &cpu->env;
  68     RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
  69     target_ulong pc;
  70
  71     if (tb_cflags(tb) & CF_PCREL) {
  72         pc = (env->pc & TARGET_PAGE_MASK) | data[0];
  73     } else {
  74         pc = data[0];
  75     }
  76
  77     if (xl == MXL_RV32) {
  78         env->pc = (int32_t)pc;
  79     } else {
  80         env->pc = pc;
  81     }
  82     env->bins = data[1];
  83 }
  84
  85 static const struct TCGCPUOps riscv_tcg_ops = {
  86     .initialize = riscv_translate_init,
  87     .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
  88     .restore_state_to_opc = riscv_restore_state_to_opc,
  89
  90 #ifndef CONFIG_USER_ONLY
  91     .tlb_fill = riscv_cpu_tlb_fill,
  92     .cpu_exec_interrupt = riscv_cpu_exec_interrupt,
  93     .do_interrupt = riscv_cpu_do_interrupt,
  94     .do_transaction_failed = riscv_cpu_do_transaction_failed,
  95     .do_unaligned_access = riscv_cpu_do_unaligned_access,
  96     .debug_excp_handler = riscv_cpu_debug_excp_handler,
  97     .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint,
  98     .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint,
  99 #endif /* !CONFIG_USER_ONLY */
 100 };
 101
 102 static int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
 103 {
 104     const RISCVIsaExtData *edata;
 105
 106     for (edata = isa_edata_arr; edata && edata->name; edata++) {
 107         if (edata->ext_enable_offset != ext_offset) {
 108             continue;
 109         }
 110
 111         return edata->min_version;
 112     }
 113
 114     g_assert_not_reached();
 115 }
 116
 117 static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset,
 118                                     bool value)
 119 {
 120     CPURISCVState *env = &cpu->env;
 121     bool prev_val = isa_ext_is_enabled(cpu, ext_offset);
 122     int min_version;
 123
 124     if (prev_val == value) {
 125         return;
 126     }
 127
 128     if (cpu_cfg_ext_is_user_set(ext_offset)) {
 129         return;
 130     }
 131
 132     if (value && env->priv_ver != PRIV_VERSION_LATEST) {
 133         /* Do not enable it if priv_ver is older than min_version */
 134         min_version = cpu_cfg_ext_get_min_version(ext_offset);
 135         if (env->priv_ver < min_version) {
 136             return;
 137         }
 138     }
 139
 140     isa_ext_update_enabled(cpu, ext_offset, value);
 141 }
 142
 143 static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)
 144 {
 145     if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) {
 146         error_setg(errp, "H extension requires priv spec 1.12.0");
 147         return;
 148     }
 149 }
 150
 151 static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp)
 152 {
 153     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
 154     CPUClass *cc = CPU_CLASS(mcc);
 155     CPURISCVState *env = &cpu->env;
 156
 157     /* Validate that MISA_MXL is set properly. */
 158     switch (env->misa_mxl_max) {
 159 #ifdef TARGET_RISCV64
 160     case MXL_RV64:
 161     case MXL_RV128:
 162         cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
 163         break;
 164 #endif
 165     case MXL_RV32:
 166         cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
 167         break;
 168     default:
 169         g_assert_not_reached();
 170     }
 171
 172     if (env->misa_mxl_max != env->misa_mxl) {
 173         error_setg(errp, "misa_mxl_max must be equal to misa_mxl");
 174         return;
 175     }
 176 }
 177
 178 static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp)
 179 {
 180     CPURISCVState *env = &cpu->env;
 181     int priv_version = -1;
 182
 183     if (cpu->cfg.priv_spec) {
 184         if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) {
 185             priv_version = PRIV_VERSION_1_12_0;
 186         } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
 187             priv_version = PRIV_VERSION_1_11_0;
 188         } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
 189             priv_version = PRIV_VERSION_1_10_0;
 190         } else {
 191             error_setg(errp,
 192                        "Unsupported privilege spec version '%s'",
 193                        cpu->cfg.priv_spec);
 194             return;
 195         }
 196
 197         env->priv_ver = priv_version;
 198     }
 199 }
 200
 201 static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
 202                                  Error **errp)
 203 {
 204     if (!is_power_of_2(cfg->vlen)) {
 205         error_setg(errp, "Vector extension VLEN must be power of 2");
 206         return;
 207     }
 208
 209     if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) {
 210         error_setg(errp,
 211                    "Vector extension implementation only supports VLEN "
 212                    "in the range [128, %d]", RV_VLEN_MAX);
 213         return;
 214     }
 215
 216     if (!is_power_of_2(cfg->elen)) {
 217         error_setg(errp, "Vector extension ELEN must be power of 2");
 218         return;
 219     }
 220
 221     if (cfg->elen > 64 || cfg->elen < 8) {
 222         error_setg(errp,
 223                    "Vector extension implementation only supports ELEN "
 224                    "in the range [8, 64]");
 225         return;
 226     }
 227
 228     if (cfg->vext_spec) {
 229         if (!g_strcmp0(cfg->vext_spec, "v1.0")) {
 230             env->vext_ver = VEXT_VERSION_1_00_0;
 231         } else {
 232             error_setg(errp, "Unsupported vector spec version '%s'",
 233                        cfg->vext_spec);
 234             return;
 235         }
 236     } else if (env->vext_ver == 0) {
 237         qemu_log("vector version is not specified, "
 238                  "use the default value v1.0\n");
 239
 240         env->vext_ver = VEXT_VERSION_1_00_0;
 241     }
 242 }
 243
 244 static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
 245 {
 246     CPURISCVState *env = &cpu->env;
 247     const RISCVIsaExtData *edata;
 248
 249     /* Force disable extensions if priv spec version does not match */
 250     for (edata = isa_edata_arr; edata && edata->name; edata++) {
 251         if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) &&
 252             (env->priv_ver < edata->min_version)) {
 253             isa_ext_update_enabled(cpu, edata->ext_enable_offset, false);
 254 #ifndef CONFIG_USER_ONLY
 255             warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
 256                         " because privilege spec version does not match",
 257                         edata->name, env->mhartid);
 258 #else
 259             warn_report("disabling %s extension because "
 260                         "privilege spec version does not match",
 261                         edata->name);
 262 #endif
 263         }
 264     }
 265 }
 266
 267 /*
 268  * Check consistency between chosen extensions while setting
 269  * cpu->cfg accordingly.
 270  */
 271 void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
 272 {
 273     CPURISCVState *env = &cpu->env;
 274     Error *local_err = NULL;
 275
 276     /* Do some ISA extension error checking */
 277     if (riscv_has_ext(env, RVG) &&
 278         !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) &&
 279           riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) &&
 280           riscv_has_ext(env, RVD) &&
 281           cpu->cfg.ext_zicsr && cpu->cfg.ext_zifencei)) {
 282
 283         if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicsr)) &&
 284             !cpu->cfg.ext_zicsr) {
 285             error_setg(errp, "RVG requires Zicsr but user set Zicsr to false");
 286             return;
 287         }
 288
 289         if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zifencei)) &&
 290             !cpu->cfg.ext_zifencei) {
 291             error_setg(errp, "RVG requires Zifencei but user set "
 292                        "Zifencei to false");
 293             return;
 294         }
 295
 296         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zicsr), true);
 297         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zifencei), true);
 298
 299         env->misa_ext |= RVI | RVM | RVA | RVF | RVD;
 300         env->misa_ext_mask |= RVI | RVM | RVA | RVF | RVD;
 301     }
 302
 303     if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) {
 304         error_setg(errp,
 305                    "I and E extensions are incompatible");
 306         return;
 307     }
 308
 309     if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) {
 310         error_setg(errp,
 311                    "Either I or E extension must be set");
 312         return;
 313     }
 314
 315     if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) {
 316         error_setg(errp,
 317                    "Setting S extension without U extension is illegal");
 318         return;
 319     }
 320
 321     if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) {
 322         error_setg(errp,
 323                    "H depends on an I base integer ISA with 32 x registers");
 324         return;
 325     }
 326
 327     if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) {
 328         error_setg(errp, "H extension implicitly requires S-mode");
 329         return;
 330     }
 331
 332     if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_zicsr) {
 333         error_setg(errp, "F extension requires Zicsr");
 334         return;
 335     }
 336
 337     if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) {
 338         error_setg(errp, "Zawrs extension requires A extension");
 339         return;
 340     }
 341
 342     if (cpu->cfg.ext_zfa && !riscv_has_ext(env, RVF)) {
 343         error_setg(errp, "Zfa extension requires F extension");
 344         return;
 345     }
 346
 347     if (cpu->cfg.ext_zfh) {
 348         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zfhmin), true);
 349     }
 350
 351     if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) {
 352         error_setg(errp, "Zfh/Zfhmin extensions require F extension");
 353         return;
 354     }
 355
 356     if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) {
 357         error_setg(errp, "Zfbfmin extension depends on F extension");
 358         return;
 359     }
 360
 361     if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) {
 362         error_setg(errp, "D extension requires F extension");
 363         return;
 364     }
 365
 366     if (riscv_has_ext(env, RVV)) {
 367         riscv_cpu_validate_v(env, &cpu->cfg, &local_err);
 368         if (local_err != NULL) {
 369             error_propagate(errp, local_err);
 370             return;
 371         }
 372
 373         /* The V vector extension depends on the Zve64d extension */
 374         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64d), true);
 375     }
 376
 377     /* The Zve64d extension depends on the Zve64f extension */
 378     if (cpu->cfg.ext_zve64d) {
 379         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true);
 380     }
 381
 382     /* The Zve64f extension depends on the Zve32f extension */
 383     if (cpu->cfg.ext_zve64f) {
 384         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true);
 385     }
 386
 387     if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) {
 388         error_setg(errp, "Zve64d/V extensions require D extension");
 389         return;
 390     }
 391
 392     if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
 393         error_setg(errp, "Zve32f/Zve64f extensions require F extension");
 394         return;
 395     }
 396
 397     if (cpu->cfg.ext_zvfh) {
 398         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvfhmin), true);
 399     }
 400
 401     if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) {
 402         error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension");
 403         return;
 404     }
 405
 406     if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) {
 407         error_setg(errp, "Zvfh extensions requires Zfhmin extension");
 408         return;
 409     }
 410
 411     if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zfbfmin) {
 412         error_setg(errp, "Zvfbfmin extension depends on Zfbfmin extension");
 413         return;
 414     }
 415
 416     if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) {
 417         error_setg(errp, "Zvfbfmin extension depends on Zve32f extension");
 418         return;
 419     }
 420
 421     if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) {
 422         error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin extension");
 423         return;
 424     }
 425
 426     /* Set the ISA extensions, checks should have happened above */
 427     if (cpu->cfg.ext_zhinx) {
 428         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
 429     }
 430
 431     if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
 432         error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
 433         return;
 434     }
 435
 436     if (cpu->cfg.ext_zfinx) {
 437         if (!cpu->cfg.ext_zicsr) {
 438             error_setg(errp, "Zfinx extension requires Zicsr");
 439             return;
 440         }
 441         if (riscv_has_ext(env, RVF)) {
 442             error_setg(errp,
 443                        "Zfinx cannot be supported together with F extension");
 444             return;
 445         }
 446     }
 447
 448     if (cpu->cfg.ext_zce) {
 449         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
 450         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true);
 451         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true);
 452         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true);
 453         if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
 454             cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
 455         }
 456     }
 457
 458     /* zca, zcd and zcf has a PRIV 1.12.0 restriction */
 459     if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) {
 460         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
 461         if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
 462             cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
 463         }
 464         if (riscv_has_ext(env, RVD)) {
 465             cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true);
 466         }
 467     }
 468
 469     if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) {
 470         error_setg(errp, "Zcf extension is only relevant to RV32");
 471         return;
 472     }
 473
 474     if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) {
 475         error_setg(errp, "Zcf extension requires F extension");
 476         return;
 477     }
 478
 479     if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) {
 480         error_setg(errp, "Zcd extension requires D extension");
 481         return;
 482     }
 483
 484     if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb ||
 485          cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) {
 486         error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca "
 487                          "extension");
 488         return;
 489     }
 490
 491     if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) {
 492         error_setg(errp, "Zcmp/Zcmt extensions are incompatible with "
 493                          "Zcd extension");
 494         return;
 495     }
 496
 497     if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_zicsr) {
 498         error_setg(errp, "Zcmt extension requires Zicsr extension");
 499         return;
 500     }
 501
 502     /*
 503      * In principle Zve*x would also suffice here, were they supported
 504      * in qemu
 505      */
 506     if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkg || cpu->cfg.ext_zvkned ||
 507          cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || cpu->cfg.ext_zvksh) &&
 508         !cpu->cfg.ext_zve32f) {
 509         error_setg(errp,
 510                    "Vector crypto extensions require V or Zve* extensions");
 511         return;
 512     }
 513
 514     if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f) {
 515         error_setg(
 516             errp,
 517             "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions");
 518         return;
 519     }
 520
 521     if (cpu->cfg.ext_zk) {
 522         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkn), true);
 523         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkr), true);
 524         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkt), true);
 525     }
 526
 527     if (cpu->cfg.ext_zkn) {
 528         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true);
 529         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true);
 530         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true);
 531         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkne), true);
 532         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknd), true);
 533         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknh), true);
 534     }
 535
 536     if (cpu->cfg.ext_zks) {
 537         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true);
 538         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true);
 539         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true);
 540         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksed), true);
 541         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksh), true);
 542     }
 543
 544     if (cpu->cfg.ext_zicntr && !cpu->cfg.ext_zicsr) {
 545         if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicntr))) {
 546             error_setg(errp, "zicntr requires zicsr");
 547             return;
 548         }
 549         cpu->cfg.ext_zicntr = false;
 550     }
 551
 552     if (cpu->cfg.ext_zihpm && !cpu->cfg.ext_zicsr) {
 553         if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zihpm))) {
 554             error_setg(errp, "zihpm requires zicsr");
 555             return;
 556         }
 557         cpu->cfg.ext_zihpm = false;
 558     }
 559
 560     if (!cpu->cfg.ext_zihpm) {
 561         cpu->cfg.pmu_num = 0;
 562         cpu->pmu_avail_ctrs = 0;
 563     }
 564
 565     /*
 566      * Disable isa extensions based on priv spec after we
 567      * validated and set everything we need.
 568      */
 569     riscv_cpu_disable_priv_spec_isa_exts(cpu);
 570 }
 571
 572 void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
 573 {
 574     CPURISCVState *env = &cpu->env;
 575     Error *local_err = NULL;
 576
 577     riscv_cpu_validate_priv_spec(cpu, &local_err);
 578     if (local_err != NULL) {
 579         error_propagate(errp, local_err);
 580         return;
 581     }
 582
 583     riscv_cpu_validate_misa_priv(env, &local_err);
 584     if (local_err != NULL) {
 585         error_propagate(errp, local_err);
 586         return;
 587     }
 588
 589     if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) {
 590         /*
 591          * Enhanced PMP should only be available
 592          * on harts with PMP support
 593          */
 594         error_setg(errp, "Invalid configuration: Smepmp requires PMP support");
 595         return;
 596     }
 597
 598     riscv_cpu_validate_set_extensions(cpu, &local_err);
 599     if (local_err != NULL) {
 600         error_propagate(errp, local_err);
 601         return;
 602     }
 603 }
 604
 605 bool riscv_cpu_tcg_compatible(RISCVCPU *cpu)
 606 {
 607     return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL;
 608 }
 609
 610 static bool riscv_cpu_is_generic(Object *cpu_obj)
 611 {
 612     return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
 613 }
 614
 615 /*
 616  * We'll get here via the following path:
 617  *
 618  * riscv_cpu_realize()
 619  *   -> cpu_exec_realizefn()
 620  *      -> tcg_cpu_realize() (via accel_cpu_common_realize())
 621  */
 622 static bool tcg_cpu_realize(CPUState *cs, Error **errp)
 623 {
 624     RISCVCPU *cpu = RISCV_CPU(cs);
 625     Error *local_err = NULL;
 626
 627     if (!riscv_cpu_tcg_compatible(cpu)) {
 628         g_autofree char *name = riscv_cpu_get_name(cpu);
 629         error_setg(errp, "'%s' CPU is not compatible with TCG acceleration",
 630                    name);
 631         return false;
 632     }
 633
 634     riscv_cpu_validate_misa_mxl(cpu, &local_err);
 635     if (local_err != NULL) {
 636         error_propagate(errp, local_err);
 637         return false;
 638     }
 639
 640 #ifndef CONFIG_USER_ONLY
 641     CPURISCVState *env = &cpu->env;
 642
 643     CPU(cs)->tcg_cflags |= CF_PCREL;
 644
 645     if (cpu->cfg.ext_sstc) {
 646         riscv_timer_init(cpu);
 647     }
 648
 649     if (cpu->cfg.pmu_num) {
 650         if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) {
 651             cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
 652                                           riscv_pmu_timer_cb, cpu);
 653         }
 654     }
 655
 656     /* With H-Ext, VSSIP, VSTIP, VSEIP and SGEIP are hardwired to one. */
 657     if (riscv_has_ext(env, RVH)) {
 658         env->mideleg = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP | MIP_SGEIP;
 659     }
 660 #endif
 661
 662     return true;
 663 }
 664
 665 typedef struct RISCVCPUMisaExtConfig {
 666     target_ulong misa_bit;
 667     bool enabled;
 668 } RISCVCPUMisaExtConfig;
 669
 670 static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
 671                                  void *opaque, Error **errp)
 672 {
 673     const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
 674     target_ulong misa_bit = misa_ext_cfg->misa_bit;
 675     RISCVCPU *cpu = RISCV_CPU(obj);
 676     CPURISCVState *env = &cpu->env;
 677     bool generic_cpu = riscv_cpu_is_generic(obj);
 678     bool prev_val, value;
 679
 680     if (!visit_type_bool(v, name, &value, errp)) {
 681         return;
 682     }
 683
 684     prev_val = env->misa_ext & misa_bit;
 685
 686     if (value == prev_val) {
 687         return;
 688     }
 689
 690     if (value) {
 691         if (!generic_cpu) {
 692             g_autofree char *cpuname = riscv_cpu_get_name(cpu);
 693             error_setg(errp, "'%s' CPU does not allow enabling extensions",
 694                        cpuname);
 695             return;
 696         }
 697
 698         env->misa_ext |= misa_bit;
 699         env->misa_ext_mask |= misa_bit;
 700     } else {
 701         env->misa_ext &= ~misa_bit;
 702         env->misa_ext_mask &= ~misa_bit;
 703     }
 704 }
 705
 706 static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
 707                                  void *opaque, Error **errp)
 708 {
 709     const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
 710     target_ulong misa_bit = misa_ext_cfg->misa_bit;
 711     RISCVCPU *cpu = RISCV_CPU(obj);
 712     CPURISCVState *env = &cpu->env;
 713     bool value;
 714
 715     value = env->misa_ext & misa_bit;
 716
 717     visit_type_bool(v, name, &value, errp);
 718 }
 719
 720 #define MISA_CFG(_bit, _enabled) \
 721     {.misa_bit = _bit, .enabled = _enabled}
 722
 723 static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
 724     MISA_CFG(RVA, true),
 725     MISA_CFG(RVC, true),
 726     MISA_CFG(RVD, true),
 727     MISA_CFG(RVF, true),
 728     MISA_CFG(RVI, true),
 729     MISA_CFG(RVE, false),
 730     MISA_CFG(RVM, true),
 731     MISA_CFG(RVS, true),
 732     MISA_CFG(RVU, true),
 733     MISA_CFG(RVH, true),
 734     MISA_CFG(RVJ, false),
 735     MISA_CFG(RVV, false),
 736     MISA_CFG(RVG, false),
 737 };
 738
 739 /*
 740  * We do not support user choice tracking for MISA
 741  * extensions yet because, so far, we do not silently
 742  * change MISA bits during realize() (RVG enables MISA
 743  * bits but the user is warned about it).
 744  */
 745 static void riscv_cpu_add_misa_properties(Object *cpu_obj)
 746 {
 747     bool use_def_vals = riscv_cpu_is_generic(cpu_obj);
 748     int i;
 749
 750     for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) {
 751         const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i];
 752         int bit = misa_cfg->misa_bit;
 753         const char *name = riscv_get_misa_ext_name(bit);
 754         const char *desc = riscv_get_misa_ext_description(bit);
 755
 756         /* Check if KVM already created the property */
 757         if (object_property_find(cpu_obj, name)) {
 758             continue;
 759         }
 760
 761         object_property_add(cpu_obj, name, "bool",
 762                             cpu_get_misa_ext_cfg,
 763                             cpu_set_misa_ext_cfg,
 764                             NULL, (void *)misa_cfg);
 765         object_property_set_description(cpu_obj, name, desc);
 766         if (use_def_vals) {
 767             object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL);
 768         }
 769     }
 770 }
 771
 772 static bool cpu_ext_is_deprecated(const char *ext_name)
 773 {
 774     return isupper(ext_name[0]);
 775 }
 776
 777 /*
 778  * String will be allocated in the heap. Caller is responsible
 779  * for freeing it.
 780  */
 781 static char *cpu_ext_to_lower(const char *ext_name)
 782 {
 783     char *ret = g_malloc0(strlen(ext_name) + 1);
 784
 785     strcpy(ret, ext_name);
 786     ret[0] = tolower(ret[0]);
 787
 788     return ret;
 789 }
 790
 791 static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
 792                                   void *opaque, Error **errp)
 793 {
 794     const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
 795     RISCVCPU *cpu = RISCV_CPU(obj);
 796     bool generic_cpu = riscv_cpu_is_generic(obj);
 797     bool prev_val, value;
 798
 799     if (!visit_type_bool(v, name, &value, errp)) {
 800         return;
 801     }
 802
 803     if (cpu_ext_is_deprecated(multi_ext_cfg->name)) {
 804         g_autofree char *lower = cpu_ext_to_lower(multi_ext_cfg->name);
 805
 806         warn_report("CPU property '%s' is deprecated. Please use '%s' instead",
 807                     multi_ext_cfg->name, lower);
 808     }
 809
 810     g_hash_table_insert(multi_ext_user_opts,
 811                         GUINT_TO_POINTER(multi_ext_cfg->offset),
 812                         (gpointer)value);
 813
 814     prev_val = isa_ext_is_enabled(cpu, multi_ext_cfg->offset);
 815
 816     if (value == prev_val) {
 817         return;
 818     }
 819
 820     if (value && !generic_cpu) {
 821         g_autofree char *cpuname = riscv_cpu_get_name(cpu);
 822         error_setg(errp, "'%s' CPU does not allow enabling extensions",
 823                    cpuname);
 824         return;
 825     }
 826
 827     isa_ext_update_enabled(cpu, multi_ext_cfg->offset, value);
 828 }
 829
 830 static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
 831                                   void *opaque, Error **errp)
 832 {
 833     const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
 834     bool value = isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offset);
 835
 836     visit_type_bool(v, name, &value, errp);
 837 }
 838
 839 static void cpu_add_multi_ext_prop(Object *cpu_obj,
 840                                    const RISCVCPUMultiExtConfig *multi_cfg)
 841 {
 842     bool generic_cpu = riscv_cpu_is_generic(cpu_obj);
 843     bool deprecated_ext = cpu_ext_is_deprecated(multi_cfg->name);
 844
 845     object_property_add(cpu_obj, multi_cfg->name, "bool",
 846                         cpu_get_multi_ext_cfg,
 847                         cpu_set_multi_ext_cfg,
 848                         NULL, (void *)multi_cfg);
 849
 850     if (!generic_cpu || deprecated_ext) {
 851         return;
 852     }
 853
 854     /*
 855      * Set def val directly instead of using
 856      * object_property_set_bool() to save the set()
 857      * callback hash for user inputs.
 858      */
 859     isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset,
 860                            multi_cfg->enabled);
 861 }
 862
 863 static void riscv_cpu_add_multiext_prop_array(Object *obj,
 864                                         const RISCVCPUMultiExtConfig *array)
 865 {
 866     const RISCVCPUMultiExtConfig *prop;
 867
 868     g_assert(array);
 869
 870     for (prop = array; prop && prop->name; prop++) {
 871         cpu_add_multi_ext_prop(obj, prop);
 872     }
 873 }
 874
 875 /*
 876  * Add CPU properties with user-facing flags.
 877  *
 878  * This will overwrite existing env->misa_ext values with the
 879  * defaults set via riscv_cpu_add_misa_properties().
 880  */
 881 static void riscv_cpu_add_user_properties(Object *obj)
 882 {
 883 #ifndef CONFIG_USER_ONLY
 884     riscv_add_satp_mode_properties(obj);
 885 #endif
 886
 887     riscv_cpu_add_misa_properties(obj);
 888
 889     riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_extensions);
 890     riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts);
 891     riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts);
 892
 893     riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_deprecated_exts);
 894
 895     for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
 896         qdev_property_add_static(DEVICE(obj), prop);
 897     }
 898 }
 899
 900 /*
 901  * The 'max' type CPU will have all possible ratified
 902  * non-vendor extensions enabled.
 903  */
 904 static void riscv_init_max_cpu_extensions(Object *obj)
 905 {
 906     RISCVCPU *cpu = RISCV_CPU(obj);
 907     CPURISCVState *env = &cpu->env;
 908     const RISCVCPUMultiExtConfig *prop;
 909
 910     /* Enable RVG, RVJ and RVV that are disabled by default */
 911     riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
 912
 913     for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
 914         isa_ext_update_enabled(cpu, prop->offset, true);
 915     }
 916
 917     /* set vector version */
 918     env->vext_ver = VEXT_VERSION_1_00_0;
 919
 920     /* Zfinx is not compatible with F. Disable it */
 921     isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false);
 922     isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false);
 923     isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false);
 924     isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false);
 925
 926     isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false);
 927     isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false);
 928     isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false);
 929
 930     if (env->misa_mxl != MXL_RV32) {
 931         isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false);
 932     }
 933 }
 934
 935 static bool riscv_cpu_has_max_extensions(Object *cpu_obj)
 936 {
 937     return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL;
 938 }
 939
 940 static void tcg_cpu_instance_init(CPUState *cs)
 941 {
 942     RISCVCPU *cpu = RISCV_CPU(cs);
 943     Object *obj = OBJECT(cpu);
 944
 945     multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
 946     riscv_cpu_add_user_properties(obj);
 947
 948     if (riscv_cpu_has_max_extensions(obj)) {
 949         riscv_init_max_cpu_extensions(obj);
 950     }
 951 }
 952
 953 static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc)
 954 {
 955     /*
 956      * All cpus use the same set of operations.
 957      */
 958     cc->tcg_ops = &riscv_tcg_ops;
 959 }
 960
 961 static void tcg_cpu_class_init(CPUClass *cc)
 962 {
 963     cc->init_accel_cpu = tcg_cpu_init_ops;
 964 }
 965
 966 static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data)
 967 {
 968     AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
 969
 970     acc->cpu_class_init = tcg_cpu_class_init;
 971     acc->cpu_instance_init = tcg_cpu_instance_init;
 972     acc->cpu_target_realize = tcg_cpu_realize;
 973 }
 974
 975 static const TypeInfo tcg_cpu_accel_type_info = {
 976     .name = ACCEL_CPU_NAME("tcg"),
 977
 978     .parent = TYPE_ACCEL_CPU,
 979     .class_init = tcg_cpu_accel_class_init,
 980     .abstract = true,
 981 };
 982
 983 static void tcg_cpu_accel_register_types(void)
 984 {
 985     type_register_static(&tcg_cpu_accel_type_info);
 986 }
 987 type_init(tcg_cpu_accel_register_types);