2 * ARM Generic/Distributed Interrupt Controller
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
10 /* This file contains implementation code for the RealView EB interrupt
11 * controller, MPCore distributed interrupt controller and ARMv7-M
12 * Nested Vectored Interrupt Controller.
13 * It is compiled in two ways:
14 * (1) as a standalone file to produce a sysbus device which is a GIC
15 * that can be used on the realview board and as one of the builtin
16 * private peripherals for the ARM MP CPUs (11MPCore, A9, etc)
17 * (2) by being directly #included into armv7m_nvic.c to produce the
21 #include "qemu/osdep.h"
22 #include "hw/sysbus.h"
23 #include "gic_internal.h"
24 #include "qapi/error.h"
28 #include "sysemu/kvm.h"
30 /* #define DEBUG_GIC */
33 #define DEBUG_GIC_GATE 1
35 #define DEBUG_GIC_GATE 0
38 #define DPRINTF(fmt, ...) do { \
39 if (DEBUG_GIC_GATE) { \
40 fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); \
44 static const uint8_t gic_id_11mpcore
[] = {
45 0x00, 0x00, 0x00, 0x00, 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1
48 static const uint8_t gic_id_gicv1
[] = {
49 0x04, 0x00, 0x00, 0x00, 0x90, 0xb3, 0x1b, 0x00, 0x0d, 0xf0, 0x05, 0xb1
52 static const uint8_t gic_id_gicv2
[] = {
53 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0xb1
56 static inline int gic_get_current_cpu(GICState
*s
)
59 return current_cpu
->cpu_index
;
64 static inline int gic_get_current_vcpu(GICState
*s
)
66 return gic_get_current_cpu(s
) + GIC_NCPU
;
69 /* Return true if this GIC config has interrupt groups, which is
70 * true if we're a GICv2, or a GICv1 with the security extensions.
72 static inline bool gic_has_groups(GICState
*s
)
74 return s
->revision
== 2 || s
->security_extn
;
77 static inline bool gic_cpu_ns_access(GICState
*s
, int cpu
, MemTxAttrs attrs
)
79 return !gic_is_vcpu(cpu
) && s
->security_extn
&& !attrs
.secure
;
82 /* TODO: Many places that call this routine could be optimized. */
83 /* Update interrupt status after enabled or pending bits have been changed. */
84 static void gic_update(GICState
*s
)
89 int irq_level
, fiq_level
;
93 for (cpu
= 0; cpu
< s
->num_cpu
; cpu
++) {
95 s
->current_pending
[cpu
] = 1023;
96 if (!(s
->ctlr
& (GICD_CTLR_EN_GRP0
| GICD_CTLR_EN_GRP1
))
97 || !(s
->cpu_ctlr
[cpu
] & (GICC_CTLR_EN_GRP0
| GICC_CTLR_EN_GRP1
))) {
98 qemu_irq_lower(s
->parent_irq
[cpu
]);
99 qemu_irq_lower(s
->parent_fiq
[cpu
]);
104 for (irq
= 0; irq
< s
->num_irq
; irq
++) {
105 if (GIC_DIST_TEST_ENABLED(irq
, cm
) &&
106 gic_test_pending(s
, irq
, cm
) &&
107 (!GIC_DIST_TEST_ACTIVE(irq
, cm
)) &&
108 (irq
< GIC_INTERNAL
|| GIC_DIST_TARGET(irq
) & cm
)) {
109 if (GIC_DIST_GET_PRIORITY(irq
, cpu
) < best_prio
) {
110 best_prio
= GIC_DIST_GET_PRIORITY(irq
, cpu
);
116 if (best_irq
!= 1023) {
117 trace_gic_update_bestirq(cpu
, best_irq
, best_prio
,
118 s
->priority_mask
[cpu
], s
->running_priority
[cpu
]);
121 irq_level
= fiq_level
= 0;
123 if (best_prio
< s
->priority_mask
[cpu
]) {
124 s
->current_pending
[cpu
] = best_irq
;
125 if (best_prio
< s
->running_priority
[cpu
]) {
126 int group
= GIC_DIST_TEST_GROUP(best_irq
, cm
);
128 if (extract32(s
->ctlr
, group
, 1) &&
129 extract32(s
->cpu_ctlr
[cpu
], group
, 1)) {
130 if (group
== 0 && s
->cpu_ctlr
[cpu
] & GICC_CTLR_FIQ_EN
) {
131 DPRINTF("Raised pending FIQ %d (cpu %d)\n",
134 trace_gic_update_set_irq(cpu
, "fiq", fiq_level
);
136 DPRINTF("Raised pending IRQ %d (cpu %d)\n",
139 trace_gic_update_set_irq(cpu
, "irq", irq_level
);
145 qemu_set_irq(s
->parent_irq
[cpu
], irq_level
);
146 qemu_set_irq(s
->parent_fiq
[cpu
], fiq_level
);
150 static void gic_set_irq_11mpcore(GICState
*s
, int irq
, int level
,
154 GIC_DIST_SET_LEVEL(irq
, cm
);
155 if (GIC_DIST_TEST_EDGE_TRIGGER(irq
) || GIC_DIST_TEST_ENABLED(irq
, cm
)) {
156 DPRINTF("Set %d pending mask %x\n", irq
, target
);
157 GIC_DIST_SET_PENDING(irq
, target
);
160 GIC_DIST_CLEAR_LEVEL(irq
, cm
);
164 static void gic_set_irq_generic(GICState
*s
, int irq
, int level
,
168 GIC_DIST_SET_LEVEL(irq
, cm
);
169 DPRINTF("Set %d pending mask %x\n", irq
, target
);
170 if (GIC_DIST_TEST_EDGE_TRIGGER(irq
)) {
171 GIC_DIST_SET_PENDING(irq
, target
);
174 GIC_DIST_CLEAR_LEVEL(irq
, cm
);
178 /* Process a change in an external IRQ input. */
179 static void gic_set_irq(void *opaque
, int irq
, int level
)
181 /* Meaning of the 'irq' parameter:
182 * [0..N-1] : external interrupts
183 * [N..N+31] : PPI (internal) interrupts for CPU 0
184 * [N+32..N+63] : PPI (internal interrupts for CPU 1
187 GICState
*s
= (GICState
*)opaque
;
189 if (irq
< (s
->num_irq
- GIC_INTERNAL
)) {
190 /* The first external input line is internal interrupt 32. */
193 target
= GIC_DIST_TARGET(irq
);
196 irq
-= (s
->num_irq
- GIC_INTERNAL
);
197 cpu
= irq
/ GIC_INTERNAL
;
203 assert(irq
>= GIC_NR_SGIS
);
205 if (level
== GIC_DIST_TEST_LEVEL(irq
, cm
)) {
209 if (s
->revision
== REV_11MPCORE
) {
210 gic_set_irq_11mpcore(s
, irq
, level
, cm
, target
);
212 gic_set_irq_generic(s
, irq
, level
, cm
, target
);
214 trace_gic_set_irq(irq
, level
, cm
, target
);
219 static uint16_t gic_get_current_pending_irq(GICState
*s
, int cpu
,
222 uint16_t pending_irq
= s
->current_pending
[cpu
];
224 if (pending_irq
< GIC_MAXIRQ
&& gic_has_groups(s
)) {
225 int group
= gic_test_group(s
, pending_irq
, cpu
);
227 /* On a GIC without the security extensions, reading this register
228 * behaves in the same way as a secure access to a GIC with them.
230 bool secure
= !gic_cpu_ns_access(s
, cpu
, attrs
);
232 if (group
== 0 && !secure
) {
233 /* Group0 interrupts hidden from Non-secure access */
236 if (group
== 1 && secure
&& !(s
->cpu_ctlr
[cpu
] & GICC_CTLR_ACK_CTL
)) {
237 /* Group1 interrupts only seen by Secure access if
246 static int gic_get_group_priority(GICState
*s
, int cpu
, int irq
)
248 /* Return the group priority of the specified interrupt
249 * (which is the top bits of its priority, with the number
250 * of bits masked determined by the applicable binary point register).
255 if (gic_has_groups(s
) &&
256 !(s
->cpu_ctlr
[cpu
] & GICC_CTLR_CBPR
) &&
257 gic_test_group(s
, irq
, cpu
)) {
258 bpr
= s
->abpr
[cpu
] - 1;
264 /* a BPR of 0 means the group priority bits are [7:1];
265 * a BPR of 1 means they are [7:2], and so on down to
266 * a BPR of 7 meaning no group priority bits at all.
268 mask
= ~0U << ((bpr
& 7) + 1);
270 return gic_get_priority(s
, irq
, cpu
) & mask
;
273 static void gic_activate_irq(GICState
*s
, int cpu
, int irq
)
275 /* Set the appropriate Active Priority Register bit for this IRQ,
276 * and update the running priority.
278 int prio
= gic_get_group_priority(s
, cpu
, irq
);
279 int min_bpr
= gic_is_vcpu(cpu
) ? GIC_VIRT_MIN_BPR
: GIC_MIN_BPR
;
280 int preemption_level
= prio
>> (min_bpr
+ 1);
281 int regno
= preemption_level
/ 32;
282 int bitno
= preemption_level
% 32;
283 uint32_t *papr
= NULL
;
285 if (gic_is_vcpu(cpu
)) {
287 papr
= &s
->h_apr
[gic_get_vcpu_real_id(cpu
)];
288 } else if (gic_has_groups(s
) && gic_test_group(s
, irq
, cpu
)) {
289 papr
= &s
->nsapr
[regno
][cpu
];
291 papr
= &s
->apr
[regno
][cpu
];
294 *papr
|= (1 << bitno
);
296 s
->running_priority
[cpu
] = prio
;
297 gic_set_active(s
, irq
, cpu
);
300 static int gic_get_prio_from_apr_bits(GICState
*s
, int cpu
)
302 /* Recalculate the current running priority for this CPU based
303 * on the set bits in the Active Priority Registers.
307 if (gic_is_vcpu(cpu
)) {
308 uint32_t apr
= s
->h_apr
[gic_get_vcpu_real_id(cpu
)];
310 return ctz32(apr
) << (GIC_VIRT_MIN_BPR
+ 1);
316 for (i
= 0; i
< GIC_NR_APRS
; i
++) {
317 uint32_t apr
= s
->apr
[i
][cpu
] | s
->nsapr
[i
][cpu
];
321 return (i
* 32 + ctz32(apr
)) << (GIC_MIN_BPR
+ 1);
326 static void gic_drop_prio(GICState
*s
, int cpu
, int group
)
328 /* Drop the priority of the currently active interrupt in the
331 * Note that we can guarantee (because of the requirement to nest
332 * GICC_IAR reads [which activate an interrupt and raise priority]
333 * with GICC_EOIR writes [which drop the priority for the interrupt])
334 * that the interrupt we're being called for is the highest priority
335 * active interrupt, meaning that it has the lowest set bit in the
338 * If the guest does not honour the ordering constraints then the
339 * behaviour of the GIC is UNPREDICTABLE, which for us means that
340 * the values of the APR registers might become incorrect and the
341 * running priority will be wrong, so interrupts that should preempt
342 * might not do so, and interrupts that should not preempt might do so.
344 if (gic_is_vcpu(cpu
)) {
345 int rcpu
= gic_get_vcpu_real_id(cpu
);
347 if (s
->h_apr
[rcpu
]) {
348 /* Clear lowest set bit */
349 s
->h_apr
[rcpu
] &= s
->h_apr
[rcpu
] - 1;
354 for (i
= 0; i
< GIC_NR_APRS
; i
++) {
355 uint32_t *papr
= group
? &s
->nsapr
[i
][cpu
] : &s
->apr
[i
][cpu
];
359 /* Clear lowest set bit */
365 s
->running_priority
[cpu
] = gic_get_prio_from_apr_bits(s
, cpu
);
368 static inline uint32_t gic_clear_pending_sgi(GICState
*s
, int irq
, int cpu
)
373 if (!gic_is_vcpu(cpu
)) {
374 /* Lookup the source CPU for the SGI and clear this in the
375 * sgi_pending map. Return the src and clear the overall pending
376 * state on this CPU if the SGI is not pending from any CPUs.
378 assert(s
->sgi_pending
[irq
][cpu
] != 0);
379 src
= ctz32(s
->sgi_pending
[irq
][cpu
]);
380 s
->sgi_pending
[irq
][cpu
] &= ~(1 << src
);
381 if (s
->sgi_pending
[irq
][cpu
] == 0) {
382 gic_clear_pending(s
, irq
, cpu
);
384 ret
= irq
| ((src
& 0x7) << 10);
386 uint32_t *lr_entry
= gic_get_lr_entry(s
, irq
, cpu
);
387 src
= GICH_LR_CPUID(*lr_entry
);
389 gic_clear_pending(s
, irq
, cpu
);
390 ret
= irq
| (src
<< 10);
396 uint32_t gic_acknowledge_irq(GICState
*s
, int cpu
, MemTxAttrs attrs
)
400 /* gic_get_current_pending_irq() will return 1022 or 1023 appropriately
401 * for the case where this GIC supports grouping and the pending interrupt
402 * is in the wrong group.
404 irq
= gic_get_current_pending_irq(s
, cpu
, attrs
);
405 trace_gic_acknowledge_irq(gic_get_vcpu_real_id(cpu
), irq
);
407 if (irq
>= GIC_MAXIRQ
) {
408 DPRINTF("ACK, no pending interrupt or it is hidden: %d\n", irq
);
412 if (gic_get_priority(s
, irq
, cpu
) >= s
->running_priority
[cpu
]) {
413 DPRINTF("ACK, pending interrupt (%d) has insufficient priority\n", irq
);
417 gic_activate_irq(s
, cpu
, irq
);
419 if (s
->revision
== REV_11MPCORE
) {
420 /* Clear pending flags for both level and edge triggered interrupts.
421 * Level triggered IRQs will be reasserted once they become inactive.
423 gic_clear_pending(s
, irq
, cpu
);
426 if (irq
< GIC_NR_SGIS
) {
427 ret
= gic_clear_pending_sgi(s
, irq
, cpu
);
429 gic_clear_pending(s
, irq
, cpu
);
435 DPRINTF("ACK %d\n", irq
);
439 void gic_dist_set_priority(GICState
*s
, int cpu
, int irq
, uint8_t val
,
442 if (s
->security_extn
&& !attrs
.secure
) {
443 if (!GIC_DIST_TEST_GROUP(irq
, (1 << cpu
))) {
444 return; /* Ignore Non-secure access of Group0 IRQ */
446 val
= 0x80 | (val
>> 1); /* Non-secure view */
449 if (irq
< GIC_INTERNAL
) {
450 s
->priority1
[irq
][cpu
] = val
;
452 s
->priority2
[(irq
) - GIC_INTERNAL
] = val
;
456 static uint32_t gic_dist_get_priority(GICState
*s
, int cpu
, int irq
,
459 uint32_t prio
= GIC_DIST_GET_PRIORITY(irq
, cpu
);
461 if (s
->security_extn
&& !attrs
.secure
) {
462 if (!GIC_DIST_TEST_GROUP(irq
, (1 << cpu
))) {
463 return 0; /* Non-secure access cannot read priority of Group0 IRQ */
465 prio
= (prio
<< 1) & 0xff; /* Non-secure view */
470 static void gic_set_priority_mask(GICState
*s
, int cpu
, uint8_t pmask
,
473 if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
474 if (s
->priority_mask
[cpu
] & 0x80) {
475 /* Priority Mask in upper half */
476 pmask
= 0x80 | (pmask
>> 1);
478 /* Non-secure write ignored if priority mask is in lower half */
482 s
->priority_mask
[cpu
] = pmask
;
485 static uint32_t gic_get_priority_mask(GICState
*s
, int cpu
, MemTxAttrs attrs
)
487 uint32_t pmask
= s
->priority_mask
[cpu
];
489 if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
491 /* Priority Mask in upper half, return Non-secure view */
492 pmask
= (pmask
<< 1) & 0xff;
494 /* Priority Mask in lower half, RAZ */
501 static uint32_t gic_get_cpu_control(GICState
*s
, int cpu
, MemTxAttrs attrs
)
503 uint32_t ret
= s
->cpu_ctlr
[cpu
];
505 if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
506 /* Construct the NS banked view of GICC_CTLR from the correct
507 * bits of the S banked view. We don't need to move the bypass
508 * control bits because we don't implement that (IMPDEF) part
509 * of the GIC architecture.
511 ret
= (ret
& (GICC_CTLR_EN_GRP1
| GICC_CTLR_EOIMODE_NS
)) >> 1;
516 static void gic_set_cpu_control(GICState
*s
, int cpu
, uint32_t value
,
521 if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
522 /* The NS view can only write certain bits in the register;
523 * the rest are unchanged
525 mask
= GICC_CTLR_EN_GRP1
;
526 if (s
->revision
== 2) {
527 mask
|= GICC_CTLR_EOIMODE_NS
;
529 s
->cpu_ctlr
[cpu
] &= ~mask
;
530 s
->cpu_ctlr
[cpu
] |= (value
<< 1) & mask
;
532 if (s
->revision
== 2) {
533 mask
= s
->security_extn
? GICC_CTLR_V2_S_MASK
: GICC_CTLR_V2_MASK
;
535 mask
= s
->security_extn
? GICC_CTLR_V1_S_MASK
: GICC_CTLR_V1_MASK
;
537 s
->cpu_ctlr
[cpu
] = value
& mask
;
539 DPRINTF("CPU Interface %d: Group0 Interrupts %sabled, "
540 "Group1 Interrupts %sabled\n", cpu
,
541 (s
->cpu_ctlr
[cpu
] & GICC_CTLR_EN_GRP0
) ? "En" : "Dis",
542 (s
->cpu_ctlr
[cpu
] & GICC_CTLR_EN_GRP1
) ? "En" : "Dis");
545 static uint8_t gic_get_running_priority(GICState
*s
, int cpu
, MemTxAttrs attrs
)
547 if ((s
->revision
!= REV_11MPCORE
) && (s
->running_priority
[cpu
] > 0xff)) {
552 if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
553 if (s
->running_priority
[cpu
] & 0x80) {
554 /* Running priority in upper half of range: return the Non-secure
555 * view of the priority.
557 return s
->running_priority
[cpu
] << 1;
559 /* Running priority in lower half of range: RAZ */
563 return s
->running_priority
[cpu
];
567 /* Return true if we should split priority drop and interrupt deactivation,
568 * ie whether the relevant EOIMode bit is set.
570 static bool gic_eoi_split(GICState
*s
, int cpu
, MemTxAttrs attrs
)
572 if (s
->revision
!= 2) {
573 /* Before GICv2 prio-drop and deactivate are not separable */
576 if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
577 return s
->cpu_ctlr
[cpu
] & GICC_CTLR_EOIMODE_NS
;
579 return s
->cpu_ctlr
[cpu
] & GICC_CTLR_EOIMODE
;
582 static void gic_deactivate_irq(GICState
*s
, int cpu
, int irq
, MemTxAttrs attrs
)
586 if (irq
>= GIC_MAXIRQ
|| (!gic_is_vcpu(cpu
) && irq
>= s
->num_irq
)) {
588 * This handles two cases:
589 * 1. If software writes the ID of a spurious interrupt [ie 1023]
590 * to the GICC_DIR, the GIC ignores that write.
591 * 2. If software writes the number of a non-existent interrupt
592 * this must be a subcase of "value written is not an active interrupt"
593 * and so this is UNPREDICTABLE. We choose to ignore it. For vCPUs,
594 * all IRQs potentially exist, so this limit does not apply.
599 if (!gic_eoi_split(s
, cpu
, attrs
)) {
600 /* This is UNPREDICTABLE; we choose to ignore it */
601 qemu_log_mask(LOG_GUEST_ERROR
,
602 "gic_deactivate_irq: GICC_DIR write when EOIMode clear");
606 if (gic_is_vcpu(cpu
) && !gic_virq_is_valid(s
, irq
, cpu
)) {
607 /* This vIRQ does not have an LR entry which is either active or
608 * pending and active. Increment EOICount and ignore the write.
610 int rcpu
= gic_get_vcpu_real_id(cpu
);
611 s
->h_hcr
[rcpu
] += 1 << R_GICH_HCR_EOICount_SHIFT
;
615 group
= gic_has_groups(s
) && gic_test_group(s
, irq
, cpu
);
617 if (gic_cpu_ns_access(s
, cpu
, attrs
) && !group
) {
618 DPRINTF("Non-secure DI for Group0 interrupt %d ignored\n", irq
);
622 gic_clear_active(s
, irq
, cpu
);
625 static void gic_complete_irq(GICState
*s
, int cpu
, int irq
, MemTxAttrs attrs
)
630 DPRINTF("EOI %d\n", irq
);
631 if (gic_is_vcpu(cpu
)) {
632 /* The call to gic_prio_drop() will clear a bit in GICH_APR iff the
633 * running prio is < 0x100.
635 bool prio_drop
= s
->running_priority
[cpu
] < 0x100;
637 if (irq
>= GIC_MAXIRQ
) {
638 /* Ignore spurious interrupt */
642 gic_drop_prio(s
, cpu
, 0);
644 if (!gic_eoi_split(s
, cpu
, attrs
)) {
645 bool valid
= gic_virq_is_valid(s
, irq
, cpu
);
646 if (prio_drop
&& !valid
) {
647 /* We are in a situation where:
648 * - V_CTRL.EOIMode is false (no EOI split),
649 * - The call to gic_drop_prio() cleared a bit in GICH_APR,
650 * - This vIRQ does not have an LR entry which is either
651 * active or pending and active.
652 * In that case, we must increment EOICount.
654 int rcpu
= gic_get_vcpu_real_id(cpu
);
655 s
->h_hcr
[rcpu
] += 1 << R_GICH_HCR_EOICount_SHIFT
;
657 gic_clear_active(s
, irq
, cpu
);
664 if (irq
>= s
->num_irq
) {
665 /* This handles two cases:
666 * 1. If software writes the ID of a spurious interrupt [ie 1023]
667 * to the GICC_EOIR, the GIC ignores that write.
668 * 2. If software writes the number of a non-existent interrupt
669 * this must be a subcase of "value written does not match the last
670 * valid interrupt value read from the Interrupt Acknowledge
671 * register" and so this is UNPREDICTABLE. We choose to ignore it.
675 if (s
->running_priority
[cpu
] == 0x100) {
676 return; /* No active IRQ. */
679 if (s
->revision
== REV_11MPCORE
) {
680 /* Mark level triggered interrupts as pending if they are still
682 if (!GIC_DIST_TEST_EDGE_TRIGGER(irq
) && GIC_DIST_TEST_ENABLED(irq
, cm
)
683 && GIC_DIST_TEST_LEVEL(irq
, cm
)
684 && (GIC_DIST_TARGET(irq
) & cm
) != 0) {
685 DPRINTF("Set %d pending mask %x\n", irq
, cm
);
686 GIC_DIST_SET_PENDING(irq
, cm
);
690 group
= gic_has_groups(s
) && gic_test_group(s
, irq
, cpu
);
692 if (gic_cpu_ns_access(s
, cpu
, attrs
) && !group
) {
693 DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq
);
697 /* Secure EOI with GICC_CTLR.AckCtl == 0 when the IRQ is a Group 1
698 * interrupt is UNPREDICTABLE. We choose to handle it as if AckCtl == 1,
699 * i.e. go ahead and complete the irq anyway.
702 gic_drop_prio(s
, cpu
, group
);
704 /* In GICv2 the guest can choose to split priority-drop and deactivate */
705 if (!gic_eoi_split(s
, cpu
, attrs
)) {
706 gic_clear_active(s
, irq
, cpu
);
711 static uint32_t gic_dist_readb(void *opaque
, hwaddr offset
, MemTxAttrs attrs
)
713 GICState
*s
= (GICState
*)opaque
;
721 cpu
= gic_get_current_cpu(s
);
723 if (offset
< 0x100) {
724 if (offset
== 0) { /* GICD_CTLR */
725 if (s
->security_extn
&& !attrs
.secure
) {
726 /* The NS bank of this register is just an alias of the
727 * EnableGrp1 bit in the S bank version.
729 return extract32(s
->ctlr
, 1, 1);
735 /* Interrupt Controller Type Register */
736 return ((s
->num_irq
/ 32) - 1)
737 | ((s
->num_cpu
- 1) << 5)
738 | (s
->security_extn
<< 10);
741 if (offset
>= 0x80) {
742 /* Interrupt Group Registers: these RAZ/WI if this is an NS
743 * access to a GIC with the security extensions, or if the GIC
744 * doesn't have groups at all.
747 if (!(s
->security_extn
&& !attrs
.secure
) && gic_has_groups(s
)) {
748 /* Every byte offset holds 8 group status bits */
749 irq
= (offset
- 0x080) * 8 + GIC_BASE_IRQ
;
750 if (irq
>= s
->num_irq
) {
753 for (i
= 0; i
< 8; i
++) {
754 if (GIC_DIST_TEST_GROUP(irq
+ i
, cm
)) {
762 } else if (offset
< 0x200) {
763 /* Interrupt Set/Clear Enable. */
765 irq
= (offset
- 0x100) * 8;
767 irq
= (offset
- 0x180) * 8;
769 if (irq
>= s
->num_irq
)
772 for (i
= 0; i
< 8; i
++) {
773 if (s
->security_extn
&& !attrs
.secure
&&
774 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
775 continue; /* Ignore Non-secure access of Group0 IRQ */
778 if (GIC_DIST_TEST_ENABLED(irq
+ i
, cm
)) {
782 } else if (offset
< 0x300) {
783 /* Interrupt Set/Clear Pending. */
785 irq
= (offset
- 0x200) * 8;
787 irq
= (offset
- 0x280) * 8;
789 if (irq
>= s
->num_irq
)
792 mask
= (irq
< GIC_INTERNAL
) ? cm
: ALL_CPU_MASK
;
793 for (i
= 0; i
< 8; i
++) {
794 if (s
->security_extn
&& !attrs
.secure
&&
795 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
796 continue; /* Ignore Non-secure access of Group0 IRQ */
799 if (gic_test_pending(s
, irq
+ i
, mask
)) {
803 } else if (offset
< 0x400) {
804 /* Interrupt Set/Clear Active. */
805 if (offset
< 0x380) {
806 irq
= (offset
- 0x300) * 8;
807 } else if (s
->revision
== 2) {
808 irq
= (offset
- 0x380) * 8;
814 if (irq
>= s
->num_irq
)
817 mask
= (irq
< GIC_INTERNAL
) ? cm
: ALL_CPU_MASK
;
818 for (i
= 0; i
< 8; i
++) {
819 if (s
->security_extn
&& !attrs
.secure
&&
820 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
821 continue; /* Ignore Non-secure access of Group0 IRQ */
824 if (GIC_DIST_TEST_ACTIVE(irq
+ i
, mask
)) {
828 } else if (offset
< 0x800) {
829 /* Interrupt Priority. */
830 irq
= (offset
- 0x400) + GIC_BASE_IRQ
;
831 if (irq
>= s
->num_irq
)
833 res
= gic_dist_get_priority(s
, cpu
, irq
, attrs
);
834 } else if (offset
< 0xc00) {
835 /* Interrupt CPU Target. */
836 if (s
->num_cpu
== 1 && s
->revision
!= REV_11MPCORE
) {
837 /* For uniprocessor GICs these RAZ/WI */
840 irq
= (offset
- 0x800) + GIC_BASE_IRQ
;
841 if (irq
>= s
->num_irq
) {
844 if (irq
< 29 && s
->revision
== REV_11MPCORE
) {
846 } else if (irq
< GIC_INTERNAL
) {
849 res
= GIC_DIST_TARGET(irq
);
852 } else if (offset
< 0xf00) {
853 /* Interrupt Configuration. */
854 irq
= (offset
- 0xc00) * 4 + GIC_BASE_IRQ
;
855 if (irq
>= s
->num_irq
)
858 for (i
= 0; i
< 4; i
++) {
859 if (s
->security_extn
&& !attrs
.secure
&&
860 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
861 continue; /* Ignore Non-secure access of Group0 IRQ */
864 if (GIC_DIST_TEST_MODEL(irq
+ i
)) {
865 res
|= (1 << (i
* 2));
867 if (GIC_DIST_TEST_EDGE_TRIGGER(irq
+ i
)) {
868 res
|= (2 << (i
* 2));
871 } else if (offset
< 0xf10) {
873 } else if (offset
< 0xf30) {
874 if (s
->revision
== REV_11MPCORE
) {
878 if (offset
< 0xf20) {
879 /* GICD_CPENDSGIRn */
880 irq
= (offset
- 0xf10);
882 irq
= (offset
- 0xf20);
883 /* GICD_SPENDSGIRn */
886 if (s
->security_extn
&& !attrs
.secure
&&
887 !GIC_DIST_TEST_GROUP(irq
, 1 << cpu
)) {
888 res
= 0; /* Ignore Non-secure access of Group0 IRQ */
890 res
= s
->sgi_pending
[irq
][cpu
];
892 } else if (offset
< 0xfd0) {
894 } else if (offset
< 0x1000) {
898 switch (s
->revision
) {
900 res
= gic_id_11mpcore
[(offset
- 0xfd0) >> 2];
903 res
= gic_id_gicv1
[(offset
- 0xfd0) >> 2];
906 res
= gic_id_gicv2
[(offset
- 0xfd0) >> 2];
913 g_assert_not_reached();
917 qemu_log_mask(LOG_GUEST_ERROR
,
918 "gic_dist_readb: Bad offset %x\n", (int)offset
);
922 static MemTxResult
gic_dist_read(void *opaque
, hwaddr offset
, uint64_t *data
,
923 unsigned size
, MemTxAttrs attrs
)
927 *data
= gic_dist_readb(opaque
, offset
, attrs
);
930 *data
= gic_dist_readb(opaque
, offset
, attrs
);
931 *data
|= gic_dist_readb(opaque
, offset
+ 1, attrs
) << 8;
934 *data
= gic_dist_readb(opaque
, offset
, attrs
);
935 *data
|= gic_dist_readb(opaque
, offset
+ 1, attrs
) << 8;
936 *data
|= gic_dist_readb(opaque
, offset
+ 2, attrs
) << 16;
937 *data
|= gic_dist_readb(opaque
, offset
+ 3, attrs
) << 24;
944 static void gic_dist_writeb(void *opaque
, hwaddr offset
,
945 uint32_t value
, MemTxAttrs attrs
)
947 GICState
*s
= (GICState
*)opaque
;
952 cpu
= gic_get_current_cpu(s
);
953 if (offset
< 0x100) {
955 if (s
->security_extn
&& !attrs
.secure
) {
956 /* NS version is just an alias of the S version's bit 1 */
957 s
->ctlr
= deposit32(s
->ctlr
, 1, 1, value
);
958 } else if (gic_has_groups(s
)) {
959 s
->ctlr
= value
& (GICD_CTLR_EN_GRP0
| GICD_CTLR_EN_GRP1
);
961 s
->ctlr
= value
& GICD_CTLR_EN_GRP0
;
963 DPRINTF("Distributor: Group0 %sabled; Group 1 %sabled\n",
964 s
->ctlr
& GICD_CTLR_EN_GRP0
? "En" : "Dis",
965 s
->ctlr
& GICD_CTLR_EN_GRP1
? "En" : "Dis");
966 } else if (offset
< 4) {
968 } else if (offset
>= 0x80) {
969 /* Interrupt Group Registers: RAZ/WI for NS access to secure
970 * GIC, or for GICs without groups.
972 if (!(s
->security_extn
&& !attrs
.secure
) && gic_has_groups(s
)) {
973 /* Every byte offset holds 8 group status bits */
974 irq
= (offset
- 0x80) * 8 + GIC_BASE_IRQ
;
975 if (irq
>= s
->num_irq
) {
978 for (i
= 0; i
< 8; i
++) {
979 /* Group bits are banked for private interrupts */
980 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
981 if (value
& (1 << i
)) {
982 /* Group1 (Non-secure) */
983 GIC_DIST_SET_GROUP(irq
+ i
, cm
);
985 /* Group0 (Secure) */
986 GIC_DIST_CLEAR_GROUP(irq
+ i
, cm
);
993 } else if (offset
< 0x180) {
994 /* Interrupt Set Enable. */
995 irq
= (offset
- 0x100) * 8 + GIC_BASE_IRQ
;
996 if (irq
>= s
->num_irq
)
998 if (irq
< GIC_NR_SGIS
) {
1002 for (i
= 0; i
< 8; i
++) {
1003 if (value
& (1 << i
)) {
1005 (irq
< GIC_INTERNAL
) ? (1 << cpu
)
1006 : GIC_DIST_TARGET(irq
+ i
);
1007 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
1009 if (s
->security_extn
&& !attrs
.secure
&&
1010 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1011 continue; /* Ignore Non-secure access of Group0 IRQ */
1014 if (!GIC_DIST_TEST_ENABLED(irq
+ i
, cm
)) {
1015 DPRINTF("Enabled IRQ %d\n", irq
+ i
);
1016 trace_gic_enable_irq(irq
+ i
);
1018 GIC_DIST_SET_ENABLED(irq
+ i
, cm
);
1019 /* If a raised level triggered IRQ enabled then mark
1021 if (GIC_DIST_TEST_LEVEL(irq
+ i
, mask
)
1022 && !GIC_DIST_TEST_EDGE_TRIGGER(irq
+ i
)) {
1023 DPRINTF("Set %d pending mask %x\n", irq
+ i
, mask
);
1024 GIC_DIST_SET_PENDING(irq
+ i
, mask
);
1028 } else if (offset
< 0x200) {
1029 /* Interrupt Clear Enable. */
1030 irq
= (offset
- 0x180) * 8 + GIC_BASE_IRQ
;
1031 if (irq
>= s
->num_irq
)
1033 if (irq
< GIC_NR_SGIS
) {
1037 for (i
= 0; i
< 8; i
++) {
1038 if (value
& (1 << i
)) {
1039 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
1041 if (s
->security_extn
&& !attrs
.secure
&&
1042 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1043 continue; /* Ignore Non-secure access of Group0 IRQ */
1046 if (GIC_DIST_TEST_ENABLED(irq
+ i
, cm
)) {
1047 DPRINTF("Disabled IRQ %d\n", irq
+ i
);
1048 trace_gic_disable_irq(irq
+ i
);
1050 GIC_DIST_CLEAR_ENABLED(irq
+ i
, cm
);
1053 } else if (offset
< 0x280) {
1054 /* Interrupt Set Pending. */
1055 irq
= (offset
- 0x200) * 8 + GIC_BASE_IRQ
;
1056 if (irq
>= s
->num_irq
)
1058 if (irq
< GIC_NR_SGIS
) {
1062 for (i
= 0; i
< 8; i
++) {
1063 if (value
& (1 << i
)) {
1064 if (s
->security_extn
&& !attrs
.secure
&&
1065 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1066 continue; /* Ignore Non-secure access of Group0 IRQ */
1069 GIC_DIST_SET_PENDING(irq
+ i
, GIC_DIST_TARGET(irq
+ i
));
1072 } else if (offset
< 0x300) {
1073 /* Interrupt Clear Pending. */
1074 irq
= (offset
- 0x280) * 8 + GIC_BASE_IRQ
;
1075 if (irq
>= s
->num_irq
)
1077 if (irq
< GIC_NR_SGIS
) {
1081 for (i
= 0; i
< 8; i
++) {
1082 if (s
->security_extn
&& !attrs
.secure
&&
1083 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1084 continue; /* Ignore Non-secure access of Group0 IRQ */
1087 /* ??? This currently clears the pending bit for all CPUs, even
1088 for per-CPU interrupts. It's unclear whether this is the
1090 if (value
& (1 << i
)) {
1091 GIC_DIST_CLEAR_PENDING(irq
+ i
, ALL_CPU_MASK
);
1094 } else if (offset
< 0x380) {
1095 /* Interrupt Set Active. */
1096 if (s
->revision
!= 2) {
1100 irq
= (offset
- 0x300) * 8 + GIC_BASE_IRQ
;
1101 if (irq
>= s
->num_irq
) {
1105 /* This register is banked per-cpu for PPIs */
1106 int cm
= irq
< GIC_INTERNAL
? (1 << cpu
) : ALL_CPU_MASK
;
1108 for (i
= 0; i
< 8; i
++) {
1109 if (s
->security_extn
&& !attrs
.secure
&&
1110 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1111 continue; /* Ignore Non-secure access of Group0 IRQ */
1114 if (value
& (1 << i
)) {
1115 GIC_DIST_SET_ACTIVE(irq
+ i
, cm
);
1118 } else if (offset
< 0x400) {
1119 /* Interrupt Clear Active. */
1120 if (s
->revision
!= 2) {
1124 irq
= (offset
- 0x380) * 8 + GIC_BASE_IRQ
;
1125 if (irq
>= s
->num_irq
) {
1129 /* This register is banked per-cpu for PPIs */
1130 int cm
= irq
< GIC_INTERNAL
? (1 << cpu
) : ALL_CPU_MASK
;
1132 for (i
= 0; i
< 8; i
++) {
1133 if (s
->security_extn
&& !attrs
.secure
&&
1134 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1135 continue; /* Ignore Non-secure access of Group0 IRQ */
1138 if (value
& (1 << i
)) {
1139 GIC_DIST_CLEAR_ACTIVE(irq
+ i
, cm
);
1142 } else if (offset
< 0x800) {
1143 /* Interrupt Priority. */
1144 irq
= (offset
- 0x400) + GIC_BASE_IRQ
;
1145 if (irq
>= s
->num_irq
)
1147 gic_dist_set_priority(s
, cpu
, irq
, value
, attrs
);
1148 } else if (offset
< 0xc00) {
1149 /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the
1150 * annoying exception of the 11MPCore's GIC.
1152 if (s
->num_cpu
!= 1 || s
->revision
== REV_11MPCORE
) {
1153 irq
= (offset
- 0x800) + GIC_BASE_IRQ
;
1154 if (irq
>= s
->num_irq
) {
1157 if (irq
< 29 && s
->revision
== REV_11MPCORE
) {
1159 } else if (irq
< GIC_INTERNAL
) {
1160 value
= ALL_CPU_MASK
;
1162 s
->irq_target
[irq
] = value
& ALL_CPU_MASK
;
1164 } else if (offset
< 0xf00) {
1165 /* Interrupt Configuration. */
1166 irq
= (offset
- 0xc00) * 4 + GIC_BASE_IRQ
;
1167 if (irq
>= s
->num_irq
)
1169 if (irq
< GIC_NR_SGIS
)
1171 for (i
= 0; i
< 4; i
++) {
1172 if (s
->security_extn
&& !attrs
.secure
&&
1173 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1174 continue; /* Ignore Non-secure access of Group0 IRQ */
1177 if (s
->revision
== REV_11MPCORE
) {
1178 if (value
& (1 << (i
* 2))) {
1179 GIC_DIST_SET_MODEL(irq
+ i
);
1181 GIC_DIST_CLEAR_MODEL(irq
+ i
);
1184 if (value
& (2 << (i
* 2))) {
1185 GIC_DIST_SET_EDGE_TRIGGER(irq
+ i
);
1187 GIC_DIST_CLEAR_EDGE_TRIGGER(irq
+ i
);
1190 } else if (offset
< 0xf10) {
1191 /* 0xf00 is only handled for 32-bit writes. */
1193 } else if (offset
< 0xf20) {
1194 /* GICD_CPENDSGIRn */
1195 if (s
->revision
== REV_11MPCORE
) {
1198 irq
= (offset
- 0xf10);
1200 if (!s
->security_extn
|| attrs
.secure
||
1201 GIC_DIST_TEST_GROUP(irq
, 1 << cpu
)) {
1202 s
->sgi_pending
[irq
][cpu
] &= ~value
;
1203 if (s
->sgi_pending
[irq
][cpu
] == 0) {
1204 GIC_DIST_CLEAR_PENDING(irq
, 1 << cpu
);
1207 } else if (offset
< 0xf30) {
1208 /* GICD_SPENDSGIRn */
1209 if (s
->revision
== REV_11MPCORE
) {
1212 irq
= (offset
- 0xf20);
1214 if (!s
->security_extn
|| attrs
.secure
||
1215 GIC_DIST_TEST_GROUP(irq
, 1 << cpu
)) {
1216 GIC_DIST_SET_PENDING(irq
, 1 << cpu
);
1217 s
->sgi_pending
[irq
][cpu
] |= value
;
1225 qemu_log_mask(LOG_GUEST_ERROR
,
1226 "gic_dist_writeb: Bad offset %x\n", (int)offset
);
1229 static void gic_dist_writew(void *opaque
, hwaddr offset
,
1230 uint32_t value
, MemTxAttrs attrs
)
1232 gic_dist_writeb(opaque
, offset
, value
& 0xff, attrs
);
1233 gic_dist_writeb(opaque
, offset
+ 1, value
>> 8, attrs
);
1236 static void gic_dist_writel(void *opaque
, hwaddr offset
,
1237 uint32_t value
, MemTxAttrs attrs
)
1239 GICState
*s
= (GICState
*)opaque
;
1240 if (offset
== 0xf00) {
1246 cpu
= gic_get_current_cpu(s
);
1247 irq
= value
& 0x3ff;
1248 switch ((value
>> 24) & 3) {
1250 mask
= (value
>> 16) & ALL_CPU_MASK
;
1253 mask
= ALL_CPU_MASK
^ (1 << cpu
);
1259 DPRINTF("Bad Soft Int target filter\n");
1260 mask
= ALL_CPU_MASK
;
1263 GIC_DIST_SET_PENDING(irq
, mask
);
1264 target_cpu
= ctz32(mask
);
1265 while (target_cpu
< GIC_NCPU
) {
1266 s
->sgi_pending
[irq
][target_cpu
] |= (1 << cpu
);
1267 mask
&= ~(1 << target_cpu
);
1268 target_cpu
= ctz32(mask
);
1273 gic_dist_writew(opaque
, offset
, value
& 0xffff, attrs
);
1274 gic_dist_writew(opaque
, offset
+ 2, value
>> 16, attrs
);
1277 static MemTxResult
gic_dist_write(void *opaque
, hwaddr offset
, uint64_t data
,
1278 unsigned size
, MemTxAttrs attrs
)
1282 gic_dist_writeb(opaque
, offset
, data
, attrs
);
1285 gic_dist_writew(opaque
, offset
, data
, attrs
);
1288 gic_dist_writel(opaque
, offset
, data
, attrs
);
1295 static inline uint32_t gic_apr_ns_view(GICState
*s
, int cpu
, int regno
)
1297 /* Return the Nonsecure view of GICC_APR<regno>. This is the
1298 * second half of GICC_NSAPR.
1300 switch (GIC_MIN_BPR
) {
1303 return s
->nsapr
[regno
+ 2][cpu
];
1308 return s
->nsapr
[regno
+ 1][cpu
];
1313 return extract32(s
->nsapr
[0][cpu
], 16, 16);
1318 return extract32(s
->nsapr
[0][cpu
], 8, 8);
1322 g_assert_not_reached();
1327 static inline void gic_apr_write_ns_view(GICState
*s
, int cpu
, int regno
,
1330 /* Write the Nonsecure view of GICC_APR<regno>. */
1331 switch (GIC_MIN_BPR
) {
1334 s
->nsapr
[regno
+ 2][cpu
] = value
;
1339 s
->nsapr
[regno
+ 1][cpu
] = value
;
1344 s
->nsapr
[0][cpu
] = deposit32(s
->nsapr
[0][cpu
], 16, 16, value
);
1349 s
->nsapr
[0][cpu
] = deposit32(s
->nsapr
[0][cpu
], 8, 8, value
);
1353 g_assert_not_reached();
1357 static MemTxResult
gic_cpu_read(GICState
*s
, int cpu
, int offset
,
1358 uint64_t *data
, MemTxAttrs attrs
)
1361 case 0x00: /* Control */
1362 *data
= gic_get_cpu_control(s
, cpu
, attrs
);
1364 case 0x04: /* Priority mask */
1365 *data
= gic_get_priority_mask(s
, cpu
, attrs
);
1367 case 0x08: /* Binary Point */
1368 if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
1369 if (s
->cpu_ctlr
[cpu
] & GICC_CTLR_CBPR
) {
1370 /* NS view of BPR when CBPR is 1 */
1371 *data
= MIN(s
->bpr
[cpu
] + 1, 7);
1373 /* BPR is banked. Non-secure copy stored in ABPR. */
1374 *data
= s
->abpr
[cpu
];
1377 *data
= s
->bpr
[cpu
];
1380 case 0x0c: /* Acknowledge */
1381 *data
= gic_acknowledge_irq(s
, cpu
, attrs
);
1383 case 0x14: /* Running Priority */
1384 *data
= gic_get_running_priority(s
, cpu
, attrs
);
1386 case 0x18: /* Highest Pending Interrupt */
1387 *data
= gic_get_current_pending_irq(s
, cpu
, attrs
);
1389 case 0x1c: /* Aliased Binary Point */
1390 /* GIC v2, no security: ABPR
1391 * GIC v1, no security: not implemented (RAZ/WI)
1392 * With security extensions, secure access: ABPR (alias of NS BPR)
1393 * With security extensions, nonsecure access: RAZ/WI
1395 if (!gic_has_groups(s
) || (gic_cpu_ns_access(s
, cpu
, attrs
))) {
1398 *data
= s
->abpr
[cpu
];
1401 case 0xd0: case 0xd4: case 0xd8: case 0xdc:
1403 int regno
= (offset
- 0xd0) / 4;
1405 if (regno
>= GIC_NR_APRS
|| s
->revision
!= 2) {
1407 } else if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
1408 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */
1409 *data
= gic_apr_ns_view(s
, regno
, cpu
);
1411 *data
= s
->apr
[regno
][cpu
];
1415 case 0xe0: case 0xe4: case 0xe8: case 0xec:
1417 int regno
= (offset
- 0xe0) / 4;
1419 if (regno
>= GIC_NR_APRS
|| s
->revision
!= 2 || !gic_has_groups(s
) ||
1420 gic_cpu_ns_access(s
, cpu
, attrs
)) {
1423 *data
= s
->nsapr
[regno
][cpu
];
1428 qemu_log_mask(LOG_GUEST_ERROR
,
1429 "gic_cpu_read: Bad offset %x\n", (int)offset
);
1436 static MemTxResult
gic_cpu_write(GICState
*s
, int cpu
, int offset
,
1437 uint32_t value
, MemTxAttrs attrs
)
1440 case 0x00: /* Control */
1441 gic_set_cpu_control(s
, cpu
, value
, attrs
);
1443 case 0x04: /* Priority mask */
1444 gic_set_priority_mask(s
, cpu
, value
, attrs
);
1446 case 0x08: /* Binary Point */
1447 if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
1448 if (s
->cpu_ctlr
[cpu
] & GICC_CTLR_CBPR
) {
1449 /* WI when CBPR is 1 */
1452 s
->abpr
[cpu
] = MAX(value
& 0x7, GIC_MIN_ABPR
);
1455 s
->bpr
[cpu
] = MAX(value
& 0x7, GIC_MIN_BPR
);
1458 case 0x10: /* End Of Interrupt */
1459 gic_complete_irq(s
, cpu
, value
& 0x3ff, attrs
);
1461 case 0x1c: /* Aliased Binary Point */
1462 if (!gic_has_groups(s
) || (gic_cpu_ns_access(s
, cpu
, attrs
))) {
1463 /* unimplemented, or NS access: RAZ/WI */
1466 s
->abpr
[cpu
] = MAX(value
& 0x7, GIC_MIN_ABPR
);
1469 case 0xd0: case 0xd4: case 0xd8: case 0xdc:
1471 int regno
= (offset
- 0xd0) / 4;
1473 if (regno
>= GIC_NR_APRS
|| s
->revision
!= 2) {
1476 if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
1477 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */
1478 gic_apr_write_ns_view(s
, regno
, cpu
, value
);
1480 s
->apr
[regno
][cpu
] = value
;
1484 case 0xe0: case 0xe4: case 0xe8: case 0xec:
1486 int regno
= (offset
- 0xe0) / 4;
1488 if (regno
>= GIC_NR_APRS
|| s
->revision
!= 2) {
1491 if (!gic_has_groups(s
) || (gic_cpu_ns_access(s
, cpu
, attrs
))) {
1494 s
->nsapr
[regno
][cpu
] = value
;
1499 gic_deactivate_irq(s
, cpu
, value
& 0x3ff, attrs
);
1502 qemu_log_mask(LOG_GUEST_ERROR
,
1503 "gic_cpu_write: Bad offset %x\n", (int)offset
);
1510 /* Wrappers to read/write the GIC CPU interface for the current CPU */
1511 static MemTxResult
gic_thiscpu_read(void *opaque
, hwaddr addr
, uint64_t *data
,
1512 unsigned size
, MemTxAttrs attrs
)
1514 GICState
*s
= (GICState
*)opaque
;
1515 return gic_cpu_read(s
, gic_get_current_cpu(s
), addr
, data
, attrs
);
1518 static MemTxResult
gic_thiscpu_write(void *opaque
, hwaddr addr
,
1519 uint64_t value
, unsigned size
,
1522 GICState
*s
= (GICState
*)opaque
;
1523 return gic_cpu_write(s
, gic_get_current_cpu(s
), addr
, value
, attrs
);
1526 /* Wrappers to read/write the GIC CPU interface for a specific CPU.
1527 * These just decode the opaque pointer into GICState* + cpu id.
1529 static MemTxResult
gic_do_cpu_read(void *opaque
, hwaddr addr
, uint64_t *data
,
1530 unsigned size
, MemTxAttrs attrs
)
1532 GICState
**backref
= (GICState
**)opaque
;
1533 GICState
*s
= *backref
;
1534 int id
= (backref
- s
->backref
);
1535 return gic_cpu_read(s
, id
, addr
, data
, attrs
);
1538 static MemTxResult
gic_do_cpu_write(void *opaque
, hwaddr addr
,
1539 uint64_t value
, unsigned size
,
1542 GICState
**backref
= (GICState
**)opaque
;
1543 GICState
*s
= *backref
;
1544 int id
= (backref
- s
->backref
);
1545 return gic_cpu_write(s
, id
, addr
, value
, attrs
);
1548 static const MemoryRegionOps gic_ops
[2] = {
1550 .read_with_attrs
= gic_dist_read
,
1551 .write_with_attrs
= gic_dist_write
,
1552 .endianness
= DEVICE_NATIVE_ENDIAN
,
1555 .read_with_attrs
= gic_thiscpu_read
,
1556 .write_with_attrs
= gic_thiscpu_write
,
1557 .endianness
= DEVICE_NATIVE_ENDIAN
,
1561 static const MemoryRegionOps gic_cpu_ops
= {
1562 .read_with_attrs
= gic_do_cpu_read
,
1563 .write_with_attrs
= gic_do_cpu_write
,
1564 .endianness
= DEVICE_NATIVE_ENDIAN
,
1567 static void arm_gic_realize(DeviceState
*dev
, Error
**errp
)
1569 /* Device instance realize function for the GIC sysbus device */
1571 GICState
*s
= ARM_GIC(dev
);
1572 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
1573 ARMGICClass
*agc
= ARM_GIC_GET_CLASS(s
);
1574 Error
*local_err
= NULL
;
1576 agc
->parent_realize(dev
, &local_err
);
1578 error_propagate(errp
, local_err
);
1582 if (kvm_enabled() && !kvm_arm_supports_user_irq()) {
1583 error_setg(errp
, "KVM with user space irqchip only works when the "
1584 "host kernel supports KVM_CAP_ARM_USER_IRQ");
1588 /* This creates distributor and main CPU interface (s->cpuiomem[0]) */
1589 gic_init_irqs_and_mmio(s
, gic_set_irq
, gic_ops
, NULL
);
1591 /* Extra core-specific regions for the CPU interfaces. This is
1592 * necessary for "franken-GIC" implementations, for example on
1594 * NB that the memory region size of 0x100 applies for the 11MPCore
1595 * and also cores following the GIC v1 spec (ie A9).
1596 * GIC v2 defines a larger memory region (0x1000) so this will need
1597 * to be extended when we implement A15.
1599 for (i
= 0; i
< s
->num_cpu
; i
++) {
1601 memory_region_init_io(&s
->cpuiomem
[i
+1], OBJECT(s
), &gic_cpu_ops
,
1602 &s
->backref
[i
], "gic_cpu", 0x100);
1603 sysbus_init_mmio(sbd
, &s
->cpuiomem
[i
+1]);
1607 static void arm_gic_class_init(ObjectClass
*klass
, void *data
)
1609 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1610 ARMGICClass
*agc
= ARM_GIC_CLASS(klass
);
1612 device_class_set_parent_realize(dc
, arm_gic_realize
, &agc
->parent_realize
);
1615 static const TypeInfo arm_gic_info
= {
1616 .name
= TYPE_ARM_GIC
,
1617 .parent
= TYPE_ARM_GIC_COMMON
,
1618 .instance_size
= sizeof(GICState
),
1619 .class_init
= arm_gic_class_init
,
1620 .class_size
= sizeof(ARMGICClass
),
1623 static void arm_gic_register_types(void)
1625 type_register_static(&arm_gic_info
);
1628 type_init(arm_gic_register_types
)