hw/xtensa/pic_cpu.c

   1 /*
   2  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *     * Redistributions of source code must retain the above copyright
   8  *       notice, this list of conditions and the following disclaimer.
   9  *     * Redistributions in binary form must reproduce the above copyright
  10  *       notice, this list of conditions and the following disclaimer in the
  11  *       documentation and/or other materials provided with the distribution.
  12  *     * Neither the name of the Open Source and Linux Lab nor the
  13  *       names of its contributors may be used to endorse or promote products
  14  *       derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  25  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #include "qemu/osdep.h"
  29 #include "cpu.h"
  30 #include "hw/irq.h"
  31 #include "qemu/log.h"
  32 #include "qemu/timer.h"
  33 #include "qemu/atomic.h"
  34
  35 void check_interrupts(CPUXtensaState *env)
  36 {
  37     CPUState *cs = env_cpu(env);
  38     int minlevel = xtensa_get_cintlevel(env);
  39     uint32_t int_set_enabled = env->sregs[INTSET] &
  40         (env->sregs[INTENABLE] | env->config->inttype_mask[INTTYPE_NMI]);
  41     int level;
  42
  43     if (minlevel >= env->config->nmi_level) {
  44         minlevel = env->config->nmi_level - 1;
  45     }
  46     for (level = env->config->nlevel; level > minlevel; --level) {
  47         if (env->config->level_mask[level] & int_set_enabled) {
  48             env->pending_irq_level = level;
  49             cpu_interrupt(cs, CPU_INTERRUPT_HARD);
  50             qemu_log_mask(CPU_LOG_INT,
  51                     "%s level = %d, cintlevel = %d, "
  52                     "pc = %08x, a0 = %08x, ps = %08x, "
  53                     "intset = %08x, intenable = %08x, "
  54                     "ccount = %08x\n",
  55                     __func__, level, xtensa_get_cintlevel(env),
  56                     env->pc, env->regs[0], env->sregs[PS],
  57                     env->sregs[INTSET], env->sregs[INTENABLE],
  58                     env->sregs[CCOUNT]);
  59             return;
  60         }
  61     }
  62     env->pending_irq_level = 0;
  63     cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
  64 }
  65
  66 static void xtensa_set_irq(void *opaque, int irq, int active)
  67 {
  68     CPUXtensaState *env = opaque;
  69
  70     if (irq >= env->config->ninterrupt) {
  71         qemu_log("%s: bad IRQ %d\n", __func__, irq);
  72     } else {
  73         uint32_t irq_bit = 1 << irq;
  74
  75         if (active) {
  76             qatomic_or(&env->sregs[INTSET], irq_bit);
  77         } else if (env->config->interrupt[irq].inttype == INTTYPE_LEVEL) {
  78             qatomic_and(&env->sregs[INTSET], ~irq_bit);
  79         }
  80
  81         check_interrupts(env);
  82     }
  83 }
  84
  85 static void xtensa_ccompare_cb(void *opaque)
  86 {
  87     XtensaCcompareTimer *ccompare = opaque;
  88     CPUXtensaState *env = ccompare->env;
  89     unsigned i = ccompare - env->ccompare;
  90
  91     qemu_set_irq(env->irq_inputs[env->config->timerint[i]], 1);
  92 }
  93
  94 static void xtensa_set_runstall(void *opaque, int irq, int active)
  95 {
  96     CPUXtensaState *env = opaque;
  97     xtensa_runstall(env, active);
  98 }
  99
 100 void xtensa_irq_init(CPUXtensaState *env)
 101 {
 102     unsigned i;
 103
 104     env->irq_inputs = qemu_allocate_irqs(xtensa_set_irq, env,
 105                                          env->config->ninterrupt);
 106     if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT)) {
 107         env->time_base = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 108         env->ccount_base = env->sregs[CCOUNT];
 109         for (i = 0; i < env->config->nccompare; ++i) {
 110             env->ccompare[i].env = env;
 111             env->ccompare[i].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
 112                     xtensa_ccompare_cb, env->ccompare + i);
 113         }
 114     }
 115     for (i = 0; i < env->config->nextint; ++i) {
 116         unsigned irq = env->config->extint[i];
 117
 118         env->ext_irq_inputs[i] = env->irq_inputs[irq];
 119     }
 120     env->runstall_irq = qemu_allocate_irq(xtensa_set_runstall, env, 0);
 121 }
 122
 123 qemu_irq *xtensa_get_extints(CPUXtensaState *env)
 124 {
 125     return env->ext_irq_inputs;
 126 }
 127
 128 qemu_irq xtensa_get_runstall(CPUXtensaState *env)
 129 {
 130     return env->runstall_irq;
 131 }