2 * QEMU IDE Emulation: PCI PIIX3/4 support.
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2006 Openedhand Ltd.
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 * [1] 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR,
27 * 290550-002, Intel Corporation, April 1997.
30 #include "qemu/osdep.h"
31 #include "qapi/error.h"
32 #include "hw/pci/pci.h"
33 #include "hw/ide/piix.h"
34 #include "hw/ide/pci.h"
37 static uint64_t bmdma_read(void *opaque
, hwaddr addr
, unsigned size
)
39 BMDMAState
*bm
= opaque
;
43 return ((uint64_t)1 << (size
* 8)) - 1;
58 trace_bmdma_read(addr
, val
);
62 static void bmdma_write(void *opaque
, hwaddr addr
,
63 uint64_t val
, unsigned size
)
65 BMDMAState
*bm
= opaque
;
71 trace_bmdma_write(addr
, val
);
75 bmdma_cmd_writeb(bm
, val
);
78 bmdma_status_writeb(bm
, val
);
83 static const MemoryRegionOps piix_bmdma_ops
= {
88 static void bmdma_setup_bar(PCIIDEState
*d
)
92 memory_region_init(&d
->bmdma_bar
, OBJECT(d
), "piix-bmdma-container", 16);
93 for(i
= 0;i
< 2; i
++) {
94 BMDMAState
*bm
= &d
->bmdma
[i
];
96 memory_region_init_io(&bm
->extra_io
, OBJECT(d
), &piix_bmdma_ops
, bm
,
98 memory_region_add_subregion(&d
->bmdma_bar
, i
* 8, &bm
->extra_io
);
99 memory_region_init_io(&bm
->addr_ioport
, OBJECT(d
),
100 &bmdma_addr_ioport_ops
, bm
, "bmdma", 4);
101 memory_region_add_subregion(&d
->bmdma_bar
, i
* 8 + 4, &bm
->addr_ioport
);
105 static void piix_ide_reset(DeviceState
*dev
)
107 PCIIDEState
*d
= PCI_IDE(dev
);
108 PCIDevice
*pd
= PCI_DEVICE(d
);
109 uint8_t *pci_conf
= pd
->config
;
112 for (i
= 0; i
< 2; i
++) {
113 ide_bus_reset(&d
->bus
[i
]);
116 /* PCI command register default value (0000h) per [1, p.48]. */
117 pci_set_word(pci_conf
+ PCI_COMMAND
, 0x0000);
118 pci_set_word(pci_conf
+ PCI_STATUS
,
119 PCI_STATUS_DEVSEL_MEDIUM
| PCI_STATUS_FAST_BACK
);
120 pci_set_long(pci_conf
+ 0x20, 0x1); /* BMIBA: 20-23h */
123 static bool pci_piix_init_bus(PCIIDEState
*d
, unsigned i
, Error
**errp
)
125 static const struct {
135 ide_bus_init(&d
->bus
[i
], sizeof(d
->bus
[i
]), DEVICE(d
), i
, 2);
136 ret
= ide_init_ioport(&d
->bus
[i
], NULL
, port_info
[i
].iobase
,
137 port_info
[i
].iobase2
);
139 error_setg_errno(errp
, -ret
, "Failed to realize %s port %u",
140 object_get_typename(OBJECT(d
)), i
);
143 ide_bus_init_output_irq(&d
->bus
[i
], isa_get_irq(NULL
, port_info
[i
].isairq
));
145 bmdma_init(&d
->bus
[i
], &d
->bmdma
[i
], d
);
146 ide_bus_register_restart_cb(&d
->bus
[i
]);
151 static void pci_piix_ide_realize(PCIDevice
*dev
, Error
**errp
)
153 PCIIDEState
*d
= PCI_IDE(dev
);
154 uint8_t *pci_conf
= dev
->config
;
156 pci_conf
[PCI_CLASS_PROG
] = 0x80; // legacy ATA mode
159 pci_register_bar(dev
, 4, PCI_BASE_ADDRESS_SPACE_IO
, &d
->bmdma_bar
);
161 for (unsigned i
= 0; i
< 2; i
++) {
162 if (!pci_piix_init_bus(d
, i
, errp
)) {
168 static void pci_piix_ide_exitfn(PCIDevice
*dev
)
170 PCIIDEState
*d
= PCI_IDE(dev
);
173 for (i
= 0; i
< 2; ++i
) {
174 memory_region_del_subregion(&d
->bmdma_bar
, &d
->bmdma
[i
].extra_io
);
175 memory_region_del_subregion(&d
->bmdma_bar
, &d
->bmdma
[i
].addr_ioport
);
179 /* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
180 static void piix3_ide_class_init(ObjectClass
*klass
, void *data
)
182 DeviceClass
*dc
= DEVICE_CLASS(klass
);
183 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
185 dc
->reset
= piix_ide_reset
;
186 dc
->vmsd
= &vmstate_ide_pci
;
187 k
->realize
= pci_piix_ide_realize
;
188 k
->exit
= pci_piix_ide_exitfn
;
189 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
190 k
->device_id
= PCI_DEVICE_ID_INTEL_82371SB_1
;
191 k
->class_id
= PCI_CLASS_STORAGE_IDE
;
192 set_bit(DEVICE_CATEGORY_STORAGE
, dc
->categories
);
193 dc
->hotpluggable
= false;
196 static const TypeInfo piix3_ide_info
= {
197 .name
= TYPE_PIIX3_IDE
,
198 .parent
= TYPE_PCI_IDE
,
199 .class_init
= piix3_ide_class_init
,
202 /* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */
203 static void piix4_ide_class_init(ObjectClass
*klass
, void *data
)
205 DeviceClass
*dc
= DEVICE_CLASS(klass
);
206 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
208 dc
->reset
= piix_ide_reset
;
209 dc
->vmsd
= &vmstate_ide_pci
;
210 k
->realize
= pci_piix_ide_realize
;
211 k
->exit
= pci_piix_ide_exitfn
;
212 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
213 k
->device_id
= PCI_DEVICE_ID_INTEL_82371AB
;
214 k
->class_id
= PCI_CLASS_STORAGE_IDE
;
215 set_bit(DEVICE_CATEGORY_STORAGE
, dc
->categories
);
216 dc
->hotpluggable
= false;
219 static const TypeInfo piix4_ide_info
= {
220 .name
= TYPE_PIIX4_IDE
,
221 .parent
= TYPE_PCI_IDE
,
222 .class_init
= piix4_ide_class_init
,
225 static void piix_ide_register_types(void)
227 type_register_static(&piix3_ide_info
);
228 type_register_static(&piix4_ide_info
);
231 type_init(piix_ide_register_types
)