target/riscv: Only unify 'riscv32/64' -> 'riscv' for host cpu in meson
[qemu/ar7.git] / fpu / 
tree8d3d898f8835ab399ac819ddd491d63c61706867
drwxr-xr-x   ..
-rw-r--r-- 67 meson.build
-rw-r--r-- 1674 softfloat-parts-addsub.c.inc
-rw-r--r-- 46732 softfloat-parts.c.inc
-rw-r--r-- 29639 softfloat-specialize.c.inc
-rw-r--r-- 150177 softfloat.c