target/riscv: add vector amo operations
[qemu/ar7.git] / target / 
tree81b26e4fb8a9e5c6f5959ac119d755d397521090
drwxr-xr-x   ..
drwxr-xr-x - alpha
drwxr-xr-x - arm
drwxr-xr-x - cris
drwxr-xr-x - hppa
drwxr-xr-x - i386
drwxr-xr-x - lm32
drwxr-xr-x - m68k
drwxr-xr-x - microblaze
drwxr-xr-x - mips
drwxr-xr-x - moxie
drwxr-xr-x - nios2
drwxr-xr-x - openrisc
drwxr-xr-x - ppc
drwxr-xr-x - riscv
drwxr-xr-x - rx
drwxr-xr-x - s390x
drwxr-xr-x - sh4
drwxr-xr-x - sparc
drwxr-xr-x - tilegx
drwxr-xr-x - tricore
drwxr-xr-x - unicore32
drwxr-xr-x - xtensa