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target/riscv/kvm: change kvm_reg_id to uint64_t
2024-02-09 Daniel Henrique... target/riscv/kvm: change kvm_reg_id to uint64_t
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-02-09 Daniel Henrique... target/riscv/cpu.c: remove cpu->cfg.vlen
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-02-09 Daniel Henrique... trans_rvv.c.inc: use vext_get_vlmax() in trans_vrgather_v*()
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-02-09 Daniel Henrique... target/riscv: change vext_get_vlmax() arguments
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-02-09 Daniel Henrique... target/riscv/cpu.h: use 'vlenb' in vext_get_vlmax()
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-02-09 Daniel Henrique... target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-02-09 Daniel Henrique... target/riscv/vector_helper.c: use vlenb in HELPER(vsetvl)
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-02-09 Daniel Henrique... target/riscv/vector_helper.c: use 'vlenb'
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-02-09 Daniel Henrique... target/riscv/insn_trans/trans_rvvk.c.inc: use 'vlenb'
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-02-09 Daniel Henrique... target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb'
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-02-09 Daniel Henrique... target/riscv/insn_trans/trans_rvbf16.c.inc: use cpu...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-02-09 Daniel Henrique... target/riscv/gdbstub.c: use 'vlenb' instead of shifting...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-02-09 Daniel Henrique... target/riscv/csr.c: use 'vlenb' instead of 'vlen'
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-02-09 Daniel Henrique... target/riscv: add 'vlenb' field in cpu->cfg
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-02-09 Alvin Changtarget/riscv: Implement optional CSR mcontext of debug...
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2024-02-09 Daniel Henrique... target/riscv/cpu.c: move 'marchid' to riscv_cpu_properties[]
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-02-09 Daniel Henrique... target/riscv/cpu.c: move 'mimpid' to riscv_cpu_properties[]
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-02-09 Daniel Henrique... target/riscv/cpu.c: move 'mvendorid' to riscv_cpu_properties[]
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-02-09 Daniel Henrique... target/riscv: remove riscv_cpu_options[]
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-02-09 Daniel Henrique... target/riscv: move 'cboz_blocksize' to riscv_cpu_properties[]
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-02-09 Daniel Henrique... target/riscv: move 'cbop_blocksize' to riscv_cpu_properties[]
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-02-09 Daniel Henrique... target/riscv: move 'cbom_blocksize' to riscv_cpu_properties[]
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-02-09 Daniel Henrique... target/riscv: create finalize_features() for KVM
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-02-09 Daniel Henrique... target/riscv: move 'elen' to riscv_cpu_properties[]
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-02-09 Daniel Henrique... target/riscv: move 'vlen' to riscv_cpu_properties[]
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-02-09 Daniel Henrique... target/riscv: rework 'vext_spec'
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-02-09 Daniel Henrique... target/riscv: rework 'priv_spec'
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-02-09 Daniel Henrique... target/riscv: move 'pmp' to riscv_cpu_properties[]
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-02-09 Daniel Henrique... target/riscv: move 'mmu' to riscv_cpu_properties[]
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-02-09 Daniel Henrique... target/riscv: move 'pmu-mask' and 'pmu-num' to riscv_cpu_pro...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-02-09 Daniel Henrique... target/riscv: make riscv_cpu_is_vendor() public
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-02-09 Daniel Henrique... target/riscv/cpu_cfg.h: remove unused fields
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-02-09 Rob Bradfordtarget/riscv: Add step to validate 'B' extension
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-02-09 Rob Bradfordtarget/riscv: Add infrastructure for 'B' MISA extension
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-02-09 Rob Bradfordtarget/riscv: Check for 'A' extension on all atomic...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Alistair Francistarget/riscv: Ensure mideleg is set correctly on reset
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Alistair Francistarget/riscv: Don't adjust vscause for exceptions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Alistair Francistarget/riscv: Assert that the CSR numbers will be correct
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Ivan Klokovtarget/riscv: pmp: Ignore writes when RW=01 and MML=0
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Bin Mengroms/opensbi: Upgrade from v1.3.1 to v1.4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Bin Mengdocs/system/riscv: sifive_u: Update S-mode U-Boot image...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Daniel Henrique... target/riscv/kvm: add RVV and Vector CSR regs
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Daniel Henrique... target/riscv/kvm: do PR_RISCV_V_SET_CONTROL during...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Daniel Henrique... linux-headers: riscv: add ptrace.h
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Daniel Henrique... linux-headers: Update to Linux v6.7-rc5
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Yong-Xuan Wangtarget/riscv/kvm.c: remove group setting of KVM AIA...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Daniel Henrique... target/riscv: add rva22s64 cpu
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Daniel Henrique... target/riscv: add RVA22S64 profile
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Daniel Henrique... target/riscv: add 'parent' in profile description
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Daniel Henrique... target/riscv: add satp_mode profile support
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Daniel Henrique... target/riscv/cpu.c: add riscv_cpu_is_32bit()
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Daniel Henrique... target/riscv/cpu.c: finalize satp_mode earlier
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Daniel Henrique... target/riscv: add priv ver restriction to profiles
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Daniel Henrique... target/riscv: implement svade
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Daniel Henrique... target/riscv: add 'rva22u64' CPU
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Daniel Henrique... riscv-qmp-cmds.c: add profile flags in cpu-model-expansion
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Daniel Henrique... target/riscv/tcg: validate profiles during finalize
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Daniel Henrique... target/riscv/tcg: honor user choice for G MISA bits
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Daniel Henrique... target/riscv/tcg: add hash table insert helpers
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Daniel Henrique... target/riscv/tcg: handle profile MISA bits
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Daniel Henrique... target/riscv/tcg: add riscv_cpu_write_misa_bit()
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Daniel Henrique... target/riscv/tcg: add MISA user options hash
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Daniel Henrique... target/riscv/tcg: add user flag for profile support
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Daniel Henrique... target/riscv/kvm: add 'rva22u64' flag as unavailable
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Daniel Henrique... target/riscv: add rva22u64 profile definition
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Daniel Henrique... riscv-qmp-cmds.c: expose named features in cpu_model_expansion
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Daniel Henrique... target/riscv/tcg: add 'zic64b' support
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Daniel Henrique... target/riscv: add zicbop extension flag
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Daniel Henrique... target/riscv: add rv64i CPU
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Daniel Henrique... target/riscv/tcg: update priv_ver on user_set extensions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Daniel Henrique... target/riscv/tcg: do not use "!generic" CPU checks
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Daniel Henrique... target/riscv: create TYPE_RISCV_VENDOR_CPU
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Heinrich Schuchardtdocs/system/riscv: document acpi parameter of virt...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Rob Bradforddisas/riscv: Add amocas.[w,d,q] instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Weiwei Litarget/riscv: Add support for Zacas extension
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Yong-Xuan Wanghw/riscv/virt.c: fix the interrupts-extended property...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Sunil V Lhw/riscv/virt-acpi-build.c: Add PLIC in MADT
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Sunil V Lhw/riscv/virt-acpi-build.c: Add IO controllers and...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Sunil V Lhw/riscv/virt: Update GPEX MMIO related properties
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Sunil V Lhw/pci-host/gpex: Define properties for MMIO ranges
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Sunil V Lhw/riscv/virt-acpi-build.c: Add MMU node in RHCT
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Sunil V Lhw/riscv/virt-acpi-build.c: Add CMO information in...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Sunil V Lhw/riscv/virt-acpi-build.c: Add APLIC in the MADT
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Sunil V Lhw/riscv/virt-acpi-build.c: Add IMSIC in the MADT
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Sunil V Lhw/riscv/virt-acpi-build.c: Add AIA support in RINTC
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Sunil V Lhw/riscv: virt: Make few IMSIC macros and functions...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Sunil V Lhw/i386/acpi-microvm.c: Use common function to add...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Sunil V Lhw/arm/virt-acpi-build.c: Migrate virtio creation to...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Sunil V Lhw/arm/virt-acpi-build.c: Migrate fw_cfg creation to...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Daniel Henrique... target/riscv/kvm: rename riscv_reg_id() to riscv_reg_id_ulong()
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Daniel Henrique... target/riscv/kvm: add RISCV_CONFIG_REG()
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Daniel Henrique... target/riscv/kvm: change timer regs size to u64
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Daniel Henrique... target/riscv/kvm: change KVM_REG_RISCV_FP_D to u64
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Daniel Henrique... target/riscv/kvm: change KVM_REG_RISCV_FP_F to u32
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Daniel Henrique... target/riscv/cpu.c: fix machine IDs getters
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Ivan Klokovtarget/riscv/pmp: Use hwaddr instead of target_ulong...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 LIU Zhiweitarget/riscv: Not allow write mstatus_vs without RVV
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 LIU Zhiweitarget/riscv: Fix th.dcache.cval1 priviledge check
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Max Choutarget/riscv: The whole vector register move instructions...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2024-01-10 Max Choutarget/riscv: Add vill check for whole vector register...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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AR7 emulation for QEMU