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target/riscv: rvv: Add tail agnostic for vector reduction instructions
2022-06-09 eopXDtarget/riscv: rvv: Add tail agnostic for vector reduction...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
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2022-06-09 eopXDtarget/riscv: rvv: Add tail agnostic for vector floating...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
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2022-06-09 eopXDtarget/riscv: rvv: Add tail agnostic for vector fix...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
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2022-06-09 eopXDtarget/riscv: rvv: Add tail agnostic for vector integer...
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2022-06-09 eopXDtarget/riscv: rvv: Add tail agnostic for vector integer...
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2022-06-09 eopXDtarget/riscv: rvv: Add tail agnostic for vector integer...
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2022-06-09 eopXDtarget/riscv: rvv: Add tail agnostic for vx, vvm, vxm...
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2022-06-09 eopXDtarget/riscv: rvv: Add tail agnostic for vector load...
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2022-06-09 eopXDtarget/riscv: rvv: Add tail agnostic for vv instructions
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2022-06-09 eopXDtarget/riscv: rvv: Early exit when vstart >= vl
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2022-06-09 eopXDtarget/riscv: rvv: Rename ambiguous esz
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2022-06-09 eopXDtarget/riscv: rvv: Prune redundant access_type parameter...
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2022-06-09 eopXDtarget/riscv: rvv: Prune redundant ESZ, DSZ parameter...
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2022-06-09 Frédéric Pétrottarget/riscv/debug.c: keep experimental rv128 support...
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2022-06-09 Andrew Brestickertarget/riscv: Wake on VS-level external interrupts
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2022-06-09 Jamie Ileshw/core/loader: return image sizes as ssize_t
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2022-06-09 Alistair Francishw/intc: sifive_plic: Avoid overflowing the addr_config...
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2022-06-09 Atish Patrahw/riscv: virt: Generate fw_cfg DT node correctly
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2022-06-09 Weiwei Litarget/riscv: add support for zmmul extension v0.1
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2022-06-09 Alistair FrancisMAINTAINERS: Cover hw/core/uboot_image.h within Generic...
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2022-05-24 Bin Menghw/core: loader: Set is_linux to true for VxWorks uImage
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2022-05-24 Bin Menghw/core: Sync uboot_image.h from U-Boot v2022.01
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2022-05-24 Hongren (Zenithal... target/riscv: add zicsr/zifencei to isa_string
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2022-05-24 Anup Patelhw/riscv: virt: Fix interrupt parent for dynamic platform...
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2022-05-24 Anup Pateltarget/riscv: Set [m|s]tval for both illegal and virtual...
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2022-05-24 Anup Pateltarget/riscv: Fix hstatus.GVA bit setting for traps...
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2022-05-24 Anup Pateltarget/riscv: Fix csr number based privilege checking
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2022-05-24 Frank Changtarget/riscv: Fix typo of mimpid cpu option
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2022-05-24 Weiwei Litarget/riscv: check 'I' and 'E' after checking 'G'...
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2022-05-24 Bernhard Beschowhw/riscv/sifive_u: Resolve redundant property accessors
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2022-05-24 Bernhard Beschowhw/vfio/pci-quirks: Resolve redundant property getters
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2022-05-24 Tsukasa OItarget/riscv: Move/refactor ISA extension checks
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2022-05-24 Tsukasa OItarget/riscv: FP extension requirements
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2022-05-24 Tsukasa OItarget/riscv: Change "G" expansion
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2022-05-24 Tsukasa OItarget/riscv: Disable "G" by default
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2022-05-24 Tsukasa OItarget/riscv: Fix coding style on "G" expansion
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2022-05-24 Tsukasa OIhw/riscv: Make CPU config error handling generous ...
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2022-05-24 Tsukasa OIhw/riscv: Make CPU config error handling generous ...
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2022-05-24 Tsukasa OItarget/riscv: Add short-isa-string option
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2022-05-23 Tsukasa OItarget/riscv: Move Zhinx* extensions on ISA string
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2022-05-23 Atish Patrahw/intc: Pass correct hartid while updating mtimecmp
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2022-05-23 eopXDtarget/riscv: rvv: Fix early exit condition for whole...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
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2022-05-23 Dylan Reidtarget/riscv: Fix VS mode hypervisor CSR access
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2022-04-29 Alistair Francishw/riscv: Enable TPM backends
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2022-04-29 Alistair Francishw/riscv: virt: Add device plug support
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2022-04-29 Alistair Francishw/riscv: virt: Add support for generating platform...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-29 Alistair Francishw/riscv: virt: Create a platform bus
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-29 Alistair Francishw/core: Move the ARM sysbus-fdt to core
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-29 Alistair Francishw/riscv: virt: Add a machine done notifier
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-29 Weiwei Litarget/riscv: add scalar crypto related extenstion...
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2022-04-29 Ralf Ramsauertarget/riscv: Fix incorrect PTE merge in walk_pte
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2022-04-29 Weiwei Litarget/riscv: rvk: expose zbk* and zk* properties
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-29 Weiwei Lidisas/riscv.c: rvk: add disas support for Zbk* and...
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2022-04-29 Weiwei Litarget/riscv: rvk: add CSR support for Zkr
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2022-04-29 Weiwei Litarget/riscv: rvk: add support for zksed/zksh extension
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-29 Weiwei Litarget/riscv: rvk: add support for sha512 related instructio...
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2022-04-29 Weiwei Litarget/riscv: rvk: add support for sha512 related instructio...
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2022-04-29 Weiwei Litarget/riscv: rvk: add support for sha256 related instructio...
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2022-04-29 Weiwei Litarget/riscv: rvk: add support for zkne/zknd extension...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-29 Weiwei Litarget/riscv: rvk: add support for zknd/zkne extension...
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2022-04-29 Weiwei Licrypto: move sm4_sbox from target/arm
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2022-04-29 Weiwei Litarget/riscv: rvk: add support for zbkx extension
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2022-04-29 Weiwei Litarget/riscv: rvk: add support for zbkc extension
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-29 Weiwei Litarget/riscv: rvk: add support for zbkb extension
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-29 Weiwei Litarget/riscv: rvk: add cfg properties for zbk* and zk*
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-29 Frank Changtarget/riscv: Support configuarable marchid, mvendorid...
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2022-04-29 Bin Menghw/riscv: Don't add empty bootargs to device tree
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-29 Bin Menghw/riscv: spike: Add '/chosen/stdout-path' in device...
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2022-04-22 Dylan Jhonghw/riscv: boot: Support 64bit fdt address.
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2022-04-22 Bin Menghw/core: tcg-cpu-ops.h: Update comments of debug_check_watch...
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2022-04-22 Bin Mengtarget/riscv: cpu: Enable native debug feature
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2022-04-22 Bin Mengtarget/riscv: machine: Add debug state description
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2022-04-22 Bin Mengtarget/riscv: csr: Hook debug CSR read/write
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2022-04-22 Bin Mengtarget/riscv: cpu: Add a config option for native debug
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2022-04-22 Bin Mengtarget/riscv: debug: Implement debug related TCGCPUOps
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2022-04-22 Jim Shuhw/intc: riscv_aclint: Add reset function of ACLINT...
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2022-04-22 Frank Changhw/intc: Make RISC-V ACLINT mtime MMIO register writable
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2022-04-22 Frank Changhw/intc: Support 32/64-bit mtimecmp and mtime accesses...
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2022-04-22 Frank Changhw/intc: Add .impl.[min|max]_access_size declaration...
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2022-04-22 Niklas Casselhw/riscv: virt: fix DT property mmu-type when CPU mmu...
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2022-04-22 Nicolas Pitretarget/riscv/pmp: fix NAPOT range computation overflow
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2022-04-22 Ralf Ramsauerhw/riscv: virt: Exit if the user provided -bios in...
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2022-04-22 Richard Hendersontarget/riscv: Use cpu_loop_exit_restore directly from...
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2022-04-22 Weiwei Litarget/riscv: fix start byte for vmv<nf>r.v when vstart...
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2022-04-22 Atish Patratarget/riscv: Add isa extenstion strings to the device...
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2022-04-22 Tsukasa OItarget/riscv: misa to ISA string conversion fix
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2022-04-22 Weiwei Litarget/riscv: optimize helper for vmv<nr>r.v
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2022-04-22 Weiwei Litarget/riscv: optimize condition assign for scale < 0
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2022-04-22 Bin Mengtarget/riscv: Add initial support for the Sdtrig extension
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-22 Alistair Francistarget/riscv: Allow software access to MIP SEIP
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-22 Alistair Francistarget/riscv: cpu: Fixup indentation
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-22 Atish Patratarget/riscv: Enable privileged spec version 1.12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-22 Atish Patratarget/riscv: Add *envcfg* CSRs support
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-22 Atish Patratarget/riscv: Add support for mconfigptr
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-22 Atish Patratarget/riscv: Introduce privilege version field in...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-22 Atish Patratarget/riscv: Add the privileged spec version 1.12.0
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-22 Atish Patratarget/riscv: Define simpler privileged spec version...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-22 Wilfred Mallawariscv: opentitan: Connect opentitan SPI Host
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-04-22 Wilfred Mallawahw/ssi: Add Ibex SPI device model
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2022-03-31 Yueh-Ting (eop)... target/riscv: rvv: Add missing early exit condition...
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AR7 emulation for QEMU