target/riscv: add support for zmmul extension v0.1
commitde799beba7f927b2a1ed38128309316511311605
authorWeiwei Li <liweiwei@iscas.ac.cn>
Tue, 31 May 2022 03:07:32 +0000 (31 11:07 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Thu, 9 Jun 2022 23:31:42 +0000 (10 09:31 +1000)
treee79a7d2de4039425364d0c5eede9a9d653e7d161
parentefe1592c43fe9b4053bf2987581a05736062a3cd
target/riscv: add support for zmmul extension v0.1

Add support for the zmmul extension v0.1. This extension includes all
multiplication operations from the M extension but not the divide ops.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: VĂ­ctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220531030732.3850-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.c
target/riscv/cpu.h
target/riscv/insn_trans/trans_rvm.c.inc