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target-mips: Correct MIPS16/microMIPS branch size calculation
2014-12-16
Maciej
W
.
Rozycki
target-mips: C
o
rrect MIPS1
6
/microMIPS branch size calculation
Signed-off-by: Maciej W. Rozycki <
macro@codesourcery.com
>
commit
|
commitdiff
|
tree
2014-12-16
Mac
i
e
j
W
.
Rozy
c
ki
target-mips: Restore the order
of helpers
Signed-off-by: Maciej W. Rozycki <
macro@codesourcery.com
>
commit
|
commitdiff
|
tree
2014-12-16
Maciej W
.
Rozycki
targ
e
t-mips: Remo
v
e unused `FL
O
A
T
_OP' mac
r
o
Signed-off-by: Maciej W. Rozycki <
macro@codesourcery.com
>
commit
|
commitdiff
|
tree
2014-12-16
Maciej W
.
Rozyck
i
target-mips: Make `helper_floa
t
_
cvtw_s' con
s
istent
.
.
.
Signed-off-by: Maciej W. Rozycki <
macro@codesourcery.com
>
commit
|
commitdiff
|
tree
2014-12-16
Macie
j
W
.
Rozycki
t
a
rget-mips:
Fix formatting in `decode_op
c
'
Signed-off-by: Maciej W. Rozycki <
macro@codesourcery.com
>
commit
|
commitdiff
|
tree
2014-12-16
Maci
e
j W
.
R
o
zycki
target-
m
ips: Fix forma
t
ting in `m
i
ps_defs'
Signed-off-by: Maciej W. Rozycki <
macro@codesourcery.com
>
commit
|
commitdiff
|
tree
2014-12-16
M
a
ciej W
.
R
ozycki
target-mi
p
s: Fix formatti
n
g in `decode_extended_mips16_
o
pc
'
Signed-off-by: Maciej W. Rozycki <
macro@codesourcery.com
>
commit
|
commitdiff
|
tree
2014-12-16
Maciej
W
.
Ro
z
ycki
ta
r
get-mips: E
n
able vect
o
r
ed interrupt support for
.
.
.
Signed-off-by: Maciej W. Rozycki <
macro@codesourcery.com
>
commit
|
commitdiff
|
tree
2014-12-16
Maciej W
.
Rozy
c
ki
target
-
mips: Add M
1
4K
a
nd
M
1
4Kc MIPS32
r
2 microMIPS
.
.
.
Signed-off-by: Maciej W. Rozycki <
macro@codesourcery.com
>
commit
|
commitdiff
|
tree
2014-12-16
M
a
ciej W
.
Rozycki
targe
t
-mips
:
Make CP0
.
Config4
a
nd CP0
.
Config5 registers
.
.
.
Signed-off-by: Maciej W. Rozycki <
macro@codesourcery.com
>
commit
|
commitdiff
|
tree
2014-12-16
Maciej W
.
Rozycki
target-mips: Add 5K
E
c and 5KEf
M
IP
S
64r2
p
r
ocessors
Signed-off-by: Maciej W. Rozycki <
macro@codesourcery.com
>
commit
|
commitdiff
|
tree
2014-12-16
Maciej W
.
Rozycki
t
arge
t
-m
i
ps: Make CP
1
.
FIR read-only here too
Signed-off-by: Maciej W. Rozycki <
macro@codesourcery.com
>
commit
|
commitdiff
|
tree
2014-12-16
Maci
e
j W
.
Ro
z
ycki
target-m
i
p
s
:
Cor
r
ect the han
d
li
n
g of regi
s
te
r
#72 on
.
.
.
Signed-off-by: Maciej W. Rozycki <
macro@codesourcery.com
>
commit
|
commitdiff
|
tree
2014-11-07
M
ac
i
e
j W
.
Rozycki
mips: Ensure PC u
p
d
a
te with MTC0
s
ingle-stepping
Signed-off-by: Maciej W. Rozycki <
macro@codesourcery.com
>
commit
|
commitdiff
|
tree
2014-11-07
Macie
j
W
.
Rozycki
mi
p
s:
Set t
h
e CP0
.
C
o
nfig3
.
DSP and CP0
.
Config3
.
DSP2P
.
.
.
Signed-off-by: Maciej W. Rozycki <
macro@codesourcery.com
>
commit
|
commitdiff
|
tree
2014-11-07
M
a
ciej W
.
Rozy
c
k
i
mips
:
Add macros
for CP0
.
Conf
i
g
3
and CP0
.
Config4 bits
Signed-off-by: Maciej W. Rozycki <
macro@codesourcery.com
>
commit
|
commitdiff
|
tree
2014-11-07
M
a
ciej W
.
Rozy
c
ki
mips: R
e
s
pect CP
0
.
Statu
s
.
CU
1
for mi
c
roMIPS FP b
r
anches
Signed-off-by: Maciej W. Rozycki <
macro@codesourcery.com
>
commit
|
commitdiff
|
tree
2014-11-07
Maciej W
.
Rozycki
mip
s
:
Remove CONFI
G
_VT82C686 from non-Fulong
configs
Signed-off-by: Maciej W. Rozycki <
macro@codesourcery.com
>
commit
|
commitdiff
|
tree
2012-09-07
Maciej W
.
Roz
y
cki
MIPS/us
e
r: Fi
x
r
e
set C
P
U state initi
a
lization
Signed-off-by: Maciej W. Rozycki <
macro@codesourcery.com
>
commit
|
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