| commit | e30614d51780f27c53b196da793c3fb89f1f620f | |
| author | Maciej W. Rozycki <macro@codesourcery.com> | |
| Tue, 4 Nov 2014 15:41:20 +0000 (4 15:41 +0000) | ||
| committer | Leon Alrae <leon.alrae@imgtec.com> | |
| Fri, 7 Nov 2014 14:15:28 +0000 (7 14:15 +0000) | ||
| tree | 149a5b040050a84557e270da2046955e0ea6b351 | treesnapshot (tar.gz zip) |
| parent | 70409e6726aa6ece565c8732f6c5cb5cd5879716 | commitdiff |
mips: Set the CP0.Config3.DSP and CP0.Config3.DSP2P bits
Set the CP0.Config3.DSP2P bit for the 74kf processor and both that bit
and the CP0.Config3.DSP bit for the artificial mips32r5-generic and
mips64dspr2 processors. They have the DSPr2 ASE enabled in `insn_flags'
and CPUs that implement that ASE need to have both CP0.Config3.DSP and
CP0.Config3.DSP2P set or software won't detect its presence.
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
[leon.alrae@imgtec.com: remove DSP flags from mips32r5-generic]
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Set the CP0.Config3.DSP2P bit for the 74kf processor and both that bit
and the CP0.Config3.DSP bit for the artificial mips32r5-generic and
mips64dspr2 processors. They have the DSPr2 ASE enabled in `insn_flags'
and CPUs that implement that ASE need to have both CP0.Config3.DSP and
CP0.Config3.DSP2P set or software won't detect its presence.
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
[leon.alrae@imgtec.com: remove DSP flags from mips32r5-generic]
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
| target-mips/translate_init.c | diffblobblamehistory |