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hw/char/ibex_uart: Make the register layout private
2021-06-24 Alistair Francishw/char/ibex_uart: Make the register layout private
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...0387a3ba2fad7d116a4986.1624001156.git.alistair.francis@wdc.com
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2021-06-24 Lukas Jüngerhw/char: QOMify sifive_uart
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-24 Lukas Jüngerhw/char: Consistent function names for sifive_uart
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-24 Bin Mengtarget/riscv: gdbstub: Fix dynamic CSR XML generation
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-24 Alistair Francistarget/riscv: Use target_ulong for the DisasContext...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...e3eec320b6a683ab56f705.1622435221.git.alistair.francis@wdc.com
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2021-06-07 Frank Changtarget/riscv: rvb: add b-ext version cpu option
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Kito Chengtarget/riscv: rvb: support and turn on B-extension...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Kito Chengtarget/riscv: rvb: add/shift with prefix zero-extend
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Kito Chengtarget/riscv: rvb: address calculation
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Frank Changtarget/riscv: rvb: generalized or-combine
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Frank Changtarget/riscv: rvb: generalized reverse
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Kito Chengtarget/riscv: rvb: rotate (left/right)
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Kito Chengtarget/riscv: rvb: shift ones
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Frank Changtarget/riscv: rvb: single-bit instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Frank Changtarget/riscv: add gen_shifti() and gen_shiftiw() helper...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Kito Chengtarget/riscv: rvb: sign-extend instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Kito Chengtarget/riscv: rvb: min/max instructions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Kito Chengtarget/riscv: rvb: pack two words into one register
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Kito Chengtarget/riscv: rvb: logic-with-negate
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Frank Changtarget/riscv: rvb: count bits set
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Kito Chengtarget/riscv: rvb: count leading/trailing zeros
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Kito Chengtarget/riscv: reformat @sh format encoding for B-extension
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 LIU Zhiweitarget/riscv: Pass the same value to oprsz and maxsz.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Alistair Francistarget/riscv/pmp: Add assert for ePMP operations
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...8c82fcb1f6805ee61dde82.1621550996.git.alistair.francis@wdc.com
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2021-06-07 Changbin Dutarget/riscv: Dump CSR mscratch/sscratch/satp
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Bin Mengtarget/riscv: Remove unnecessary riscv_*_names[] declaration
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Philippe Mathieu... target/riscv: Do not include 'pmp.h' in user emulation
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Alistair Francisdocs/system: Move the RISC-V -bios information to removed
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...bb8926d85fe1d35e48ea5b.1620081256.git.alistair.francis@wdc.com
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2021-06-07 Jose Martinstarget/riscv: fix wfi exception behavior
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Bin Menghw/riscv: microchip_pfsoc: Support direct kernel boot
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Bin Menghw/riscv: Use macros for BIOS image names
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Bin Mengdocs/system/riscv: sifive_u: Document '-dtb' usage
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Bin Mengdocs/system/riscv: Correct the indentation level of...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Bin Menghw/riscv: Support the official PLIC DT bindings
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Bin Menghw/riscv: Support the official CLINT DT bindings
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Bin Menghw/riscv: virt: Switch to use qemu_fdt_setprop_string_array...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-06-07 Bin Menghw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_ar...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Fix the RV64H decode comment
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...4b253512428c4baca7e4ba.1619234854.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Consolidate RV32/64 16-bit instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...ebf133c2cde6a7a37224d7.1619234854.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Consolidate RV32/64 32-bit instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...c6483ab973fe4791aefa77.1619234854.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Remove an unused CASE_OP_32_64 macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...0120c74ad892f60cec35ff.1619234854.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Remove the unused HSTATUS_WPRI macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...822958f04dfc732d7beb7e.1619234854.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Remove the hardcoded SATP_MODE macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...1739334198e36a64fe04df.1619234854.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Remove the hardcoded MSTATUS_SD macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...817c9dd6068dc36478fc53.1619234854.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Remove the hardcoded HGATP_MODE macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...265004b07de7489c77a766.1619234854.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Remove the hardcoded SSTATUS_SD macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...172790f5b5fc058b40f2f1.1619234854.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Remove the hardcoded RVXLEN macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...4f93cbc5d0acc31ed3344a.1619234854.git.alistair.francis@wdc.com
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2021-05-11 Emmanuel Blottarget/riscv: fix a typo with interrupt names
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Frank Changfpu/softfloat: set invalid excp flag for RISC-V muladd...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alexander Wagnerhw/riscv: Fix OT IBEX reset vector
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Emmanuel Blottarget/riscv: fix exception index on instruction access...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Frank Changtarget/riscv: fix vrgather macro index variable type bug
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Add ePMP support for the Ibex CPU
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...2e989dbe416e417a551fd1.1618812899.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv/pmp: Remove outdated comment
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...9a78fdba85280cab4dd27f.1618812899.git.alistair.francis@wdc.com
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2021-05-11 Hou Weiyingtarget/riscv: Add a config option for ePMP
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...35d3b323f966623f8af020.1618812899.git.alistair.francis@wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Hou Weiyingtarget/riscv: Implementation of enhanced PMP (ePMP)
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...4e7c98b168bdec5d297bb1.1618812899.git.alistair.francis@wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Hou Weiyingtarget/riscv: Add ePMP CSR access functions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...eeb99a774cf49f7da9cc32.1618812899.git.alistair.francis@wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Add the ePMP feature
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...c3ae009f5467e2b3960ce0.1618812899.git.alistair.francis@wdc.com
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2021-05-11 Hou Weiyingtarget/riscv: Define ePMP mseccfg
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...d4f930136d2d7fd7f99c78.1618812899.git.alistair.francis@wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francistarget/riscv: Fix the PMP is locked check when using TOR
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...89bd59c59990247265b0c6.1618812899.git.alistair.francis@wdc.com
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2021-05-11 Vijai Kumar Kdocs: Add documentation for shakti_c machine
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 LIU Zhiweitarget/riscv: Fixup saturate subtract function
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Jade Finkriscv: don't look at SUM when accessing memory from...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Alistair Francishw/riscv: Enable VIRTIO_VGA for RISC-V virt machine
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...0640f3233f8ad1ab270e1e.1617367317.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francishw/opentitan: Update the interrupt layout
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...10da2e9f23c414db5a6960.1617202791.git.alistair.francis@wdc.com
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2021-05-11 Alistair FrancisMAINTAINERS: Update the RISC-V CPU Maintainers
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...d28f43be69d8eb5cf4b56b.1617749142.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Use RISCVException enum for CSR access
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...11b351b5c9f43039ca8ea3.1617290165.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Use the RISCVException enum for CSR operations
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...ae8fc2429f906a459f17ce.1617290165.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Fix 32-bit HS mode access permissions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...ce3cf4f6622588f9c09149.1617290165.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Use the RISCVException enum for CSR predicates
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...5aa482adb2a558c02a7cad.1617290165.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Convert the RISC-V exceptions to an enum
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...e743a7c7f824d68879a527.1617290165.git.alistair.francis@wdc.com
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2021-05-11 Vijai Kumar Khw/riscv: Connect Shakti UART to Shakti platform
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Vijai Kumar Khw/char: Add Shakti UART emulation
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Vijai Kumar Kriscv: Add initial support for Shakti C machine
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Vijai Kumar Ktarget/riscv: Add Shakti C class CPU
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Bin Menghw/riscv: sifive_e: Add 'const' to sifive_e_memmap[]
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Dylan Jhongtarget/riscv: Align the data type of reset vector address
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Axel Heiderdocs/system/generic-loader.rst: Fix style
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-05-11 Atish Patratarget/riscv: Remove privilege v1.9 specific CSR related...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-23 Georg Kotheimertarget/riscv: Prevent lost illegal instruction exceptions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-23 Bin Mengdocs/system: riscv: Add documentation for 'microchip...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-23 Bin Menghw/riscv: microchip_pfsoc: Map EMMC/SD mux register
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-23 Bin Menghw/block: m25p80: Support fast read for SST flashes
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-23 Georg Kotheimertarget/riscv: Add proper two-stage lookup exception...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-23 Georg Kotheimertarget/riscv: Fix read and write accesses to vsip and...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-23 Asherah Connorhw/riscv: allow ramfb on virt
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2021-03-23 Asherah Connorhw/riscv: Add fw_cfg support to virt
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-23 Georg Kotheimertarget/riscv: Use background registers also for MSTATUS_MPV
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-23 Georg Kotheimertarget/riscv: Make VSTIP and VSEIP read-only in hip
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-23 Georg Kotheimertarget/riscv: Adjust privilege level for HLV(X)/HSV...
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2021-03-23 Jim Shutarget/riscv: flush TLB pages if PMP permission has...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-23 Jim Shutarget/riscv: add log of PMP permission checking
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-23 Jim Shutarget/riscv: propagate PMP permission to TLB page
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-23 Alexander Wagnerhw/char: disable ibex uart receive if the buffer is...
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2021-03-23 Frank Changtarget/riscv: fix vs() to return proper error code
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-04 Bin Menghw/riscv: virt: Map high mmio for PCIe
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-04 Bin Menghw/riscv: virt: Limit RAM size in a 32-bit system
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-04 Bin Menghw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init()
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-04 Bin Menghw/riscv: Drop 'struct MemmapEntry'
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2021-03-04 Alistair FrancisMAINTAINERS: Add a SiFive machine section
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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AR7 emulation for QEMU