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target/mips: Add emulation of MXU instruction D16MUL
2018-10-29
C
r
aig Janeczek
target
/
mips:
A
d
d emulation of MXU
i
nstruction D16MUL
Signed-off-by: Craig Janeczek <
jancraig@amazon.com
>
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2018-10-29
Craig Jan
e
cze
k
ta
r
get/mips: Ad
d
emulat
i
on of MXU
ins
t
ruction
S8LDD
Signed-off-by: Craig Janeczek <
jancraig@amazon.com
>
commit
|
commitdiff
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2018-10-29
Cr
a
ig Janeczek
target/mip
s
: Add
e
mu
l
ation of
M
XU instructions S32I
2
M
.
.
.
Signed-off-by: Craig Janeczek <
jancraig@amazon.com
>
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2018-10-29
Craig
J
aneczek
ta
r
get/mips: A
d
d emulatio
n
of no
n
-
MXU MUL
L
with
i
n
M
XU
.
.
.
Signed-off-by: Craig Janeczek <
jancraig@amazon.com
>
commit
|
commitdiff
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tree
2018-10-29
Craig Janecze
k
t
a
rget/mips: Add b
i
t
en
c
oding for
MXU operand get
t
ing
.
.
.
Signed-off-by: Craig Janeczek <
jancraig@amazon.com
>
commit
|
commitdiff
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2018-10-29
Craig J
a
n
ecz
e
k
targ
e
t/mips: Add bit
enco
d
i
ng f
o
r MXU o
p
erand getting
.
.
.
Signed-off-by: Craig Janeczek <
jancraig@amazon.com
>
commit
|
commitdiff
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tree
2018-10-29
Craig Ja
n
e
czek
target/mips
:
Ad
d
bit e
n
coding for
M
XU accumulate
add
.
.
.
Signed-off-by: Craig Janeczek <
jancraig@amazon.com
>
commit
|
commitdiff
|
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2018-10-29
Cra
i
g Janecze
k
target/mips: Define a bit f
o
r
M
XU in insn_
f
lags
Signed-off-by: Craig Janeczek <
jancraig@amazon.com
>
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|
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2018-10-29
Craig
J
a
necze
k
target/m
i
ps:
Introduce MXU registers
Signed-off-by: Craig Janeczek <
jancraig@amazon.com
>
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