| commit | eb5559f67dc8dc12335dd996877bb6daaea32eb2 | |
| author | Craig Janeczek <jancraig@amazon.com> | |
| Thu, 18 Oct 2018 12:06:20 +0000 (18 14:06 +0200) | ||
| committer | Aleksandar Markovic <amarkovic@wavecomp.com> | |
| Mon, 29 Oct 2018 13:13:47 +0000 (29 14:13 +0100) | ||
| tree | 1ff6313e427506de0f1bd03068a88c2b20c832e0 | treesnapshot (tar.gz zip) |
| parent | 2431a422d325c1832d77dd64fa3135ec303b00de | commitdiff |
target/mips: Introduce MXU registers
Define and initialize the 16 MXU registers - 15 general computational
register, and 1 control register). There is also a zero register, but
it does not have any corresponding variable.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Craig Janeczek <jancraig@amazon.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Define and initialize the 16 MXU registers - 15 general computational
register, and 1 control register). There is also a zero register, but
it does not have any corresponding variable.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Craig Janeczek <jancraig@amazon.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
| target/mips/cpu.h | diffblobblamehistory | |
| target/mips/translate.c | diffblobblamehistory |