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target/riscv: zfh: half-precision floating-point classify
2021-12-20
K
i
t
o
Cheng
target/riscv: zfh
:
half-precision floating-poi
n
t classif
y
Signed-off-by:
Kito Cheng
<kito.cheng@sifive.com>
commit
|
commitdiff
|
tree
2021-12-20
Kito
C
heng
tar
g
et/riscv: zfh
:
half-precision flo
a
ting-
p
oint compar
e
Signed-off-by:
Kito Cheng
<kito.cheng@sifive.com>
commit
|
commitdiff
|
tree
2021-12-20
Kito Cheng
target/riscv: zfh:
h
alf
-
prec
i
sion c
o
nve
r
t an
d
move
Signed-off-by:
Kito Cheng
<kito.cheng@sifive.com>
commit
|
commitdiff
|
tree
2021-12-20
Kito C
h
en
g
target/risc
v
: zfh: half-precision computati
o
nal
Signed-off-by:
Kito Cheng
<kito.cheng@sifive.com>
commit
|
commitdiff
|
tree
2021-12-20
Kito Cheng
t
a
rget/r
i
scv: zfh
:
half-precision load
a
nd stor
e
Signed-off-by:
Kito Cheng
<kito.cheng@sifive.com>
commit
|
commitdiff
|
tree
2021-07-07
K
i
to Cheng
linux-
u
ser/elfload: Imp
l
ement ELF_HW
C
AP for RI
S
C-V
Signed-off-by:
Kito Cheng
<kito.cheng@sifive.com>
commit
|
commitdiff
|
tree
2021-06-07
Kit
o
Cheng
targe
t
/
r
iscv:
r
vb: support
a
nd turn on
B
-extension
.
.
.
Signed-off-by:
Kito Cheng
<kito.cheng@sifive.com>
commit
|
commitdiff
|
tree
2021-06-07
Kito Cheng
t
a
rget/ris
c
v:
rvb: add/
s
hift with pr
e
fix zero-extend
Signed-off-by:
Kito Cheng
<kito.cheng@sifive.com>
commit
|
commitdiff
|
tree
2021-06-07
Kito Cheng
target/riscv: rvb: address
calculation
Signed-off-by:
Kito Cheng
<kito.cheng@sifive.com>
commit
|
commitdiff
|
tree
2021-06-07
Kit
o
Cheng
target/riscv
:
rvb
:
rotate (le
f
t
/ri
g
ht
)
Signed-off-by:
Kito Cheng
<kito.cheng@sifive.com>
commit
|
commitdiff
|
tree
2021-06-07
K
i
t
o
Che
n
g
tar
g
et/risc
v
:
rvb:
shift
o
nes
Signed-off-by:
Kito Cheng
<kito.cheng@sifive.com>
commit
|
commitdiff
|
tree
2021-06-07
Kit
o
Ch
e
ng
tar
g
et
/
riscv: rv
b
: sign-extend instr
u
ctions
Signed-off-by:
Kito Cheng
<kito.cheng@sifive.com>
commit
|
commitdiff
|
tree
2021-06-07
Kito Chen
g
t
arget/riscv: rvb
:
m
i
n/m
a
x
i
nstruc
t
io
n
s
Signed-off-by:
Kito Cheng
<kito.cheng@sifive.com>
commit
|
commitdiff
|
tree
2021-06-07
Kito C
h
eng
target/risc
v
: r
v
b: pack two words into on
e
re
g
iste
r
Signed-off-by:
Kito Cheng
<kito.cheng@sifive.com>
commit
|
commitdiff
|
tree
2021-06-07
Kito Cheng
t
arget/ri
s
cv: r
v
b:
l
o
g
ic-with-negate
Signed-off-by:
Kito Cheng
<kito.cheng@sifive.com>
commit
|
commitdiff
|
tree
2021-06-07
Ki
t
o
Cheng
t
arget/r
i
scv: rvb: cou
n
t
l
e
adi
n
g/trailing zer
o
s
Signed-off-by:
Kito Cheng
<kito.cheng@sifive.com>
commit
|
commitdiff
|
tree
2021-06-07
Kito Cheng
target/riscv: reformat @sh format enc
o
ding
f
o
r B-ex
t
ension
Signed-off-by:
Kito Cheng
<kito.cheng@sifive.com>
commit
|
commitdiff
|
tree
2021-05-15
K
i
to Chen
g
l
i
n
ux-use
r
:
A
dd
stra
c
e supp
o
rt for pri
n
tin
g
arg
u
me
n
ts
.
.
.
Signed-off-by:
Kito Cheng
<kito.cheng@sifive.com>
commit
|
commitdiff
|
tree
2021-01-18
Kito C
h
eng
riscv: Add semihosting support for user mode
Signed-off-by:
Kito Cheng
<kito.cheng@sifive.com>
commit
|
commitdiff
|
tree
2020-08-28
Ki
t
o Cheng
so
f
tfl
o
at: I
m
plement th
e
full se
t
of comp
a
r
i
so
n
s
for
.
.
.
Signed-off-by:
Kito Cheng
<kito.cheng@sifive.com>
commit
|
commitdiff
|
tree
2019-03-26
Kito Cheng
target/riscv: Fix wrong expandi
n
g for
c
.
fswsp
Signed-off-by:
Kito Cheng
<kito.cheng@gmail.com>
commit
|
commitdiff
|
tree
2019-03-25
Kito Cheng
h
ar
d
float:
f
ix float3
2
/
6
4 fused multiply-add
Signed-off-by:
Kito Cheng
<kito.cheng@gmail.com>
commit
|
commitdiff
|
tree
2019-03-19
Kito Cheng
RISC-V: linux-
u
ser support f
o
r
R
VE ABI
Co-authored-by:
Kito Cheng
<kito.cheng@gmail.com>
commit
|
commitdiff
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tree
