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target-mips: Fix DisasContext's ulri member initialization
2014-12-16 Maciej W. Rozyckitarget-mips: Fix DisasContext's ulri member initialization
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
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2014-12-16 Maciej W. Rozyckitarget-mips: Use local float status pointer across...
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
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2014-12-16 Maciej W. Rozyckitarget-mips: Add missing calls to synchronise SoftFloat...
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
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2014-12-16 Maciej W. Rozyckilinux-user: Use the 5KEf processor for 64-bit emulation
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
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2014-12-16 Maciej W. Rozyckitarget-mips: Also apply the CP0.Status mask to MTTC0
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
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2014-12-16 Maciej W. Rozyckitarget-mips: gdbstub: Clean up FPU register handling
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
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2014-12-16 Maciej W. Rozyckitarget-mips: Correct 32-bit address space wrapping
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
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2014-12-16 Maciej W. Rozyckitarget-mips: Tighten ISA level checks
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
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2014-12-16 Maciej W. Rozyckitarget-mips: Fix CP0.Config3.ISAOnExc write accesses
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
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2014-12-16 Maciej W. Rozyckitarget-mips: Output CP0.Config2-5 in the register dump
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
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2014-12-16 Maciej W. Rozyckitarget-mips: Fix the 64-bit case for microMIPS MOVE16...
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
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2014-12-16 Maciej W. Rozyckitarget-mips: Correct the writes to Status and Cause...
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
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2014-12-16 Maciej W. Rozyckitarget-mips: Correct the handling of writes to CP0...
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
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2014-12-16 Maciej W. Rozyckitarget-mips: Correct MIPS16/microMIPS branch size calculation
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
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2014-12-16 Maciej W. Rozyckitarget-mips: Restore the order of helpers
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
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2014-12-16 Maciej W. Rozyckitarget-mips: Remove unused `FLOAT_OP' macro
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
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2014-12-16 Maciej W. Rozyckitarget-mips: Make `helper_float_cvtw_s' consistent...
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
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2014-12-16 Maciej W. Rozyckitarget-mips: Fix formatting in `decode_opc'
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
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2014-12-16 Maciej W. Rozyckitarget-mips: Fix formatting in `mips_defs'
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
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2014-12-16 Maciej W. Rozyckitarget-mips: Fix formatting in `decode_extended_mips16_opc'
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
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2014-12-16 Maciej W. Rozyckitarget-mips: Enable vectored interrupt support for...
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
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2014-12-16 Maciej W. Rozyckitarget-mips: Add M14K and M14Kc MIPS32r2 microMIPS...
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
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2014-12-16 Maciej W. Rozyckitarget-mips: Make CP0.Config4 and CP0.Config5 registers...
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
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2014-12-16 Maciej W. Rozyckitarget-mips: Add 5KEc and 5KEf MIPS64r2 processors
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
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2014-12-16 Maciej W. Rozyckitarget-mips: Make CP1.FIR read-only here too
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
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2014-12-16 Maciej W. Rozyckitarget-mips: Correct the handling of register #72 on...
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
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2014-11-07 Maciej W. Rozyckimips: Ensure PC update with MTC0 single-stepping
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
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2014-11-07 Maciej W. Rozyckimips: Set the CP0.Config3.DSP and CP0.Config3.DSP2P...
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
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2014-11-07 Maciej W. Rozyckimips: Add macros for CP0.Config3 and CP0.Config4 bits
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
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2014-11-07 Maciej W. Rozyckimips: Respect CP0.Status.CU1 for microMIPS FP branches
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
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2014-11-07 Maciej W. Rozyckimips: Remove CONFIG_VT82C686 from non-Fulong configs
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
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2012-09-07 Maciej W. RozyckiMIPS/user: Fix reset CPU state initialization
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
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AR7 emulation for QEMU