| 2019-03-26 | Kito Cheng | target/riscv: Fix wrong expanding for c.fswsp Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-03-22 | Palmer Dabbelt | target/riscv: Zero extend the inputs of divuw and remuw Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-03-19 | Bin Meng | riscv: sifive_u: Correct UART0's IRQ in the device... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-03-19 | Bin Meng | riscv: sifive_uart: Generate TX interrupt Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-03-19 | Alistair Francis | target/riscv: Remove unused struct Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-03-19 | Alistair Francis | riscv: sifive_u: Allow up to 4 CPUs to be created Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-03-19 | Michael Clark | RISC-V: Update load reservation comment in do_interrupt Cc: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-03-19 | Michael Clark | RISC-V: Convert trap debugging to trace events Cc: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-03-19 | Michael Clark | RISC-V: Add support for vectored interrupts Cc: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-03-19 | Michael Clark | RISC-V: Change local interrupts from edge to level Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-03-19 | Kito Cheng | RISC-V: linux-user support for RVE ABI Cc: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-03-19 | Michael Clark | elf: Add RISC-V PSABI ELF header defines Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-03-19 | Michael Clark | RISC-V: Remove unnecessary disassembler constraints Cc: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-03-19 | Michael Clark | RISC-V: Allow interrupt controllers to claim interrupts Cc: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-03-19 | Michael Clark | RISC-V: Replace __builtin_popcount with ctpop8 in PLIC Cc: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-03-19 | Alistair Francis | riscv: pmp: Log pmp access errors as guest errors Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-03-19 | Jim Wilson | RISC-V: Add hooks to use the gdb xml files. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-03-19 | Jim Wilson | RISC-V: Add debug support for accessing CSRs. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-03-19 | Jim Wilson | RISC-V: Fixes to CSR_* register macros. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-03-19 | Jim Wilson | RISC-V: Add 64-bit gdb xml files. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-03-19 | Jim Wilson | RISC-V: Add 32-bit gdb xml files. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-03-18 | Bastian Koppelmann | target/riscv: Fix manually parsed 16 bit insn Tested-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-02-11 | Alistair Francis | riscv: Ensure the kernel start address is correctly... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-02-11 | Xi Wang | target/riscv: fix counter-enable checks in ctr() Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-02-11 | Palmer Dabbelt | MAINTAINERS: Remove Michael Clark as a RISC-V Maintainer Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-02-11 | Michael Clark | RISC-V: Add misa runtime write support Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-02-11 | Michael Clark | RISC-V: Add misa.MAFD checks to translate Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-02-11 | Michael Clark | RISC-V: Add misa to DisasContext Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-02-11 | Alistair Francis | RISC-V: Add priv_ver to DisasContext Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-02-11 | Michael Clark | RISC-V: Use riscv prefix consistently on cpu helpers Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-02-11 | Michael Clark | RISC-V: Implement mstatus.TSR/TW/TVM Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-02-11 | Richard Henderson | RISC-V: Mark mstatus.fs dirty Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-02-11 | Richard Henderson | RISC-V: Split out mstatus_fs from tb_flags Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-01-10 | Alistair Francis | default-configs: Enable USB support for RISC-V machines Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-01-09 | Michael Clark | RISC-V: Implement existential predicates for CSRs Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-01-09 | Michael Clark | RISC-V: Implement atomic mip/sip CSR updates Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2019-01-08 | Michael Clark | RISC-V: Implement modular CSR helper interface Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-12-21 | Palmer Dabbelt | MAINTAINERS: Mark RISC-V as Supported Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-12-20 | Mao Zhongyi | riscv/cpu: use device_class_set_parent_realize Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-12-20 | Anup Patel | target/riscv/pmp.c: Fix pmp_decode_napot() Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-12-20 | Nathaniel Graff | sifive_uart: Implement interrupt pending register Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-12-20 | Michael Clark | RISC-V: Enable second UART on sifive_e and sifive_u Cc: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-12-20 | Michael Clark | RISC-V: Fix PLIC pending bitfield reads Cc: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-12-20 | Michael Clark | RISC-V: Fix CLINT timecmp low 32-bit writes Cc: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-12-20 | Michael Clark | RISC-V: Add hartid and \n to interrupt logging Cc: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-12-20 | Anup Patel | sifive_u: Set 'clock-frequency' DT property for SiFive... Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-12-20 | Anup Patel | sifive_u: Add clock DT node for GEM ethernet Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-12-20 | Alistair Francis | riscv: Enable VGA and PCIE_VGA Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-12-20 | Alistair Francis | hw/riscv/virt: Connect the gpex PCIe Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-12-20 | Alistair Francis | hw/riscv/virt: Adjust memory layout spacing Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-12-20 | Alistair Francis | hw/riscv/virt: Increase the number of interrupts Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-11-13 | Palmer Dabbelt | RISC-V: Respect fences for user-only emulators Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-11-13 | Bastian Koppelmann | target/riscv: Fix sfence.vm/a both available in any... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-11-13 | Bastian Koppelmann | target/riscv: Fix FCLASS_D being treated as RV64 only Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-11-13 | Alistair Francis | hw/riscv/virt: Free the test device tree node name Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-11-08 | Alistair Francis | riscv: spike: Fix memory leak in the board init Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-10-30 | Palmer Dabbelt | Add qemu-riscv@nongnu.org as the RISC-V list Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-10-30 | Palmer Dabbelt | Add Alistair as a RISC-V Maintainer Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-10-30 | Dayeol Lee | target/riscv/pmp.c: pmpcfg_csr_read returns bogus value... Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-10-17 | Michael Clark | RISC-V: Don't add NULL bootargs to device-tree Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-10-17 | Michael Clark | RISC-V: Add missing free for plic_hart_config Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-10-17 | Michael Clark | RISC-V: Update CSR and interrupt definitions Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-10-17 | Michael Clark | RISC-V: Move non-ops from op_helper to cpu_helper Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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| 2018-10-17 | Michael Clark | RISC-V: Allow setting and clearing multiple irqs Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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