| commit | e6488eeba89e559f284a40aeafde347d7d0a86a8 | |
| author | Cédric Le Goater <clg@kaod.org> | |
| Fri, 15 Nov 2019 16:24:15 +0000 (15 17:24 +0100) | ||
| committer | David Gibson <david@gibson.dropbear.id.au> | |
| Mon, 16 Dec 2019 23:39:47 +0000 (17 10:39 +1100) | ||
| tree | 7405f260f58c5867a5e89d4d41cc5b0f0743e29c | treesnapshot (tar.gz zip) |
| parent | 516883c2f15bdd844543be218155898d06953c90 | commitdiff |
ppc/xive: Introduce helpers for the NVT id
Each vCPU in the system is identified with an NVT identifier which is
pushed in the OS CAM line (QW1W2) of the HW thread interrupt context
register when the vCPU is dispatched on a HW thread. This identifier
is used by the presenter subengine to find a matching target to notify
of an event. It is also used to fetch the associate NVT structure
which may contain pending interrupts that need a resend.
Add a couple of helpers for the NVT ids. The NVT space is 19 bits
wide, giving a maximum of 512K per chip.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191115162436.30548-3-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Each vCPU in the system is identified with an NVT identifier which is
pushed in the OS CAM line (QW1W2) of the HW thread interrupt context
register when the vCPU is dispatched on a HW thread. This identifier
is used by the presenter subengine to find a matching target to notify
of an event. It is also used to fetch the associate NVT structure
which may contain pending interrupts that need a resend.
Add a couple of helpers for the NVT ids. The NVT space is 19 bits
wide, giving a maximum of 512K per chip.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191115162436.30548-3-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| include/hw/ppc/xive.h | diffblobblamehistory | |
| include/hw/ppc/xive_regs.h | diffblobblamehistory |