| commit | 516883c2f15bdd844543be218155898d06953c90 | |
| author | Cédric Le Goater <clg@kaod.org> | |
| Fri, 15 Nov 2019 16:24:14 +0000 (15 17:24 +0100) | ||
| committer | David Gibson <david@gibson.dropbear.id.au> | |
| Mon, 16 Dec 2019 23:39:47 +0000 (17 10:39 +1100) | ||
| tree | 9d913306625dcdce1555674dd5d456ddd4f58b09 | treesnapshot (tar.gz zip) |
| parent | 95bd61c4dfc4c08d4248071f2f70d9c2afacc0d1 | commitdiff |
ppc/xive: Record the IPB in the associated NVT
When an interrupt can not be presented to a vCPU, because it is not
running on any of the HW treads, the XIVE presenter updates the
Interrupt Pending Buffer register of the associated XIVE NVT
structure. This is only done if backlog is activated in the END but
this is generally the case.
The current code assumes that the fields of the NVT structure is
architected with the same layout of the thread interrupt context
registers. Fix this assumption and define an offset for the IPB
register backup value in the NVT.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191115162436.30548-2-clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
When an interrupt can not be presented to a vCPU, because it is not
running on any of the HW treads, the XIVE presenter updates the
Interrupt Pending Buffer register of the associated XIVE NVT
structure. This is only done if backlog is activated in the END but
this is generally the case.
The current code assumes that the fields of the NVT structure is
architected with the same layout of the thread interrupt context
registers. Fix this assumption and define an offset for the IPB
register backup value in the NVT.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191115162436.30548-2-clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| hw/intc/xive.c | diffblobblamehistory | |
| include/hw/ppc/xive_regs.h | diffblobblamehistory |