| commit | d0bec217ee0f6c948ba4579ca0f43a1a3f346cb4 | |
| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | |
| Mon, 12 Oct 2020 09:57:53 +0000 (12 11:57 +0200) | ||
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | |
| Sat, 17 Oct 2020 09:13:15 +0000 (17 11:13 +0200) | ||
| tree | 2b7642eba94be8849c9089d67fe97200cbd42812 | treesnapshot (tar.gz zip) |
| parent | 68b981aa76079216f5765a6aecaf8728f27d3696 | commitdiff |
target/mips/cpu: Make cp0_count_rate a property
Since not all CPU implementations use a cores use a CP0 timer
at half the frequency of the CPU, make this variable a property.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201012095804.3335117-11-f4bug@amsat.org>
Since not all CPU implementations use a cores use a CP0 timer
at half the frequency of the CPU, make this variable a property.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201012095804.3335117-11-f4bug@amsat.org>
| target/mips/cpu.c | diffblobblamehistory | |
| target/mips/cpu.h | diffblobblamehistory |