| commit | 68b981aa76079216f5765a6aecaf8728f27d3696 | |
| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | |
| Mon, 12 Oct 2020 09:57:52 +0000 (12 11:57 +0200) | ||
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | |
| Sat, 17 Oct 2020 09:13:15 +0000 (17 11:13 +0200) | ||
| tree | 51e21fb183ef004f55767fc8c8e57ab72b77dbd3 | treesnapshot (tar.gz zip) |
| parent | d225b5122029c3d6293aab6e2d0a05597fc92ba4 | commitdiff |
target/mips/cpu: Calculate the CP0 timer period using the CPU frequency
The CP0 timer period is a function of the CPU frequency.
Start using the default values, which will be replaced by
properties in the next commits.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201012095804.3335117-10-f4bug@amsat.org>
The CP0 timer period is a function of the CPU frequency.
Start using the default values, which will be replaced by
properties in the next commits.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201012095804.3335117-10-f4bug@amsat.org>
| target/mips/cpu.c | diffblobblamehistory |