| commit | d225b5122029c3d6293aab6e2d0a05597fc92ba4 | |
| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | |
| Mon, 12 Oct 2020 09:57:51 +0000 (12 11:57 +0200) | ||
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | |
| Sat, 17 Oct 2020 09:13:15 +0000 (17 11:13 +0200) | ||
| tree | c2f16e1f4469854dd70cace1ade25b293a825e04 | treesnapshot (tar.gz zip) |
| parent | 8dadffc01700f79fd66db972fff3a93a594715ee | commitdiff |
target/mips: Move cp0_count_ns to CPUMIPSState
Currently the CP0 timer period is fixed at 10 ns, corresponding
to a fixed CPU frequency of 200 MHz (using half the speed of the
CPU).
In few commits we will be able to use a different CPU frequency.
In preparation, move the cp0_count_ns variable to CPUMIPSState
so we can modify it.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201012095804.3335117-9-f4bug@amsat.org>
Currently the CP0 timer period is fixed at 10 ns, corresponding
to a fixed CPU frequency of 200 MHz (using half the speed of the
CPU).
In few commits we will be able to use a different CPU frequency.
In preparation, move the cp0_count_ns variable to CPUMIPSState
so we can modify it.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201012095804.3335117-9-f4bug@amsat.org>
| target/mips/cp0_timer.c | diffblobblamehistory | |
| target/mips/cpu.c | diffblobblamehistory | |
| target/mips/cpu.h | diffblobblamehistory |