Public Git Hosting - qemu/ar7.git/commit

commit	cf327449816d5643106445420a0b06b0f38d4f01
author	Stephen Long <steplong@quicinc.com>
	Tue, 25 May 2021 01:03:11 +0000 (24 18:03 -0700)
committer	Peter Maydell <peter.maydell@linaro.org>
	Tue, 25 May 2021 15:01:44 +0000 (25 16:01 +0100)
tree	1ef6dd26d40de7e162a99b6a408b4d778b90a2e8	tree \| snapshot (tar.gz zip)
parent	6ebca45faffd697a045f1d54800d00c6f77c5eb9	commit \| diff

target/arm: Implement SVE2 gather load insns

Add decoding logic for SVE2 64-bit/32-bit gather non-temporal
load insns.

64-bit
* LDNT1SB
* LDNT1B (vector plus scalar)
* LDNT1SH
* LDNT1H (vector plus scalar)
* LDNT1SW
* LDNT1W (vector plus scalar)
* LDNT1D (vector plus scalar)

32-bit
* LDNT1SB
* LDNT1B (vector plus scalar)
* LDNT1SH
* LDNT1H (vector plus scalar)
* LDNT1W (vector plus scalar)

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-46-richard.henderson@linaro.org
Message-Id: <20200422152343.12493-1-steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

target/arm/sve.decode		diff \| blob \| blame \| history
target/arm/translate-sve.c		diff \| blob \| blame \| history