| commit | 6ebca45faffd697a045f1d54800d00c6f77c5eb9 | |
| author | Stephen Long <steplong@quicinc.com> | |
| Tue, 25 May 2021 01:03:10 +0000 (24 18:03 -0700) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Tue, 25 May 2021 15:01:44 +0000 (25 16:01 +0100) | ||
| tree | 099b683084abf6f4d52c0c6787720b415be01c79 | treesnapshot (tar.gz zip) |
| parent | e6eba6e532a5f19519d925c8f68da032537abcac | commitdiff |
target/arm: Implement SVE2 scatter store insns
Add decoding logic for SVE2 64-bit/32-bit scatter non-temporal
store insns.
64-bit
* STNT1B (vector plus scalar)
* STNT1H (vector plus scalar)
* STNT1W (vector plus scalar)
* STNT1D (vector plus scalar)
32-bit
* STNT1B (vector plus scalar)
* STNT1H (vector plus scalar)
* STNT1W (vector plus scalar)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-45-richard.henderson@linaro.org
Message-Id: <20200422141553.8037-1-steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Add decoding logic for SVE2 64-bit/32-bit scatter non-temporal
store insns.
64-bit
* STNT1B (vector plus scalar)
* STNT1H (vector plus scalar)
* STNT1W (vector plus scalar)
* STNT1D (vector plus scalar)
32-bit
* STNT1B (vector plus scalar)
* STNT1H (vector plus scalar)
* STNT1W (vector plus scalar)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-45-richard.henderson@linaro.org
Message-Id: <20200422141553.8037-1-steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| target/arm/sve.decode | diffblobblamehistory | |
| target/arm/translate-sve.c | diffblobblamehistory |