| commit | e6eba6e532a5f19519d925c8f68da032537abcac | |
| author | Richard Henderson <richard.henderson@linaro.org> | |
| Tue, 25 May 2021 01:03:09 +0000 (24 18:03 -0700) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Tue, 25 May 2021 15:01:44 +0000 (25 16:01 +0100) | ||
| tree | 1b948454d2264b3ee6594809241084480753ef98 | treesnapshot (tar.gz zip) |
| parent | 7d47ac94a7c15e820d41adda4cf706c2001e675c | commitdiff |
target/arm: Implement SVE2 XAR
In addition, use the same vector generator interface for AdvSIMD.
This fixes a bug in which the AdvSIMD insn failed to clear the
high bits of the SVE register.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-44-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
In addition, use the same vector generator interface for AdvSIMD.
This fixes a bug in which the AdvSIMD insn failed to clear the
high bits of the SVE register.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-44-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>