| commit | ccf628b7939c542cf9e46e9aaa2b0acf0888ec52 | |
| author | Richard Henderson <richard.henderson@linaro.org> | |
| Thu, 20 Aug 2020 05:44:49 +0000 (19 22:44 -0700) | ||
| committer | Richard Henderson <richard.henderson@linaro.org> | |
| Tue, 1 Sep 2020 14:41:38 +0000 (1 07:41 -0700) | ||
| tree | 9135f99a9d9a74d7af7bd5872e3f155cdd641074 | treesnapshot (tar.gz zip) |
| parent | 86017ccfbd2b39371bd47dd7d2bed69ee184c3e5 | commitdiff |
target/microblaze: Fix width of BTR
The branch target register is only 32-bits wide. Do not use a
64-bit type to represent it. Since cpu_btr is only used during
MSR and MTR instructions, we can just as easily use an explicit
load and store, so eliminate the variable.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
The branch target register is only 32-bits wide. Do not use a
64-bit type to represent it. Since cpu_btr is only used during
MSR and MTR instructions, we can just as easily use an explicit
load and store, so eliminate the variable.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| target/microblaze/cpu.h | diffblobblamehistory | |
| target/microblaze/translate.c | diffblobblamehistory |