| commit | 86017ccfbd2b39371bd47dd7d2bed69ee184c3e5 | |
| author | Richard Henderson <richard.henderson@linaro.org> | |
| Thu, 20 Aug 2020 05:40:23 +0000 (19 22:40 -0700) | ||
| committer | Richard Henderson <richard.henderson@linaro.org> | |
| Tue, 1 Sep 2020 14:41:38 +0000 (1 07:41 -0700) | ||
| tree | 8ad0692956642fab346c78636d4a771d77460809 | treesnapshot (tar.gz zip) |
| parent | 6efd55995a224787baa712500b82ef21a148d38e | commitdiff |
target/microblaze: Fix width of FSR
The exception status register is only 32-bits wide. Do not use a
64-bit type to represent it. Since cpu_fsr is only used during
MSR and MTR instructions, we can just as easily use an explicit
load and store, so eliminate the variable.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
The exception status register is only 32-bits wide. Do not use a
64-bit type to represent it. Since cpu_fsr is only used during
MSR and MTR instructions, we can just as easily use an explicit
load and store, so eliminate the variable.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| target/microblaze/cpu.h | diffblobblamehistory | |
| target/microblaze/translate.c | diffblobblamehistory |