| commit | 9c72b68ad746a51f63822cffab4d144b5957823a | |
| author | Peter Maydell <peter.maydell@linaro.org> | |
| Fri, 1 Feb 2019 14:55:44 +0000 (1 14:55 +0000) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Fri, 1 Feb 2019 14:55:44 +0000 (1 14:55 +0000) | ||
| tree | 80fed61e3cc2efc83413ddfe5a7a0a308d17fd50 | treesnapshot (tar.gz zip) |
| parent | e1f220811dbd5d85fb02ff286358f9ee6188938f | commitdiff |
target/arm/translate-a64: Don't underdecode SIMD ld/st single
In the AdvSIMD load/store single structure encodings, the
non-post-indexed case should have zeroes in [20:16] (which is the
Rm field for the post-indexed case). Bit 31 must also be zero
(a check we got right in ldst_multiple but not here). Correctly
UNDEF these unallocated encodings.
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20190125182626.9221-5-peter.maydell@linaro.org
In the AdvSIMD load/store single structure encodings, the
non-post-indexed case should have zeroes in [20:16] (which is the
Rm field for the post-indexed case). Bit 31 must also be zero
(a check we got right in ldst_multiple but not here). Correctly
UNDEF these unallocated encodings.
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20190125182626.9221-5-peter.maydell@linaro.org
| target/arm/translate-a64.c | diffblobblamehistory |