| commit | e1f220811dbd5d85fb02ff286358f9ee6188938f | |
| author | Peter Maydell <peter.maydell@linaro.org> | |
| Fri, 1 Feb 2019 14:55:44 +0000 (1 14:55 +0000) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Fri, 1 Feb 2019 14:55:44 +0000 (1 14:55 +0000) | ||
| tree | 8a5fd70fcce087c4c4e849f461e521aebf2bedbc | treesnapshot (tar.gz zip) |
| parent | a80c4256543987ca88407349ee012a673a10a2ae | commitdiff |
target/arm/translate-a64: Don't underdecode SIMD ld/st multiple
In the AdvSIMD load/store multiple structures encodings,
the non-post-indexed case should have zeroes in [20:16]
(which is the Rm field for the post-indexed case).
Correctly UNDEF the currently unallocated encodings which
have non-zeroes in those bits.
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20190125182626.9221-4-peter.maydell@linaro.org
In the AdvSIMD load/store multiple structures encodings,
the non-post-indexed case should have zeroes in [20:16]
(which is the Rm field for the post-indexed case).
Correctly UNDEF the currently unallocated encodings which
have non-zeroes in those bits.
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20190125182626.9221-4-peter.maydell@linaro.org
| target/arm/translate-a64.c | diffblobblamehistory |