target/mips: Fix gen_mxu_s32ldd_s32lddr
commit92ecfab50ee2b30e60c774f96f05fc38714874f1
authorRichard Henderson <richard.henderson@linaro.org>
Sun, 13 Jun 2021 23:27:13 +0000 (13 16:27 -0700)
committerRichard Henderson <richard.henderson@linaro.org>
Tue, 29 Jun 2021 17:04:57 +0000 (29 10:04 -0700)
tree07407b0c1a10d8abaa3c1ac8ccd90d3f27a30a23
parentb983a0e17240fcbc8e1a32ef44221a1954332c81
target/mips: Fix gen_mxu_s32ldd_s32lddr

There were two bugs here: (1) the required endianness was
not present in the MemOp, and (2) we were not providing a
zero-extended input to the bswap as semantics required.

The best fix is to fold the bswap into the memory operation,
producing the desired result directly.

Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
target/mips/tcg/mxu_translate.c