| commit | 6da4433fc5fa8aff1096cc651c8d313c70ee6f4d | |
| author | Cédric Le Goater <clg@kaod.org> | |
| Mon, 1 Jul 2019 16:26:17 +0000 (1 17:26 +0100) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Mon, 1 Jul 2019 16:28:59 +0000 (1 17:28 +0100) | ||
| tree | 0ffaad3157d8abb9216a61ca5996a5d95ac38bd7 | treesnapshot (tar.gz zip) |
| parent | ad1a9782186d0ed1c02eb008f268d34599a54a42 | commitdiff |
aspeed/smc: add a 'sdram_base' property
The DRAM address of a DMA transaction depends on the DRAM base address
of the SoC. Inform the SMC controller model with this value.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20190618165311.27066-15-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
The DRAM address of a DMA transaction depends on the DRAM base address
of the SoC. Inform the SMC controller model with this value.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20190618165311.27066-15-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| hw/arm/aspeed_soc.c | diffblobblamehistory | |
| hw/ssi/aspeed_smc.c | diffblobblamehistory | |
| include/hw/ssi/aspeed_smc.h | diffblobblamehistory |