| commit | ad1a9782186d0ed1c02eb008f268d34599a54a42 | |
| author | Cédric Le Goater <clg@kaod.org> | |
| Mon, 1 Jul 2019 16:26:17 +0000 (1 17:26 +0100) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Mon, 1 Jul 2019 16:28:59 +0000 (1 17:28 +0100) | ||
| tree | f6e3e89a842f1fecf657f8a2bced0c47856a0951 | treesnapshot (tar.gz zip) |
| parent | 026498a8f19fec9cbdc7dd3857d53b794be02e2e | commitdiff |
aspeed: add a RAM memory region container
The RAM memory region is defined after the SoC is realized when the
SDMC controller has checked that the defined RAM size for the machine
is correct. This is problematic for controller models requiring a link
on the RAM region, for DMA support in the SMC controller for instance.
Introduce a container memory region for the RAM that we can link into
the controllers early, before the SoC is realized. It will be
populated with the RAM region after the checks have be done.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-id: 20190618165311.27066-14-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
The RAM memory region is defined after the SoC is realized when the
SDMC controller has checked that the defined RAM size for the machine
is correct. This is problematic for controller models requiring a link
on the RAM region, for DMA support in the SMC controller for instance.
Introduce a container memory region for the RAM that we can link into
the controllers early, before the SoC is realized. It will be
populated with the RAM region after the checks have be done.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-id: 20190618165311.27066-14-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| hw/arm/aspeed.c | diffblobblamehistory |