| commit | 01a112e2e9f8c969b3d190e1fd2faf24644a771c | |
| author | Richard Henderson <richard.henderson@linaro.org> | |
| Mon, 3 Apr 2023 22:25:06 +0000 (4 01:25 +0300) | ||
| committer | Richard Henderson <richard.henderson@linaro.org> | |
| Thu, 11 May 2023 08:53:41 +0000 (11 09:53 +0100) | ||
| tree | dda7b08077739134f9077d4ae69006825498a33d | treesnapshot (tar.gz zip) |
| parent | f48cc9020b6a1b41f7ccc639a09fecc5a6b42ad1 | commitdiff |
tcg/ppc: Reorg tcg_out_tlb_read
Allocate TCG_REG_TMP2. Use R0, TMP1, TMP2 instead of any of
the normally allocated registers for the tlb load.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Allocate TCG_REG_TMP2. Use R0, TMP1, TMP2 instead of any of
the normally allocated registers for the tlb load.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| tcg/ppc/tcg-target.c.inc | diffblobblamehistory |