?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
ARM: KVM: Check KVM_CAP_ARM_IRQ_LINE_LAYOUT_2 for smp_cpus > 256
[qemu/ar7.git] / target / mips / msa_helper.c
bloba2052baa57c164d6c17faa795f40793fe6302b31
1 /*
2 * MIPS SIMD Architecture Module Instruction emulation helpers for QEMU.
3 *
4 * Copyright (c) 2014 Imagination Technologies
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "cpu.h"
22 #include "internal.h"
23 #include "exec/exec-all.h"
24 #include "exec/helper-proto.h"
25 #include "fpu/softfloat.h"
26
27 /* Data format min and max values */
28 #define DF_BITS(df) (1 << ((df) + 3))
29
30 #define DF_MAX_INT(df) (int64_t)((1LL << (DF_BITS(df) - 1)) - 1)
31 #define M_MAX_INT(m) (int64_t)((1LL << ((m) - 1)) - 1)
32
33 #define DF_MIN_INT(df) (int64_t)(-(1LL << (DF_BITS(df) - 1)))
34 #define M_MIN_INT(m) (int64_t)(-(1LL << ((m) - 1)))
35
36 #define DF_MAX_UINT(df) (uint64_t)(-1ULL >> (64 - DF_BITS(df)))
37 #define M_MAX_UINT(m) (uint64_t)(-1ULL >> (64 - (m)))
38
39 #define UNSIGNED(x, df) ((x) & DF_MAX_UINT(df))
40 #define SIGNED(x, df) \
41 ((((int64_t)x) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df)))
42
43 /* Element-by-element access macros */
44 #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
45
46
47
48 /*
49 * Bit Count
50 * ---------
51 *
52 * +---------------+----------------------------------------------------------+
53 * | NLOC.B | Vector Leading Ones Count (byte) |
54 * | NLOC.H | Vector Leading Ones Count (halfword) |
55 * | NLOC.W | Vector Leading Ones Count (word) |
56 * | NLOC.D | Vector Leading Ones Count (doubleword) |
57 * | NLZC.B | Vector Leading Zeros Count (byte) |
58 * | NLZC.H | Vector Leading Zeros Count (halfword) |
59 * | NLZC.W | Vector Leading Zeros Count (word) |
60 * | NLZC.D | Vector Leading Zeros Count (doubleword) |
61 * | PCNT.B | Vector Population Count (byte) |
62 * | PCNT.H | Vector Population Count (halfword) |
63 * | PCNT.W | Vector Population Count (word) |
64 * | PCNT.D | Vector Population Count (doubleword) |
65 * +---------------+----------------------------------------------------------+
66 */
67
68 static inline int64_t msa_nlzc_df(uint32_t df, int64_t arg)
69 {
70 uint64_t x, y;
71 int n, c;
72
73 x = UNSIGNED(arg, df);
74 n = DF_BITS(df);
75 c = DF_BITS(df) / 2;
76
77 do {
78 y = x >> c;
79 if (y != 0) {
80 n = n - c;
81 x = y;
82 }
83 c = c >> 1;
84 } while (c != 0);
85
86 return n - x;
87 }
88
89 static inline int64_t msa_nloc_df(uint32_t df, int64_t arg)
90 {
91 return msa_nlzc_df(df, UNSIGNED((~arg), df));
92 }
93
94 void helper_msa_nloc_b(CPUMIPSState *env, uint32_t wd, uint32_t ws)
95 {
96 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
97 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
98
99 pwd->b[0] = msa_nloc_df(DF_BYTE, pws->b[0]);
100 pwd->b[1] = msa_nloc_df(DF_BYTE, pws->b[1]);
101 pwd->b[2] = msa_nloc_df(DF_BYTE, pws->b[2]);
102 pwd->b[3] = msa_nloc_df(DF_BYTE, pws->b[3]);
103 pwd->b[4] = msa_nloc_df(DF_BYTE, pws->b[4]);
104 pwd->b[5] = msa_nloc_df(DF_BYTE, pws->b[5]);
105 pwd->b[6] = msa_nloc_df(DF_BYTE, pws->b[6]);
106 pwd->b[7] = msa_nloc_df(DF_BYTE, pws->b[7]);
107 pwd->b[8] = msa_nloc_df(DF_BYTE, pws->b[8]);
108 pwd->b[9] = msa_nloc_df(DF_BYTE, pws->b[9]);
109 pwd->b[10] = msa_nloc_df(DF_BYTE, pws->b[10]);
110 pwd->b[11] = msa_nloc_df(DF_BYTE, pws->b[11]);
111 pwd->b[12] = msa_nloc_df(DF_BYTE, pws->b[12]);
112 pwd->b[13] = msa_nloc_df(DF_BYTE, pws->b[13]);
113 pwd->b[14] = msa_nloc_df(DF_BYTE, pws->b[14]);
114 pwd->b[15] = msa_nloc_df(DF_BYTE, pws->b[15]);
115 }
116
117 void helper_msa_nloc_h(CPUMIPSState *env, uint32_t wd, uint32_t ws)
118 {
119 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
120 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
121
122 pwd->h[0] = msa_nloc_df(DF_HALF, pws->h[0]);
123 pwd->h[1] = msa_nloc_df(DF_HALF, pws->h[1]);
124 pwd->h[2] = msa_nloc_df(DF_HALF, pws->h[2]);
125 pwd->h[3] = msa_nloc_df(DF_HALF, pws->h[3]);
126 pwd->h[4] = msa_nloc_df(DF_HALF, pws->h[4]);
127 pwd->h[5] = msa_nloc_df(DF_HALF, pws->h[5]);
128 pwd->h[6] = msa_nloc_df(DF_HALF, pws->h[6]);
129 pwd->h[7] = msa_nloc_df(DF_HALF, pws->h[7]);
130 }
131
132 void helper_msa_nloc_w(CPUMIPSState *env, uint32_t wd, uint32_t ws)
133 {
134 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
135 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
136
137 pwd->w[0] = msa_nloc_df(DF_WORD, pws->w[0]);
138 pwd->w[1] = msa_nloc_df(DF_WORD, pws->w[1]);
139 pwd->w[2] = msa_nloc_df(DF_WORD, pws->w[2]);
140 pwd->w[3] = msa_nloc_df(DF_WORD, pws->w[3]);
141 }
142
143 void helper_msa_nloc_d(CPUMIPSState *env, uint32_t wd, uint32_t ws)
144 {
145 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
146 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
147
148 pwd->d[0] = msa_nloc_df(DF_DOUBLE, pws->d[0]);
149 pwd->d[1] = msa_nloc_df(DF_DOUBLE, pws->d[1]);
150 }
151
152 void helper_msa_nlzc_b(CPUMIPSState *env, uint32_t wd, uint32_t ws)
153 {
154 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
155 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
156
157 pwd->b[0] = msa_nlzc_df(DF_BYTE, pws->b[0]);
158 pwd->b[1] = msa_nlzc_df(DF_BYTE, pws->b[1]);
159 pwd->b[2] = msa_nlzc_df(DF_BYTE, pws->b[2]);
160 pwd->b[3] = msa_nlzc_df(DF_BYTE, pws->b[3]);
161 pwd->b[4] = msa_nlzc_df(DF_BYTE, pws->b[4]);
162 pwd->b[5] = msa_nlzc_df(DF_BYTE, pws->b[5]);
163 pwd->b[6] = msa_nlzc_df(DF_BYTE, pws->b[6]);
164 pwd->b[7] = msa_nlzc_df(DF_BYTE, pws->b[7]);
165 pwd->b[8] = msa_nlzc_df(DF_BYTE, pws->b[8]);
166 pwd->b[9] = msa_nlzc_df(DF_BYTE, pws->b[9]);
167 pwd->b[10] = msa_nlzc_df(DF_BYTE, pws->b[10]);
168 pwd->b[11] = msa_nlzc_df(DF_BYTE, pws->b[11]);
169 pwd->b[12] = msa_nlzc_df(DF_BYTE, pws->b[12]);
170 pwd->b[13] = msa_nlzc_df(DF_BYTE, pws->b[13]);
171 pwd->b[14] = msa_nlzc_df(DF_BYTE, pws->b[14]);
172 pwd->b[15] = msa_nlzc_df(DF_BYTE, pws->b[15]);
173 }
174
175 void helper_msa_nlzc_h(CPUMIPSState *env, uint32_t wd, uint32_t ws)
176 {
177 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
178 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
179
180 pwd->h[0] = msa_nlzc_df(DF_HALF, pws->h[0]);
181 pwd->h[1] = msa_nlzc_df(DF_HALF, pws->h[1]);
182 pwd->h[2] = msa_nlzc_df(DF_HALF, pws->h[2]);
183 pwd->h[3] = msa_nlzc_df(DF_HALF, pws->h[3]);
184 pwd->h[4] = msa_nlzc_df(DF_HALF, pws->h[4]);
185 pwd->h[5] = msa_nlzc_df(DF_HALF, pws->h[5]);
186 pwd->h[6] = msa_nlzc_df(DF_HALF, pws->h[6]);
187 pwd->h[7] = msa_nlzc_df(DF_HALF, pws->h[7]);
188 }
189
190 void helper_msa_nlzc_w(CPUMIPSState *env, uint32_t wd, uint32_t ws)
191 {
192 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
193 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
194
195 pwd->w[0] = msa_nlzc_df(DF_WORD, pws->w[0]);
196 pwd->w[1] = msa_nlzc_df(DF_WORD, pws->w[1]);
197 pwd->w[2] = msa_nlzc_df(DF_WORD, pws->w[2]);
198 pwd->w[3] = msa_nlzc_df(DF_WORD, pws->w[3]);
199 }
200
201 void helper_msa_nlzc_d(CPUMIPSState *env, uint32_t wd, uint32_t ws)
202 {
203 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
204 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
205
206 pwd->d[0] = msa_nlzc_df(DF_DOUBLE, pws->d[0]);
207 pwd->d[1] = msa_nlzc_df(DF_DOUBLE, pws->d[1]);
208 }
209
210 static inline int64_t msa_pcnt_df(uint32_t df, int64_t arg)
211 {
212 uint64_t x;
213
214 x = UNSIGNED(arg, df);
215
216 x = (x & 0x5555555555555555ULL) + ((x >> 1) & 0x5555555555555555ULL);
217 x = (x & 0x3333333333333333ULL) + ((x >> 2) & 0x3333333333333333ULL);
218 x = (x & 0x0F0F0F0F0F0F0F0FULL) + ((x >> 4) & 0x0F0F0F0F0F0F0F0FULL);
219 x = (x & 0x00FF00FF00FF00FFULL) + ((x >> 8) & 0x00FF00FF00FF00FFULL);
220 x = (x & 0x0000FFFF0000FFFFULL) + ((x >> 16) & 0x0000FFFF0000FFFFULL);
221 x = (x & 0x00000000FFFFFFFFULL) + ((x >> 32));
222
223 return x;
224 }
225
226 void helper_msa_pcnt_b(CPUMIPSState *env, uint32_t wd, uint32_t ws)
227 {
228 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
229 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
230
231 pwd->b[0] = msa_pcnt_df(DF_BYTE, pws->b[0]);
232 pwd->b[1] = msa_pcnt_df(DF_BYTE, pws->b[1]);
233 pwd->b[2] = msa_pcnt_df(DF_BYTE, pws->b[2]);
234 pwd->b[3] = msa_pcnt_df(DF_BYTE, pws->b[3]);
235 pwd->b[4] = msa_pcnt_df(DF_BYTE, pws->b[4]);
236 pwd->b[5] = msa_pcnt_df(DF_BYTE, pws->b[5]);
237 pwd->b[6] = msa_pcnt_df(DF_BYTE, pws->b[6]);
238 pwd->b[7] = msa_pcnt_df(DF_BYTE, pws->b[7]);
239 pwd->b[8] = msa_pcnt_df(DF_BYTE, pws->b[8]);
240 pwd->b[9] = msa_pcnt_df(DF_BYTE, pws->b[9]);
241 pwd->b[10] = msa_pcnt_df(DF_BYTE, pws->b[10]);
242 pwd->b[11] = msa_pcnt_df(DF_BYTE, pws->b[11]);
243 pwd->b[12] = msa_pcnt_df(DF_BYTE, pws->b[12]);
244 pwd->b[13] = msa_pcnt_df(DF_BYTE, pws->b[13]);
245 pwd->b[14] = msa_pcnt_df(DF_BYTE, pws->b[14]);
246 pwd->b[15] = msa_pcnt_df(DF_BYTE, pws->b[15]);
247 }
248
249 void helper_msa_pcnt_h(CPUMIPSState *env, uint32_t wd, uint32_t ws)
250 {
251 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
252 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
253
254 pwd->h[0] = msa_pcnt_df(DF_HALF, pws->h[0]);
255 pwd->h[1] = msa_pcnt_df(DF_HALF, pws->h[1]);
256 pwd->h[2] = msa_pcnt_df(DF_HALF, pws->h[2]);
257 pwd->h[3] = msa_pcnt_df(DF_HALF, pws->h[3]);
258 pwd->h[4] = msa_pcnt_df(DF_HALF, pws->h[4]);
259 pwd->h[5] = msa_pcnt_df(DF_HALF, pws->h[5]);
260 pwd->h[6] = msa_pcnt_df(DF_HALF, pws->h[6]);
261 pwd->h[7] = msa_pcnt_df(DF_HALF, pws->h[7]);
262 }
263
264 void helper_msa_pcnt_w(CPUMIPSState *env, uint32_t wd, uint32_t ws)
265 {
266 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
267 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
268
269 pwd->w[0] = msa_pcnt_df(DF_WORD, pws->w[0]);
270 pwd->w[1] = msa_pcnt_df(DF_WORD, pws->w[1]);
271 pwd->w[2] = msa_pcnt_df(DF_WORD, pws->w[2]);
272 pwd->w[3] = msa_pcnt_df(DF_WORD, pws->w[3]);
273 }
274
275 void helper_msa_pcnt_d(CPUMIPSState *env, uint32_t wd, uint32_t ws)
276 {
277 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
278 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
279
280 pwd->d[0] = msa_pcnt_df(DF_DOUBLE, pws->d[0]);
281 pwd->d[1] = msa_pcnt_df(DF_DOUBLE, pws->d[1]);
282 }
283
284
285 /*
286 * Bit Move
287 * --------
288 *
289 * +---------------+----------------------------------------------------------+
290 * | BINSL.B | Vector Bit Insert Left (byte) |
291 * | BINSL.H | Vector Bit Insert Left (halfword) |
292 * | BINSL.W | Vector Bit Insert Left (word) |
293 * | BINSL.D | Vector Bit Insert Left (doubleword) |
294 * | BINSR.B | Vector Bit Insert Right (byte) |
295 * | BINSR.H | Vector Bit Insert Right (halfword) |
296 * | BINSR.W | Vector Bit Insert Right (word) |
297 * | BINSR.D | Vector Bit Insert Right (doubleword) |
298 * | BMNZ.V | Vector Bit Move If Not Zero |
299 * | BMZ.V | Vector Bit Move If Zero |
300 * | BSEL.V | Vector Bit Select |
301 * +---------------+----------------------------------------------------------+
302 */
303
304 /* Data format bit position and unsigned values */
305 #define BIT_POSITION(x, df) ((uint64_t)(x) % DF_BITS(df))
306
307 static inline int64_t msa_binsl_df(uint32_t df,
308 int64_t dest, int64_t arg1, int64_t arg2)
309 {
310 uint64_t u_arg1 = UNSIGNED(arg1, df);
311 uint64_t u_dest = UNSIGNED(dest, df);
312 int32_t sh_d = BIT_POSITION(arg2, df) + 1;
313 int32_t sh_a = DF_BITS(df) - sh_d;
314 if (sh_d == DF_BITS(df)) {
315 return u_arg1;
316 } else {
317 return UNSIGNED(UNSIGNED(u_dest << sh_d, df) >> sh_d, df) |
318 UNSIGNED(UNSIGNED(u_arg1 >> sh_a, df) << sh_a, df);
319 }
320 }
321
322 void helper_msa_binsl_b(CPUMIPSState *env,
323 uint32_t wd, uint32_t ws, uint32_t wt)
324 {
325 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
326 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
327 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
328
329 pwd->b[0] = msa_binsl_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[0]);
330 pwd->b[1] = msa_binsl_df(DF_BYTE, pwd->b[1], pws->b[1], pwt->b[1]);
331 pwd->b[2] = msa_binsl_df(DF_BYTE, pwd->b[2], pws->b[2], pwt->b[2]);
332 pwd->b[3] = msa_binsl_df(DF_BYTE, pwd->b[3], pws->b[3], pwt->b[3]);
333 pwd->b[4] = msa_binsl_df(DF_BYTE, pwd->b[4], pws->b[4], pwt->b[4]);
334 pwd->b[5] = msa_binsl_df(DF_BYTE, pwd->b[5], pws->b[5], pwt->b[5]);
335 pwd->b[6] = msa_binsl_df(DF_BYTE, pwd->b[6], pws->b[6], pwt->b[6]);
336 pwd->b[7] = msa_binsl_df(DF_BYTE, pwd->b[7], pws->b[7], pwt->b[7]);
337 pwd->b[8] = msa_binsl_df(DF_BYTE, pwd->b[8], pws->b[8], pwt->b[8]);
338 pwd->b[9] = msa_binsl_df(DF_BYTE, pwd->b[9], pws->b[9], pwt->b[9]);
339 pwd->b[10] = msa_binsl_df(DF_BYTE, pwd->b[10], pws->b[10], pwt->b[10]);
340 pwd->b[11] = msa_binsl_df(DF_BYTE, pwd->b[11], pws->b[11], pwt->b[11]);
341 pwd->b[12] = msa_binsl_df(DF_BYTE, pwd->b[12], pws->b[12], pwt->b[12]);
342 pwd->b[13] = msa_binsl_df(DF_BYTE, pwd->b[13], pws->b[13], pwt->b[13]);
343 pwd->b[14] = msa_binsl_df(DF_BYTE, pwd->b[14], pws->b[14], pwt->b[14]);
344 pwd->b[15] = msa_binsl_df(DF_BYTE, pwd->b[15], pws->b[15], pwt->b[15]);
345 }
346
347 void helper_msa_binsl_h(CPUMIPSState *env,
348 uint32_t wd, uint32_t ws, uint32_t wt)
349 {
350 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
351 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
352 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
353
354 pwd->h[0] = msa_binsl_df(DF_HALF, pwd->h[0], pws->h[0], pwt->h[0]);
355 pwd->h[1] = msa_binsl_df(DF_HALF, pwd->h[1], pws->h[1], pwt->h[1]);
356 pwd->h[2] = msa_binsl_df(DF_HALF, pwd->h[2], pws->h[2], pwt->h[2]);
357 pwd->h[3] = msa_binsl_df(DF_HALF, pwd->h[3], pws->h[3], pwt->h[3]);
358 pwd->h[4] = msa_binsl_df(DF_HALF, pwd->h[4], pws->h[4], pwt->h[4]);
359 pwd->h[5] = msa_binsl_df(DF_HALF, pwd->h[5], pws->h[5], pwt->h[5]);
360 pwd->h[6] = msa_binsl_df(DF_HALF, pwd->h[6], pws->h[6], pwt->h[6]);
361 pwd->h[7] = msa_binsl_df(DF_HALF, pwd->h[7], pws->h[7], pwt->h[7]);
362 }
363
364 void helper_msa_binsl_w(CPUMIPSState *env,
365 uint32_t wd, uint32_t ws, uint32_t wt)
366 {
367 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
368 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
369 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
370
371 pwd->w[0] = msa_binsl_df(DF_WORD, pwd->w[0], pws->w[0], pwt->w[0]);
372 pwd->w[1] = msa_binsl_df(DF_WORD, pwd->w[1], pws->w[1], pwt->w[1]);
373 pwd->w[2] = msa_binsl_df(DF_WORD, pwd->w[2], pws->w[2], pwt->w[2]);
374 pwd->w[3] = msa_binsl_df(DF_WORD, pwd->w[3], pws->w[3], pwt->w[3]);
375 }
376
377 void helper_msa_binsl_d(CPUMIPSState *env,
378 uint32_t wd, uint32_t ws, uint32_t wt)
379 {
380 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
381 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
382 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
383
384 pwd->d[0] = msa_binsl_df(DF_DOUBLE, pwd->d[0], pws->d[0], pwt->d[0]);
385 pwd->d[1] = msa_binsl_df(DF_DOUBLE, pwd->d[1], pws->d[1], pwt->d[1]);
386 }
387
388 static inline int64_t msa_binsr_df(uint32_t df,
389 int64_t dest, int64_t arg1, int64_t arg2)
390 {
391 uint64_t u_arg1 = UNSIGNED(arg1, df);
392 uint64_t u_dest = UNSIGNED(dest, df);
393 int32_t sh_d = BIT_POSITION(arg2, df) + 1;
394 int32_t sh_a = DF_BITS(df) - sh_d;
395 if (sh_d == DF_BITS(df)) {
396 return u_arg1;
397 } else {
398 return UNSIGNED(UNSIGNED(u_dest >> sh_d, df) << sh_d, df) |
399 UNSIGNED(UNSIGNED(u_arg1 << sh_a, df) >> sh_a, df);
400 }
401 }
402
403 void helper_msa_binsr_b(CPUMIPSState *env,
404 uint32_t wd, uint32_t ws, uint32_t wt)
405 {
406 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
407 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
408 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
409
410 pwd->b[0] = msa_binsr_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[0]);
411 pwd->b[1] = msa_binsr_df(DF_BYTE, pwd->b[1], pws->b[1], pwt->b[1]);
412 pwd->b[2] = msa_binsr_df(DF_BYTE, pwd->b[2], pws->b[2], pwt->b[2]);
413 pwd->b[3] = msa_binsr_df(DF_BYTE, pwd->b[3], pws->b[3], pwt->b[3]);
414 pwd->b[4] = msa_binsr_df(DF_BYTE, pwd->b[4], pws->b[4], pwt->b[4]);
415 pwd->b[5] = msa_binsr_df(DF_BYTE, pwd->b[5], pws->b[5], pwt->b[5]);
416 pwd->b[6] = msa_binsr_df(DF_BYTE, pwd->b[6], pws->b[6], pwt->b[6]);
417 pwd->b[7] = msa_binsr_df(DF_BYTE, pwd->b[7], pws->b[7], pwt->b[7]);
418 pwd->b[8] = msa_binsr_df(DF_BYTE, pwd->b[8], pws->b[8], pwt->b[8]);
419 pwd->b[9] = msa_binsr_df(DF_BYTE, pwd->b[9], pws->b[9], pwt->b[9]);
420 pwd->b[10] = msa_binsr_df(DF_BYTE, pwd->b[10], pws->b[10], pwt->b[10]);
421 pwd->b[11] = msa_binsr_df(DF_BYTE, pwd->b[11], pws->b[11], pwt->b[11]);
422 pwd->b[12] = msa_binsr_df(DF_BYTE, pwd->b[12], pws->b[12], pwt->b[12]);
423 pwd->b[13] = msa_binsr_df(DF_BYTE, pwd->b[13], pws->b[13], pwt->b[13]);
424 pwd->b[14] = msa_binsr_df(DF_BYTE, pwd->b[14], pws->b[14], pwt->b[14]);
425 pwd->b[15] = msa_binsr_df(DF_BYTE, pwd->b[15], pws->b[15], pwt->b[15]);
426 }
427
428 void helper_msa_binsr_h(CPUMIPSState *env,
429 uint32_t wd, uint32_t ws, uint32_t wt)
430 {
431 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
432 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
433 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
434
435 pwd->h[0] = msa_binsr_df(DF_HALF, pwd->h[0], pws->h[0], pwt->h[0]);
436 pwd->h[1] = msa_binsr_df(DF_HALF, pwd->h[1], pws->h[1], pwt->h[1]);
437 pwd->h[2] = msa_binsr_df(DF_HALF, pwd->h[2], pws->h[2], pwt->h[2]);
438 pwd->h[3] = msa_binsr_df(DF_HALF, pwd->h[3], pws->h[3], pwt->h[3]);
439 pwd->h[4] = msa_binsr_df(DF_HALF, pwd->h[4], pws->h[4], pwt->h[4]);
440 pwd->h[5] = msa_binsr_df(DF_HALF, pwd->h[5], pws->h[5], pwt->h[5]);
441 pwd->h[6] = msa_binsr_df(DF_HALF, pwd->h[6], pws->h[6], pwt->h[6]);
442 pwd->h[7] = msa_binsr_df(DF_HALF, pwd->h[7], pws->h[7], pwt->h[7]);
443 }
444
445 void helper_msa_binsr_w(CPUMIPSState *env,
446 uint32_t wd, uint32_t ws, uint32_t wt)
447 {
448 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
449 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
450 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
451
452 pwd->w[0] = msa_binsr_df(DF_WORD, pwd->w[0], pws->w[0], pwt->w[0]);
453 pwd->w[1] = msa_binsr_df(DF_WORD, pwd->w[1], pws->w[1], pwt->w[1]);
454 pwd->w[2] = msa_binsr_df(DF_WORD, pwd->w[2], pws->w[2], pwt->w[2]);
455 pwd->w[3] = msa_binsr_df(DF_WORD, pwd->w[3], pws->w[3], pwt->w[3]);
456 }
457
458 void helper_msa_binsr_d(CPUMIPSState *env,
459 uint32_t wd, uint32_t ws, uint32_t wt)
460 {
461 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
462 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
463 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
464
465 pwd->d[0] = msa_binsr_df(DF_DOUBLE, pwd->d[0], pws->d[0], pwt->d[0]);
466 pwd->d[1] = msa_binsr_df(DF_DOUBLE, pwd->d[1], pws->d[1], pwt->d[1]);
467 }
468
469 void helper_msa_bmnz_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
470 {
471 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
472 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
473 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
474
475 pwd->d[0] = UNSIGNED( \
476 ((pwd->d[0] & (~pwt->d[0])) | (pws->d[0] & pwt->d[0])), DF_DOUBLE);
477 pwd->d[1] = UNSIGNED( \
478 ((pwd->d[1] & (~pwt->d[1])) | (pws->d[1] & pwt->d[1])), DF_DOUBLE);
479 }
480
481 void helper_msa_bmz_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
482 {
483 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
484 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
485 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
486
487 pwd->d[0] = UNSIGNED( \
488 ((pwd->d[0] & pwt->d[0]) | (pws->d[0] & (~pwt->d[0]))), DF_DOUBLE);
489 pwd->d[1] = UNSIGNED( \
490 ((pwd->d[1] & pwt->d[1]) | (pws->d[1] & (~pwt->d[1]))), DF_DOUBLE);
491 }
492
493 void helper_msa_bsel_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
494 {
495 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
496 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
497 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
498
499 pwd->d[0] = UNSIGNED( \
500 (pws->d[0] & (~pwd->d[0])) | (pwt->d[0] & pwd->d[0]), DF_DOUBLE);
501 pwd->d[1] = UNSIGNED( \
502 (pws->d[1] & (~pwd->d[1])) | (pwt->d[1] & pwd->d[1]), DF_DOUBLE);
503 }
504
505
506 /*
507 * Bit Set
508 * -------
509 *
510 * +---------------+----------------------------------------------------------+
511 * | BCLR.B | Vector Bit Clear (byte) |
512 * | BCLR.H | Vector Bit Clear (halfword) |
513 * | BCLR.W | Vector Bit Clear (word) |
514 * | BCLR.D | Vector Bit Clear (doubleword) |
515 * | BNEG.B | Vector Bit Negate (byte) |
516 * | BNEG.H | Vector Bit Negate (halfword) |
517 * | BNEG.W | Vector Bit Negate (word) |
518 * | BNEG.D | Vector Bit Negate (doubleword) |
519 * | BSET.B | Vector Bit Set (byte) |
520 * | BSET.H | Vector Bit Set (halfword) |
521 * | BSET.W | Vector Bit Set (word) |
522 * | BSET.D | Vector Bit Set (doubleword) |
523 * +---------------+----------------------------------------------------------+
524 */
525
526 static inline int64_t msa_bclr_df(uint32_t df, int64_t arg1, int64_t arg2)
527 {
528 int32_t b_arg2 = BIT_POSITION(arg2, df);
529 return UNSIGNED(arg1 & (~(1LL << b_arg2)), df);
530 }
531
532 void helper_msa_bclr_b(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
533 {
534 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
535 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
536 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
537
538 pwd->b[0] = msa_bclr_df(DF_BYTE, pws->b[0], pwt->b[0]);
539 pwd->b[1] = msa_bclr_df(DF_BYTE, pws->b[1], pwt->b[1]);
540 pwd->b[2] = msa_bclr_df(DF_BYTE, pws->b[2], pwt->b[2]);
541 pwd->b[3] = msa_bclr_df(DF_BYTE, pws->b[3], pwt->b[3]);
542 pwd->b[4] = msa_bclr_df(DF_BYTE, pws->b[4], pwt->b[4]);
543 pwd->b[5] = msa_bclr_df(DF_BYTE, pws->b[5], pwt->b[5]);
544 pwd->b[6] = msa_bclr_df(DF_BYTE, pws->b[6], pwt->b[6]);
545 pwd->b[7] = msa_bclr_df(DF_BYTE, pws->b[7], pwt->b[7]);
546 pwd->b[8] = msa_bclr_df(DF_BYTE, pws->b[8], pwt->b[8]);
547 pwd->b[9] = msa_bclr_df(DF_BYTE, pws->b[9], pwt->b[9]);
548 pwd->b[10] = msa_bclr_df(DF_BYTE, pws->b[10], pwt->b[10]);
549 pwd->b[11] = msa_bclr_df(DF_BYTE, pws->b[11], pwt->b[11]);
550 pwd->b[12] = msa_bclr_df(DF_BYTE, pws->b[12], pwt->b[12]);
551 pwd->b[13] = msa_bclr_df(DF_BYTE, pws->b[13], pwt->b[13]);
552 pwd->b[14] = msa_bclr_df(DF_BYTE, pws->b[14], pwt->b[14]);
553 pwd->b[15] = msa_bclr_df(DF_BYTE, pws->b[15], pwt->b[15]);
554 }
555
556 void helper_msa_bclr_h(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
557 {
558 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
559 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
560 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
561
562 pwd->h[0] = msa_bclr_df(DF_HALF, pws->h[0], pwt->h[0]);
563 pwd->h[1] = msa_bclr_df(DF_HALF, pws->h[1], pwt->h[1]);
564 pwd->h[2] = msa_bclr_df(DF_HALF, pws->h[2], pwt->h[2]);
565 pwd->h[3] = msa_bclr_df(DF_HALF, pws->h[3], pwt->h[3]);
566 pwd->h[4] = msa_bclr_df(DF_HALF, pws->h[4], pwt->h[4]);
567 pwd->h[5] = msa_bclr_df(DF_HALF, pws->h[5], pwt->h[5]);
568 pwd->h[6] = msa_bclr_df(DF_HALF, pws->h[6], pwt->h[6]);
569 pwd->h[7] = msa_bclr_df(DF_HALF, pws->h[7], pwt->h[7]);
570 }
571
572 void helper_msa_bclr_w(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
573 {
574 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
575 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
576 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
577
578 pwd->w[0] = msa_bclr_df(DF_WORD, pws->w[0], pwt->w[0]);
579 pwd->w[1] = msa_bclr_df(DF_WORD, pws->w[1], pwt->w[1]);
580 pwd->w[2] = msa_bclr_df(DF_WORD, pws->w[2], pwt->w[2]);
581 pwd->w[3] = msa_bclr_df(DF_WORD, pws->w[3], pwt->w[3]);
582 }
583
584 void helper_msa_bclr_d(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
585 {
586 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
587 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
588 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
589
590 pwd->d[0] = msa_bclr_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
591 pwd->d[1] = msa_bclr_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
592 }
593
594 static inline int64_t msa_bneg_df(uint32_t df, int64_t arg1, int64_t arg2)
595 {
596 int32_t b_arg2 = BIT_POSITION(arg2, df);
597 return UNSIGNED(arg1 ^ (1LL << b_arg2), df);
598 }
599
600 void helper_msa_bneg_b(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
601 {
602 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
603 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
604 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
605
606 pwd->b[0] = msa_bneg_df(DF_BYTE, pws->b[0], pwt->b[0]);
607 pwd->b[1] = msa_bneg_df(DF_BYTE, pws->b[1], pwt->b[1]);
608 pwd->b[2] = msa_bneg_df(DF_BYTE, pws->b[2], pwt->b[2]);
609 pwd->b[3] = msa_bneg_df(DF_BYTE, pws->b[3], pwt->b[3]);
610 pwd->b[4] = msa_bneg_df(DF_BYTE, pws->b[4], pwt->b[4]);
611 pwd->b[5] = msa_bneg_df(DF_BYTE, pws->b[5], pwt->b[5]);
612 pwd->b[6] = msa_bneg_df(DF_BYTE, pws->b[6], pwt->b[6]);
613 pwd->b[7] = msa_bneg_df(DF_BYTE, pws->b[7], pwt->b[7]);
614 pwd->b[8] = msa_bneg_df(DF_BYTE, pws->b[8], pwt->b[8]);
615 pwd->b[9] = msa_bneg_df(DF_BYTE, pws->b[9], pwt->b[9]);
616 pwd->b[10] = msa_bneg_df(DF_BYTE, pws->b[10], pwt->b[10]);
617 pwd->b[11] = msa_bneg_df(DF_BYTE, pws->b[11], pwt->b[11]);
618 pwd->b[12] = msa_bneg_df(DF_BYTE, pws->b[12], pwt->b[12]);
619 pwd->b[13] = msa_bneg_df(DF_BYTE, pws->b[13], pwt->b[13]);
620 pwd->b[14] = msa_bneg_df(DF_BYTE, pws->b[14], pwt->b[14]);
621 pwd->b[15] = msa_bneg_df(DF_BYTE, pws->b[15], pwt->b[15]);
622 }
623
624 void helper_msa_bneg_h(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
625 {
626 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
627 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
628 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
629
630 pwd->h[0] = msa_bneg_df(DF_HALF, pws->h[0], pwt->h[0]);
631 pwd->h[1] = msa_bneg_df(DF_HALF, pws->h[1], pwt->h[1]);
632 pwd->h[2] = msa_bneg_df(DF_HALF, pws->h[2], pwt->h[2]);
633 pwd->h[3] = msa_bneg_df(DF_HALF, pws->h[3], pwt->h[3]);
634 pwd->h[4] = msa_bneg_df(DF_HALF, pws->h[4], pwt->h[4]);
635 pwd->h[5] = msa_bneg_df(DF_HALF, pws->h[5], pwt->h[5]);
636 pwd->h[6] = msa_bneg_df(DF_HALF, pws->h[6], pwt->h[6]);
637 pwd->h[7] = msa_bneg_df(DF_HALF, pws->h[7], pwt->h[7]);
638 }
639
640 void helper_msa_bneg_w(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
641 {
642 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
643 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
644 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
645
646 pwd->w[0] = msa_bneg_df(DF_WORD, pws->w[0], pwt->w[0]);
647 pwd->w[1] = msa_bneg_df(DF_WORD, pws->w[1], pwt->w[1]);
648 pwd->w[2] = msa_bneg_df(DF_WORD, pws->w[2], pwt->w[2]);
649 pwd->w[3] = msa_bneg_df(DF_WORD, pws->w[3], pwt->w[3]);
650 }
651
652 void helper_msa_bneg_d(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
653 {
654 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
655 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
656 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
657
658 pwd->d[0] = msa_bneg_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
659 pwd->d[1] = msa_bneg_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
660 }
661
662 static inline int64_t msa_bset_df(uint32_t df, int64_t arg1,
663 int64_t arg2)
664 {
665 int32_t b_arg2 = BIT_POSITION(arg2, df);
666 return UNSIGNED(arg1 | (1LL << b_arg2), df);
667 }
668
669 void helper_msa_bset_b(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
670 {
671 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
672 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
673 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
674
675 pwd->b[0] = msa_bset_df(DF_BYTE, pws->b[0], pwt->b[0]);
676 pwd->b[1] = msa_bset_df(DF_BYTE, pws->b[1], pwt->b[1]);
677 pwd->b[2] = msa_bset_df(DF_BYTE, pws->b[2], pwt->b[2]);
678 pwd->b[3] = msa_bset_df(DF_BYTE, pws->b[3], pwt->b[3]);
679 pwd->b[4] = msa_bset_df(DF_BYTE, pws->b[4], pwt->b[4]);
680 pwd->b[5] = msa_bset_df(DF_BYTE, pws->b[5], pwt->b[5]);
681 pwd->b[6] = msa_bset_df(DF_BYTE, pws->b[6], pwt->b[6]);
682 pwd->b[7] = msa_bset_df(DF_BYTE, pws->b[7], pwt->b[7]);
683 pwd->b[8] = msa_bset_df(DF_BYTE, pws->b[8], pwt->b[8]);
684 pwd->b[9] = msa_bset_df(DF_BYTE, pws->b[9], pwt->b[9]);
685 pwd->b[10] = msa_bset_df(DF_BYTE, pws->b[10], pwt->b[10]);
686 pwd->b[11] = msa_bset_df(DF_BYTE, pws->b[11], pwt->b[11]);
687 pwd->b[12] = msa_bset_df(DF_BYTE, pws->b[12], pwt->b[12]);
688 pwd->b[13] = msa_bset_df(DF_BYTE, pws->b[13], pwt->b[13]);
689 pwd->b[14] = msa_bset_df(DF_BYTE, pws->b[14], pwt->b[14]);
690 pwd->b[15] = msa_bset_df(DF_BYTE, pws->b[15], pwt->b[15]);
691 }
692
693 void helper_msa_bset_h(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
694 {
695 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
696 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
697 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
698
699 pwd->h[0] = msa_bset_df(DF_HALF, pws->h[0], pwt->h[0]);
700 pwd->h[1] = msa_bset_df(DF_HALF, pws->h[1], pwt->h[1]);
701 pwd->h[2] = msa_bset_df(DF_HALF, pws->h[2], pwt->h[2]);
702 pwd->h[3] = msa_bset_df(DF_HALF, pws->h[3], pwt->h[3]);
703 pwd->h[4] = msa_bset_df(DF_HALF, pws->h[4], pwt->h[4]);
704 pwd->h[5] = msa_bset_df(DF_HALF, pws->h[5], pwt->h[5]);
705 pwd->h[6] = msa_bset_df(DF_HALF, pws->h[6], pwt->h[6]);
706 pwd->h[7] = msa_bset_df(DF_HALF, pws->h[7], pwt->h[7]);
707 }
708
709 void helper_msa_bset_w(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
710 {
711 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
712 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
713 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
714
715 pwd->w[0] = msa_bset_df(DF_WORD, pws->w[0], pwt->w[0]);
716 pwd->w[1] = msa_bset_df(DF_WORD, pws->w[1], pwt->w[1]);
717 pwd->w[2] = msa_bset_df(DF_WORD, pws->w[2], pwt->w[2]);
718 pwd->w[3] = msa_bset_df(DF_WORD, pws->w[3], pwt->w[3]);
719 }
720
721 void helper_msa_bset_d(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
722 {
723 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
724 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
725 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
726
727 pwd->d[0] = msa_bset_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
728 pwd->d[1] = msa_bset_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
729 }
730
731
732 /*
733 * Fixed Multiply
734 * --------------
735 *
736 * +---------------+----------------------------------------------------------+
737 * | MADD_Q.H | Vector Fixed-Point Multiply and Add (halfword) |
738 * | MADD_Q.W | Vector Fixed-Point Multiply and Add (word) |
739 * | MADDR_Q.H | Vector Fixed-Point Multiply and Add Rounded (halfword) |
740 * | MADDR_Q.W | Vector Fixed-Point Multiply and Add Rounded (word) |
741 * | MSUB_Q.H | Vector Fixed-Point Multiply and Subtr. (halfword) |
742 * | MSUB_Q.W | Vector Fixed-Point Multiply and Subtr. (word) |
743 * | MSUBR_Q.H | Vector Fixed-Point Multiply and Subtr. Rounded (halfword)|
744 * | MSUBR_Q.W | Vector Fixed-Point Multiply and Subtr. Rounded (word) |
745 * | MUL_Q.H | Vector Fixed-Point Multiply (halfword) |
746 * | MUL_Q.W | Vector Fixed-Point Multiply (word) |
747 * | MULR_Q.H | Vector Fixed-Point Multiply Rounded (halfword) |
748 * | MULR_Q.W | Vector Fixed-Point Multiply Rounded (word) |
749 * +---------------+----------------------------------------------------------+
750 */
751
752 /* TODO: insert Fixed Multiply group helpers here */
753
754
755 /*
756 * Float Max Min
757 * -------------
758 *
759 * +---------------+----------------------------------------------------------+
760 * | FMAX_A.W | Vector Floating-Point Maximum (Absolute) (word) |
761 * | FMAX_A.D | Vector Floating-Point Maximum (Absolute) (doubleword) |
762 * | FMAX.W | Vector Floating-Point Maximum (word) |
763 * | FMAX.D | Vector Floating-Point Maximum (doubleword) |
764 * | FMIN_A.W | Vector Floating-Point Minimum (Absolute) (word) |
765 * | FMIN_A.D | Vector Floating-Point Minimum (Absolute) (doubleword) |
766 * | FMIN.W | Vector Floating-Point Minimum (word) |
767 * | FMIN.D | Vector Floating-Point Minimum (doubleword) |
768 * +---------------+----------------------------------------------------------+
769 */
770
771 /* TODO: insert Float Max Min group helpers here */
772
773
774 /*
775 * Int Add
776 * -------
777 *
778 * +---------------+----------------------------------------------------------+
779 * | ADD_A.B | Vector Add Absolute Values (byte) |
780 * | ADD_A.H | Vector Add Absolute Values (halfword) |
781 * | ADD_A.W | Vector Add Absolute Values (word) |
782 * | ADD_A.D | Vector Add Absolute Values (doubleword) |
783 * | ADDS_A.B | Vector Signed Saturated Add (of Absolute) (byte) |
784 * | ADDS_A.H | Vector Signed Saturated Add (of Absolute) (halfword) |
785 * | ADDS_A.W | Vector Signed Saturated Add (of Absolute) (word) |
786 * | ADDS_A.D | Vector Signed Saturated Add (of Absolute) (doubleword) |
787 * | ADDS_S.B | Vector Signed Saturated Add (of Signed) (byte) |
788 * | ADDS_S.H | Vector Signed Saturated Add (of Signed) (halfword) |
789 * | ADDS_S.W | Vector Signed Saturated Add (of Signed) (word) |
790 * | ADDS_S.D | Vector Signed Saturated Add (of Signed) (doubleword) |
791 * | ADDS_U.B | Vector Unsigned Saturated Add (of Unsigned) (byte) |
792 * | ADDS_U.H | Vector Unsigned Saturated Add (of Unsigned) (halfword) |
793 * | ADDS_U.W | Vector Unsigned Saturated Add (of Unsigned) (word) |
794 * | ADDS_U.D | Vector Unsigned Saturated Add (of Unsigned) (doubleword) |
795 * | ADDV.B | Vector Add (byte) |
796 * | ADDV.H | Vector Add (halfword) |
797 * | ADDV.W | Vector Add (word) |
798 * | ADDV.D | Vector Add (doubleword) |
799 * | HADD_S.H | Vector Signed Horizontal Add (halfword) |
800 * | HADD_S.W | Vector Signed Horizontal Add (word) |
801 * | HADD_S.D | Vector Signed Horizontal Add (doubleword) |
802 * | HADD_U.H | Vector Unigned Horizontal Add (halfword) |
803 * | HADD_U.W | Vector Unigned Horizontal Add (word) |
804 * | HADD_U.D | Vector Unigned Horizontal Add (doubleword) |
805 * +---------------+----------------------------------------------------------+
806 */
807
808 /* TODO: insert Int Add group helpers here */
809
810
811 /*
812 * Int Average
813 * -----------
814 *
815 * +---------------+----------------------------------------------------------+
816 * | AVE_S.B | Vector Signed Average (byte) |
817 * | AVE_S.H | Vector Signed Average (halfword) |
818 * | AVE_S.W | Vector Signed Average (word) |
819 * | AVE_S.D | Vector Signed Average (doubleword) |
820 * | AVE_U.B | Vector Unsigned Average (byte) |
821 * | AVE_U.H | Vector Unsigned Average (halfword) |
822 * | AVE_U.W | Vector Unsigned Average (word) |
823 * | AVE_U.D | Vector Unsigned Average (doubleword) |
824 * | AVER_S.B | Vector Signed Average Rounded (byte) |
825 * | AVER_S.H | Vector Signed Average Rounded (halfword) |
826 * | AVER_S.W | Vector Signed Average Rounded (word) |
827 * | AVER_S.D | Vector Signed Average Rounded (doubleword) |
828 * | AVER_U.B | Vector Unsigned Average Rounded (byte) |
829 * | AVER_U.H | Vector Unsigned Average Rounded (halfword) |
830 * | AVER_U.W | Vector Unsigned Average Rounded (word) |
831 * | AVER_U.D | Vector Unsigned Average Rounded (doubleword) |
832 * +---------------+----------------------------------------------------------+
833 */
834
835 static inline int64_t msa_ave_s_df(uint32_t df, int64_t arg1, int64_t arg2)
836 {
837 /* signed shift */
838 return (arg1 >> 1) + (arg2 >> 1) + (arg1 & arg2 & 1);
839 }
840
841 void helper_msa_ave_s_b(CPUMIPSState *env,
842 uint32_t wd, uint32_t ws, uint32_t wt)
843 {
844 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
845 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
846 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
847
848 pwd->b[0] = msa_ave_s_df(DF_BYTE, pws->b[0], pwt->b[0]);
849 pwd->b[1] = msa_ave_s_df(DF_BYTE, pws->b[1], pwt->b[1]);
850 pwd->b[2] = msa_ave_s_df(DF_BYTE, pws->b[2], pwt->b[2]);
851 pwd->b[3] = msa_ave_s_df(DF_BYTE, pws->b[3], pwt->b[3]);
852 pwd->b[4] = msa_ave_s_df(DF_BYTE, pws->b[4], pwt->b[4]);
853 pwd->b[5] = msa_ave_s_df(DF_BYTE, pws->b[5], pwt->b[5]);
854 pwd->b[6] = msa_ave_s_df(DF_BYTE, pws->b[6], pwt->b[6]);
855 pwd->b[7] = msa_ave_s_df(DF_BYTE, pws->b[7], pwt->b[7]);
856 pwd->b[8] = msa_ave_s_df(DF_BYTE, pws->b[8], pwt->b[8]);
857 pwd->b[9] = msa_ave_s_df(DF_BYTE, pws->b[9], pwt->b[9]);
858 pwd->b[10] = msa_ave_s_df(DF_BYTE, pws->b[10], pwt->b[10]);
859 pwd->b[11] = msa_ave_s_df(DF_BYTE, pws->b[11], pwt->b[11]);
860 pwd->b[12] = msa_ave_s_df(DF_BYTE, pws->b[12], pwt->b[12]);
861 pwd->b[13] = msa_ave_s_df(DF_BYTE, pws->b[13], pwt->b[13]);
862 pwd->b[14] = msa_ave_s_df(DF_BYTE, pws->b[14], pwt->b[14]);
863 pwd->b[15] = msa_ave_s_df(DF_BYTE, pws->b[15], pwt->b[15]);
864 }
865
866 void helper_msa_ave_s_h(CPUMIPSState *env,
867 uint32_t wd, uint32_t ws, uint32_t wt)
868 {
869 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
870 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
871 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
872
873 pwd->h[0] = msa_ave_s_df(DF_HALF, pws->h[0], pwt->h[0]);
874 pwd->h[1] = msa_ave_s_df(DF_HALF, pws->h[1], pwt->h[1]);
875 pwd->h[2] = msa_ave_s_df(DF_HALF, pws->h[2], pwt->h[2]);
876 pwd->h[3] = msa_ave_s_df(DF_HALF, pws->h[3], pwt->h[3]);
877 pwd->h[4] = msa_ave_s_df(DF_HALF, pws->h[4], pwt->h[4]);
878 pwd->h[5] = msa_ave_s_df(DF_HALF, pws->h[5], pwt->h[5]);
879 pwd->h[6] = msa_ave_s_df(DF_HALF, pws->h[6], pwt->h[6]);
880 pwd->h[7] = msa_ave_s_df(DF_HALF, pws->h[7], pwt->h[7]);
881 }
882
883 void helper_msa_ave_s_w(CPUMIPSState *env,
884 uint32_t wd, uint32_t ws, uint32_t wt)
885 {
886 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
887 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
888 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
889
890 pwd->w[0] = msa_ave_s_df(DF_WORD, pws->w[0], pwt->w[0]);
891 pwd->w[1] = msa_ave_s_df(DF_WORD, pws->w[1], pwt->w[1]);
892 pwd->w[2] = msa_ave_s_df(DF_WORD, pws->w[2], pwt->w[2]);
893 pwd->w[3] = msa_ave_s_df(DF_WORD, pws->w[3], pwt->w[3]);
894 }
895
896 void helper_msa_ave_s_d(CPUMIPSState *env,
897 uint32_t wd, uint32_t ws, uint32_t wt)
898 {
899 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
900 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
901 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
902
903 pwd->d[0] = msa_ave_s_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
904 pwd->d[1] = msa_ave_s_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
905 }
906
907 static inline uint64_t msa_ave_u_df(uint32_t df, uint64_t arg1, uint64_t arg2)
908 {
909 uint64_t u_arg1 = UNSIGNED(arg1, df);
910 uint64_t u_arg2 = UNSIGNED(arg2, df);
911 /* unsigned shift */
912 return (u_arg1 >> 1) + (u_arg2 >> 1) + (u_arg1 & u_arg2 & 1);
913 }
914
915 void helper_msa_ave_u_b(CPUMIPSState *env,
916 uint32_t wd, uint32_t ws, uint32_t wt)
917 {
918 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
919 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
920 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
921
922 pwd->b[0] = msa_ave_u_df(DF_BYTE, pws->b[0], pwt->b[0]);
923 pwd->b[1] = msa_ave_u_df(DF_BYTE, pws->b[1], pwt->b[1]);
924 pwd->b[2] = msa_ave_u_df(DF_BYTE, pws->b[2], pwt->b[2]);
925 pwd->b[3] = msa_ave_u_df(DF_BYTE, pws->b[3], pwt->b[3]);
926 pwd->b[4] = msa_ave_u_df(DF_BYTE, pws->b[4], pwt->b[4]);
927 pwd->b[5] = msa_ave_u_df(DF_BYTE, pws->b[5], pwt->b[5]);
928 pwd->b[6] = msa_ave_u_df(DF_BYTE, pws->b[6], pwt->b[6]);
929 pwd->b[7] = msa_ave_u_df(DF_BYTE, pws->b[7], pwt->b[7]);
930 pwd->b[8] = msa_ave_u_df(DF_BYTE, pws->b[8], pwt->b[8]);
931 pwd->b[9] = msa_ave_u_df(DF_BYTE, pws->b[9], pwt->b[9]);
932 pwd->b[10] = msa_ave_u_df(DF_BYTE, pws->b[10], pwt->b[10]);
933 pwd->b[11] = msa_ave_u_df(DF_BYTE, pws->b[11], pwt->b[11]);
934 pwd->b[12] = msa_ave_u_df(DF_BYTE, pws->b[12], pwt->b[12]);
935 pwd->b[13] = msa_ave_u_df(DF_BYTE, pws->b[13], pwt->b[13]);
936 pwd->b[14] = msa_ave_u_df(DF_BYTE, pws->b[14], pwt->b[14]);
937 pwd->b[15] = msa_ave_u_df(DF_BYTE, pws->b[15], pwt->b[15]);
938 }
939
940 void helper_msa_ave_u_h(CPUMIPSState *env,
941 uint32_t wd, uint32_t ws, uint32_t wt)
942 {
943 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
944 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
945 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
946
947 pwd->h[0] = msa_ave_u_df(DF_HALF, pws->h[0], pwt->h[0]);
948 pwd->h[1] = msa_ave_u_df(DF_HALF, pws->h[1], pwt->h[1]);
949 pwd->h[2] = msa_ave_u_df(DF_HALF, pws->h[2], pwt->h[2]);
950 pwd->h[3] = msa_ave_u_df(DF_HALF, pws->h[3], pwt->h[3]);
951 pwd->h[4] = msa_ave_u_df(DF_HALF, pws->h[4], pwt->h[4]);
952 pwd->h[5] = msa_ave_u_df(DF_HALF, pws->h[5], pwt->h[5]);
953 pwd->h[6] = msa_ave_u_df(DF_HALF, pws->h[6], pwt->h[6]);
954 pwd->h[7] = msa_ave_u_df(DF_HALF, pws->h[7], pwt->h[7]);
955 }
956
957 void helper_msa_ave_u_w(CPUMIPSState *env,
958 uint32_t wd, uint32_t ws, uint32_t wt)
959 {
960 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
961 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
962 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
963
964 pwd->w[0] = msa_ave_u_df(DF_WORD, pws->w[0], pwt->w[0]);
965 pwd->w[1] = msa_ave_u_df(DF_WORD, pws->w[1], pwt->w[1]);
966 pwd->w[2] = msa_ave_u_df(DF_WORD, pws->w[2], pwt->w[2]);
967 pwd->w[3] = msa_ave_u_df(DF_WORD, pws->w[3], pwt->w[3]);
968 }
969
970 void helper_msa_ave_u_d(CPUMIPSState *env,
971 uint32_t wd, uint32_t ws, uint32_t wt)
972 {
973 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
974 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
975 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
976
977 pwd->d[0] = msa_ave_u_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
978 pwd->d[1] = msa_ave_u_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
979 }
980
981 static inline int64_t msa_aver_s_df(uint32_t df, int64_t arg1, int64_t arg2)
982 {
983 /* signed shift */
984 return (arg1 >> 1) + (arg2 >> 1) + ((arg1 | arg2) & 1);
985 }
986
987 void helper_msa_aver_s_b(CPUMIPSState *env,
988 uint32_t wd, uint32_t ws, uint32_t wt)
989 {
990 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
991 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
992 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
993
994 pwd->b[0] = msa_aver_s_df(DF_BYTE, pws->b[0], pwt->b[0]);
995 pwd->b[1] = msa_aver_s_df(DF_BYTE, pws->b[1], pwt->b[1]);
996 pwd->b[2] = msa_aver_s_df(DF_BYTE, pws->b[2], pwt->b[2]);
997 pwd->b[3] = msa_aver_s_df(DF_BYTE, pws->b[3], pwt->b[3]);
998 pwd->b[4] = msa_aver_s_df(DF_BYTE, pws->b[4], pwt->b[4]);
999 pwd->b[5] = msa_aver_s_df(DF_BYTE, pws->b[5], pwt->b[5]);
1000 pwd->b[6] = msa_aver_s_df(DF_BYTE, pws->b[6], pwt->b[6]);
1001 pwd->b[7] = msa_aver_s_df(DF_BYTE, pws->b[7], pwt->b[7]);
1002 pwd->b[8] = msa_aver_s_df(DF_BYTE, pws->b[8], pwt->b[8]);
1003 pwd->b[9] = msa_aver_s_df(DF_BYTE, pws->b[9], pwt->b[9]);
1004 pwd->b[10] = msa_aver_s_df(DF_BYTE, pws->b[10], pwt->b[10]);
1005 pwd->b[11] = msa_aver_s_df(DF_BYTE, pws->b[11], pwt->b[11]);
1006 pwd->b[12] = msa_aver_s_df(DF_BYTE, pws->b[12], pwt->b[12]);
1007 pwd->b[13] = msa_aver_s_df(DF_BYTE, pws->b[13], pwt->b[13]);
1008 pwd->b[14] = msa_aver_s_df(DF_BYTE, pws->b[14], pwt->b[14]);
1009 pwd->b[15] = msa_aver_s_df(DF_BYTE, pws->b[15], pwt->b[15]);
1010 }
1011
1012 void helper_msa_aver_s_h(CPUMIPSState *env,
1013 uint32_t wd, uint32_t ws, uint32_t wt)
1014 {
1015 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1016 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1017 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1018
1019 pwd->h[0] = msa_aver_s_df(DF_HALF, pws->h[0], pwt->h[0]);
1020 pwd->h[1] = msa_aver_s_df(DF_HALF, pws->h[1], pwt->h[1]);
1021 pwd->h[2] = msa_aver_s_df(DF_HALF, pws->h[2], pwt->h[2]);
1022 pwd->h[3] = msa_aver_s_df(DF_HALF, pws->h[3], pwt->h[3]);
1023 pwd->h[4] = msa_aver_s_df(DF_HALF, pws->h[4], pwt->h[4]);
1024 pwd->h[5] = msa_aver_s_df(DF_HALF, pws->h[5], pwt->h[5]);
1025 pwd->h[6] = msa_aver_s_df(DF_HALF, pws->h[6], pwt->h[6]);
1026 pwd->h[7] = msa_aver_s_df(DF_HALF, pws->h[7], pwt->h[7]);
1027 }
1028
1029 void helper_msa_aver_s_w(CPUMIPSState *env,
1030 uint32_t wd, uint32_t ws, uint32_t wt)
1031 {
1032 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1033 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1034 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1035
1036 pwd->w[0] = msa_aver_s_df(DF_WORD, pws->w[0], pwt->w[0]);
1037 pwd->w[1] = msa_aver_s_df(DF_WORD, pws->w[1], pwt->w[1]);
1038 pwd->w[2] = msa_aver_s_df(DF_WORD, pws->w[2], pwt->w[2]);
1039 pwd->w[3] = msa_aver_s_df(DF_WORD, pws->w[3], pwt->w[3]);
1040 }
1041
1042 void helper_msa_aver_s_d(CPUMIPSState *env,
1043 uint32_t wd, uint32_t ws, uint32_t wt)
1044 {
1045 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1046 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1047 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1048
1049 pwd->d[0] = msa_aver_s_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
1050 pwd->d[1] = msa_aver_s_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
1051 }
1052
1053 static inline uint64_t msa_aver_u_df(uint32_t df, uint64_t arg1, uint64_t arg2)
1054 {
1055 uint64_t u_arg1 = UNSIGNED(arg1, df);
1056 uint64_t u_arg2 = UNSIGNED(arg2, df);
1057 /* unsigned shift */
1058 return (u_arg1 >> 1) + (u_arg2 >> 1) + ((u_arg1 | u_arg2) & 1);
1059 }
1060
1061 void helper_msa_aver_u_b(CPUMIPSState *env,
1062 uint32_t wd, uint32_t ws, uint32_t wt)
1063 {
1064 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1065 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1066 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1067
1068 pwd->b[0] = msa_aver_u_df(DF_BYTE, pws->b[0], pwt->b[0]);
1069 pwd->b[1] = msa_aver_u_df(DF_BYTE, pws->b[1], pwt->b[1]);
1070 pwd->b[2] = msa_aver_u_df(DF_BYTE, pws->b[2], pwt->b[2]);
1071 pwd->b[3] = msa_aver_u_df(DF_BYTE, pws->b[3], pwt->b[3]);
1072 pwd->b[4] = msa_aver_u_df(DF_BYTE, pws->b[4], pwt->b[4]);
1073 pwd->b[5] = msa_aver_u_df(DF_BYTE, pws->b[5], pwt->b[5]);
1074 pwd->b[6] = msa_aver_u_df(DF_BYTE, pws->b[6], pwt->b[6]);
1075 pwd->b[7] = msa_aver_u_df(DF_BYTE, pws->b[7], pwt->b[7]);
1076 pwd->b[8] = msa_aver_u_df(DF_BYTE, pws->b[8], pwt->b[8]);
1077 pwd->b[9] = msa_aver_u_df(DF_BYTE, pws->b[9], pwt->b[9]);
1078 pwd->b[10] = msa_aver_u_df(DF_BYTE, pws->b[10], pwt->b[10]);
1079 pwd->b[11] = msa_aver_u_df(DF_BYTE, pws->b[11], pwt->b[11]);
1080 pwd->b[12] = msa_aver_u_df(DF_BYTE, pws->b[12], pwt->b[12]);
1081 pwd->b[13] = msa_aver_u_df(DF_BYTE, pws->b[13], pwt->b[13]);
1082 pwd->b[14] = msa_aver_u_df(DF_BYTE, pws->b[14], pwt->b[14]);
1083 pwd->b[15] = msa_aver_u_df(DF_BYTE, pws->b[15], pwt->b[15]);
1084 }
1085
1086 void helper_msa_aver_u_h(CPUMIPSState *env,
1087 uint32_t wd, uint32_t ws, uint32_t wt)
1088 {
1089 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1090 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1091 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1092
1093 pwd->h[0] = msa_aver_u_df(DF_HALF, pws->h[0], pwt->h[0]);
1094 pwd->h[1] = msa_aver_u_df(DF_HALF, pws->h[1], pwt->h[1]);
1095 pwd->h[2] = msa_aver_u_df(DF_HALF, pws->h[2], pwt->h[2]);
1096 pwd->h[3] = msa_aver_u_df(DF_HALF, pws->h[3], pwt->h[3]);
1097 pwd->h[4] = msa_aver_u_df(DF_HALF, pws->h[4], pwt->h[4]);
1098 pwd->h[5] = msa_aver_u_df(DF_HALF, pws->h[5], pwt->h[5]);
1099 pwd->h[6] = msa_aver_u_df(DF_HALF, pws->h[6], pwt->h[6]);
1100 pwd->h[7] = msa_aver_u_df(DF_HALF, pws->h[7], pwt->h[7]);
1101 }
1102
1103 void helper_msa_aver_u_w(CPUMIPSState *env,
1104 uint32_t wd, uint32_t ws, uint32_t wt)
1105 {
1106 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1107 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1108 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1109
1110 pwd->w[0] = msa_aver_u_df(DF_WORD, pws->w[0], pwt->w[0]);
1111 pwd->w[1] = msa_aver_u_df(DF_WORD, pws->w[1], pwt->w[1]);
1112 pwd->w[2] = msa_aver_u_df(DF_WORD, pws->w[2], pwt->w[2]);
1113 pwd->w[3] = msa_aver_u_df(DF_WORD, pws->w[3], pwt->w[3]);
1114 }
1115
1116 void helper_msa_aver_u_d(CPUMIPSState *env,
1117 uint32_t wd, uint32_t ws, uint32_t wt)
1118 {
1119 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1120 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1121 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1122
1123 pwd->d[0] = msa_aver_u_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
1124 pwd->d[1] = msa_aver_u_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
1125 }
1126
1127
1128 /*
1129 * Int Compare
1130 * -----------
1131 *
1132 * +---------------+----------------------------------------------------------+
1133 * | CEQ.B | Vector Compare Equal (byte) |
1134 * | CEQ.H | Vector Compare Equal (halfword) |
1135 * | CEQ.W | Vector Compare Equal (word) |
1136 * | CEQ.D | Vector Compare Equal (doubleword) |
1137 * | CLE_S.B | Vector Compare Signed Less Than or Equal (byte) |
1138 * | CLE_S.H | Vector Compare Signed Less Than or Equal (halfword) |
1139 * | CLE_S.W | Vector Compare Signed Less Than or Equal (word) |
1140 * | CLE_S.D | Vector Compare Signed Less Than or Equal (doubleword) |
1141 * | CLE_U.B | Vector Compare Unsigned Less Than or Equal (byte) |
1142 * | CLE_U.H | Vector Compare Unsigned Less Than or Equal (halfword) |
1143 * | CLE_U.W | Vector Compare Unsigned Less Than or Equal (word) |
1144 * | CLE_U.D | Vector Compare Unsigned Less Than or Equal (doubleword) |
1145 * | CLT_S.B | Vector Compare Signed Less Than (byte) |
1146 * | CLT_S.H | Vector Compare Signed Less Than (halfword) |
1147 * | CLT_S.W | Vector Compare Signed Less Than (word) |
1148 * | CLT_S.D | Vector Compare Signed Less Than (doubleword) |
1149 * | CLT_U.B | Vector Compare Unsigned Less Than (byte) |
1150 * | CLT_U.H | Vector Compare Unsigned Less Than (halfword) |
1151 * | CLT_U.W | Vector Compare Unsigned Less Than (word) |
1152 * | CLT_U.D | Vector Compare Unsigned Less Than (doubleword) |
1153 * +---------------+----------------------------------------------------------+
1154 */
1155
1156 static inline int64_t msa_ceq_df(uint32_t df, int64_t arg1, int64_t arg2)
1157 {
1158 return arg1 == arg2 ? -1 : 0;
1159 }
1160
1161 void helper_msa_ceq_b(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
1162 {
1163 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1164 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1165 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1166
1167 pwd->b[0] = msa_ceq_df(DF_BYTE, pws->b[0], pwt->b[0]);
1168 pwd->b[1] = msa_ceq_df(DF_BYTE, pws->b[1], pwt->b[1]);
1169 pwd->b[2] = msa_ceq_df(DF_BYTE, pws->b[2], pwt->b[2]);
1170 pwd->b[3] = msa_ceq_df(DF_BYTE, pws->b[3], pwt->b[3]);
1171 pwd->b[4] = msa_ceq_df(DF_BYTE, pws->b[4], pwt->b[4]);
1172 pwd->b[5] = msa_ceq_df(DF_BYTE, pws->b[5], pwt->b[5]);
1173 pwd->b[6] = msa_ceq_df(DF_BYTE, pws->b[6], pwt->b[6]);
1174 pwd->b[7] = msa_ceq_df(DF_BYTE, pws->b[7], pwt->b[7]);
1175 pwd->b[8] = msa_ceq_df(DF_BYTE, pws->b[8], pwt->b[8]);
1176 pwd->b[9] = msa_ceq_df(DF_BYTE, pws->b[9], pwt->b[9]);
1177 pwd->b[10] = msa_ceq_df(DF_BYTE, pws->b[10], pwt->b[10]);
1178 pwd->b[11] = msa_ceq_df(DF_BYTE, pws->b[11], pwt->b[11]);
1179 pwd->b[12] = msa_ceq_df(DF_BYTE, pws->b[12], pwt->b[12]);
1180 pwd->b[13] = msa_ceq_df(DF_BYTE, pws->b[13], pwt->b[13]);
1181 pwd->b[14] = msa_ceq_df(DF_BYTE, pws->b[14], pwt->b[14]);
1182 pwd->b[15] = msa_ceq_df(DF_BYTE, pws->b[15], pwt->b[15]);
1183 }
1184
1185 void helper_msa_ceq_h(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
1186 {
1187 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1188 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1189 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1190
1191 pwd->h[0] = msa_ceq_df(DF_HALF, pws->h[0], pwt->h[0]);
1192 pwd->h[1] = msa_ceq_df(DF_HALF, pws->h[1], pwt->h[1]);
1193 pwd->h[2] = msa_ceq_df(DF_HALF, pws->h[2], pwt->h[2]);
1194 pwd->h[3] = msa_ceq_df(DF_HALF, pws->h[3], pwt->h[3]);
1195 pwd->h[4] = msa_ceq_df(DF_HALF, pws->h[4], pwt->h[4]);
1196 pwd->h[5] = msa_ceq_df(DF_HALF, pws->h[5], pwt->h[5]);
1197 pwd->h[6] = msa_ceq_df(DF_HALF, pws->h[6], pwt->h[6]);
1198 pwd->h[7] = msa_ceq_df(DF_HALF, pws->h[7], pwt->h[7]);
1199 }
1200
1201 void helper_msa_ceq_w(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
1202 {
1203 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1204 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1205 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1206
1207 pwd->w[0] = msa_ceq_df(DF_WORD, pws->w[0], pwt->w[0]);
1208 pwd->w[1] = msa_ceq_df(DF_WORD, pws->w[1], pwt->w[1]);
1209 pwd->w[2] = msa_ceq_df(DF_WORD, pws->w[2], pwt->w[2]);
1210 pwd->w[3] = msa_ceq_df(DF_WORD, pws->w[3], pwt->w[3]);
1211 }
1212
1213 void helper_msa_ceq_d(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
1214 {
1215 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1216 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1217 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1218
1219 pwd->d[0] = msa_ceq_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
1220 pwd->d[1] = msa_ceq_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
1221 }
1222
1223 static inline int64_t msa_cle_s_df(uint32_t df, int64_t arg1, int64_t arg2)
1224 {
1225 return arg1 <= arg2 ? -1 : 0;
1226 }
1227
1228 void helper_msa_cle_s_b(CPUMIPSState *env,
1229 uint32_t wd, uint32_t ws, uint32_t wt)
1230 {
1231 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1232 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1233 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1234
1235 pwd->b[0] = msa_cle_s_df(DF_BYTE, pws->b[0], pwt->b[0]);
1236 pwd->b[1] = msa_cle_s_df(DF_BYTE, pws->b[1], pwt->b[1]);
1237 pwd->b[2] = msa_cle_s_df(DF_BYTE, pws->b[2], pwt->b[2]);
1238 pwd->b[3] = msa_cle_s_df(DF_BYTE, pws->b[3], pwt->b[3]);
1239 pwd->b[4] = msa_cle_s_df(DF_BYTE, pws->b[4], pwt->b[4]);
1240 pwd->b[5] = msa_cle_s_df(DF_BYTE, pws->b[5], pwt->b[5]);
1241 pwd->b[6] = msa_cle_s_df(DF_BYTE, pws->b[6], pwt->b[6]);
1242 pwd->b[7] = msa_cle_s_df(DF_BYTE, pws->b[7], pwt->b[7]);
1243 pwd->b[8] = msa_cle_s_df(DF_BYTE, pws->b[8], pwt->b[8]);
1244 pwd->b[9] = msa_cle_s_df(DF_BYTE, pws->b[9], pwt->b[9]);
1245 pwd->b[10] = msa_cle_s_df(DF_BYTE, pws->b[10], pwt->b[10]);
1246 pwd->b[11] = msa_cle_s_df(DF_BYTE, pws->b[11], pwt->b[11]);
1247 pwd->b[12] = msa_cle_s_df(DF_BYTE, pws->b[12], pwt->b[12]);
1248 pwd->b[13] = msa_cle_s_df(DF_BYTE, pws->b[13], pwt->b[13]);
1249 pwd->b[14] = msa_cle_s_df(DF_BYTE, pws->b[14], pwt->b[14]);
1250 pwd->b[15] = msa_cle_s_df(DF_BYTE, pws->b[15], pwt->b[15]);
1251 }
1252
1253 void helper_msa_cle_s_h(CPUMIPSState *env,
1254 uint32_t wd, uint32_t ws, uint32_t wt)
1255 {
1256 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1257 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1258 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1259
1260 pwd->h[0] = msa_cle_s_df(DF_HALF, pws->h[0], pwt->h[0]);
1261 pwd->h[1] = msa_cle_s_df(DF_HALF, pws->h[1], pwt->h[1]);
1262 pwd->h[2] = msa_cle_s_df(DF_HALF, pws->h[2], pwt->h[2]);
1263 pwd->h[3] = msa_cle_s_df(DF_HALF, pws->h[3], pwt->h[3]);
1264 pwd->h[4] = msa_cle_s_df(DF_HALF, pws->h[4], pwt->h[4]);
1265 pwd->h[5] = msa_cle_s_df(DF_HALF, pws->h[5], pwt->h[5]);
1266 pwd->h[6] = msa_cle_s_df(DF_HALF, pws->h[6], pwt->h[6]);
1267 pwd->h[7] = msa_cle_s_df(DF_HALF, pws->h[7], pwt->h[7]);
1268 }
1269
1270 void helper_msa_cle_s_w(CPUMIPSState *env,
1271 uint32_t wd, uint32_t ws, uint32_t wt)
1272 {
1273 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1274 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1275 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1276
1277 pwd->w[0] = msa_cle_s_df(DF_WORD, pws->w[0], pwt->w[0]);
1278 pwd->w[1] = msa_cle_s_df(DF_WORD, pws->w[1], pwt->w[1]);
1279 pwd->w[2] = msa_cle_s_df(DF_WORD, pws->w[2], pwt->w[2]);
1280 pwd->w[3] = msa_cle_s_df(DF_WORD, pws->w[3], pwt->w[3]);
1281 }
1282
1283 void helper_msa_cle_s_d(CPUMIPSState *env,
1284 uint32_t wd, uint32_t ws, uint32_t wt)
1285 {
1286 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1287 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1288 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1289
1290 pwd->d[0] = msa_cle_s_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
1291 pwd->d[1] = msa_cle_s_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
1292 }
1293
1294 static inline int64_t msa_cle_u_df(uint32_t df, int64_t arg1, int64_t arg2)
1295 {
1296 uint64_t u_arg1 = UNSIGNED(arg1, df);
1297 uint64_t u_arg2 = UNSIGNED(arg2, df);
1298 return u_arg1 <= u_arg2 ? -1 : 0;
1299 }
1300
1301 void helper_msa_cle_u_b(CPUMIPSState *env,
1302 uint32_t wd, uint32_t ws, uint32_t wt)
1303 {
1304 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1305 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1306 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1307
1308 pwd->b[0] = msa_cle_u_df(DF_BYTE, pws->b[0], pwt->b[0]);
1309 pwd->b[1] = msa_cle_u_df(DF_BYTE, pws->b[1], pwt->b[1]);
1310 pwd->b[2] = msa_cle_u_df(DF_BYTE, pws->b[2], pwt->b[2]);
1311 pwd->b[3] = msa_cle_u_df(DF_BYTE, pws->b[3], pwt->b[3]);
1312 pwd->b[4] = msa_cle_u_df(DF_BYTE, pws->b[4], pwt->b[4]);
1313 pwd->b[5] = msa_cle_u_df(DF_BYTE, pws->b[5], pwt->b[5]);
1314 pwd->b[6] = msa_cle_u_df(DF_BYTE, pws->b[6], pwt->b[6]);
1315 pwd->b[7] = msa_cle_u_df(DF_BYTE, pws->b[7], pwt->b[7]);
1316 pwd->b[8] = msa_cle_u_df(DF_BYTE, pws->b[8], pwt->b[8]);
1317 pwd->b[9] = msa_cle_u_df(DF_BYTE, pws->b[9], pwt->b[9]);
1318 pwd->b[10] = msa_cle_u_df(DF_BYTE, pws->b[10], pwt->b[10]);
1319 pwd->b[11] = msa_cle_u_df(DF_BYTE, pws->b[11], pwt->b[11]);
1320 pwd->b[12] = msa_cle_u_df(DF_BYTE, pws->b[12], pwt->b[12]);
1321 pwd->b[13] = msa_cle_u_df(DF_BYTE, pws->b[13], pwt->b[13]);
1322 pwd->b[14] = msa_cle_u_df(DF_BYTE, pws->b[14], pwt->b[14]);
1323 pwd->b[15] = msa_cle_u_df(DF_BYTE, pws->b[15], pwt->b[15]);
1324 }
1325
1326 void helper_msa_cle_u_h(CPUMIPSState *env,
1327 uint32_t wd, uint32_t ws, uint32_t wt)
1328 {
1329 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1330 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1331 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1332
1333 pwd->h[0] = msa_cle_u_df(DF_HALF, pws->h[0], pwt->h[0]);
1334 pwd->h[1] = msa_cle_u_df(DF_HALF, pws->h[1], pwt->h[1]);
1335 pwd->h[2] = msa_cle_u_df(DF_HALF, pws->h[2], pwt->h[2]);
1336 pwd->h[3] = msa_cle_u_df(DF_HALF, pws->h[3], pwt->h[3]);
1337 pwd->h[4] = msa_cle_u_df(DF_HALF, pws->h[4], pwt->h[4]);
1338 pwd->h[5] = msa_cle_u_df(DF_HALF, pws->h[5], pwt->h[5]);
1339 pwd->h[6] = msa_cle_u_df(DF_HALF, pws->h[6], pwt->h[6]);
1340 pwd->h[7] = msa_cle_u_df(DF_HALF, pws->h[7], pwt->h[7]);
1341 }
1342
1343 void helper_msa_cle_u_w(CPUMIPSState *env,
1344 uint32_t wd, uint32_t ws, uint32_t wt)
1345 {
1346 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1347 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1348 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1349
1350 pwd->w[0] = msa_cle_u_df(DF_WORD, pws->w[0], pwt->w[0]);
1351 pwd->w[1] = msa_cle_u_df(DF_WORD, pws->w[1], pwt->w[1]);
1352 pwd->w[2] = msa_cle_u_df(DF_WORD, pws->w[2], pwt->w[2]);
1353 pwd->w[3] = msa_cle_u_df(DF_WORD, pws->w[3], pwt->w[3]);
1354 }
1355
1356 void helper_msa_cle_u_d(CPUMIPSState *env,
1357 uint32_t wd, uint32_t ws, uint32_t wt)
1358 {
1359 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1360 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1361 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1362
1363 pwd->d[0] = msa_cle_u_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
1364 pwd->d[1] = msa_cle_u_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
1365 }
1366
1367 static inline int64_t msa_clt_s_df(uint32_t df, int64_t arg1, int64_t arg2)
1368 {
1369 return arg1 < arg2 ? -1 : 0;
1370 }
1371
1372 void helper_msa_clt_s_b(CPUMIPSState *env,
1373 uint32_t wd, uint32_t ws, uint32_t wt)
1374 {
1375 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1376 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1377 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1378
1379 pwd->b[0] = msa_clt_s_df(DF_BYTE, pws->b[0], pwt->b[0]);
1380 pwd->b[1] = msa_clt_s_df(DF_BYTE, pws->b[1], pwt->b[1]);
1381 pwd->b[2] = msa_clt_s_df(DF_BYTE, pws->b[2], pwt->b[2]);
1382 pwd->b[3] = msa_clt_s_df(DF_BYTE, pws->b[3], pwt->b[3]);
1383 pwd->b[4] = msa_clt_s_df(DF_BYTE, pws->b[4], pwt->b[4]);
1384 pwd->b[5] = msa_clt_s_df(DF_BYTE, pws->b[5], pwt->b[5]);
1385 pwd->b[6] = msa_clt_s_df(DF_BYTE, pws->b[6], pwt->b[6]);
1386 pwd->b[7] = msa_clt_s_df(DF_BYTE, pws->b[7], pwt->b[7]);
1387 pwd->b[8] = msa_clt_s_df(DF_BYTE, pws->b[8], pwt->b[8]);
1388 pwd->b[9] = msa_clt_s_df(DF_BYTE, pws->b[9], pwt->b[9]);
1389 pwd->b[10] = msa_clt_s_df(DF_BYTE, pws->b[10], pwt->b[10]);
1390 pwd->b[11] = msa_clt_s_df(DF_BYTE, pws->b[11], pwt->b[11]);
1391 pwd->b[12] = msa_clt_s_df(DF_BYTE, pws->b[12], pwt->b[12]);
1392 pwd->b[13] = msa_clt_s_df(DF_BYTE, pws->b[13], pwt->b[13]);
1393 pwd->b[14] = msa_clt_s_df(DF_BYTE, pws->b[14], pwt->b[14]);
1394 pwd->b[15] = msa_clt_s_df(DF_BYTE, pws->b[15], pwt->b[15]);
1395 }
1396
1397 void helper_msa_clt_s_h(CPUMIPSState *env,
1398 uint32_t wd, uint32_t ws, uint32_t wt)
1399 {
1400 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1401 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1402 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1403
1404 pwd->h[0] = msa_clt_s_df(DF_HALF, pws->h[0], pwt->h[0]);
1405 pwd->h[1] = msa_clt_s_df(DF_HALF, pws->h[1], pwt->h[1]);
1406 pwd->h[2] = msa_clt_s_df(DF_HALF, pws->h[2], pwt->h[2]);
1407 pwd->h[3] = msa_clt_s_df(DF_HALF, pws->h[3], pwt->h[3]);
1408 pwd->h[4] = msa_clt_s_df(DF_HALF, pws->h[4], pwt->h[4]);
1409 pwd->h[5] = msa_clt_s_df(DF_HALF, pws->h[5], pwt->h[5]);
1410 pwd->h[6] = msa_clt_s_df(DF_HALF, pws->h[6], pwt->h[6]);
1411 pwd->h[7] = msa_clt_s_df(DF_HALF, pws->h[7], pwt->h[7]);
1412 }
1413
1414 void helper_msa_clt_s_w(CPUMIPSState *env,
1415 uint32_t wd, uint32_t ws, uint32_t wt)
1416 {
1417 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1418 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1419 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1420
1421 pwd->w[0] = msa_clt_s_df(DF_WORD, pws->w[0], pwt->w[0]);
1422 pwd->w[1] = msa_clt_s_df(DF_WORD, pws->w[1], pwt->w[1]);
1423 pwd->w[2] = msa_clt_s_df(DF_WORD, pws->w[2], pwt->w[2]);
1424 pwd->w[3] = msa_clt_s_df(DF_WORD, pws->w[3], pwt->w[3]);
1425 }
1426
1427 void helper_msa_clt_s_d(CPUMIPSState *env,
1428 uint32_t wd, uint32_t ws, uint32_t wt)
1429 {
1430 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1431 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1432 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1433
1434 pwd->d[0] = msa_clt_s_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
1435 pwd->d[1] = msa_clt_s_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
1436 }
1437
1438 static inline int64_t msa_clt_u_df(uint32_t df, int64_t arg1, int64_t arg2)
1439 {
1440 uint64_t u_arg1 = UNSIGNED(arg1, df);
1441 uint64_t u_arg2 = UNSIGNED(arg2, df);
1442 return u_arg1 < u_arg2 ? -1 : 0;
1443 }
1444
1445 void helper_msa_clt_u_b(CPUMIPSState *env,
1446 uint32_t wd, uint32_t ws, uint32_t wt)
1447 {
1448 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1449 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1450 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1451
1452 pwd->b[0] = msa_clt_u_df(DF_BYTE, pws->b[0], pwt->b[0]);
1453 pwd->b[1] = msa_clt_u_df(DF_BYTE, pws->b[1], pwt->b[1]);
1454 pwd->b[2] = msa_clt_u_df(DF_BYTE, pws->b[2], pwt->b[2]);
1455 pwd->b[3] = msa_clt_u_df(DF_BYTE, pws->b[3], pwt->b[3]);
1456 pwd->b[4] = msa_clt_u_df(DF_BYTE, pws->b[4], pwt->b[4]);
1457 pwd->b[5] = msa_clt_u_df(DF_BYTE, pws->b[5], pwt->b[5]);
1458 pwd->b[6] = msa_clt_u_df(DF_BYTE, pws->b[6], pwt->b[6]);
1459 pwd->b[7] = msa_clt_u_df(DF_BYTE, pws->b[7], pwt->b[7]);
1460 pwd->b[8] = msa_clt_u_df(DF_BYTE, pws->b[8], pwt->b[8]);
1461 pwd->b[9] = msa_clt_u_df(DF_BYTE, pws->b[9], pwt->b[9]);
1462 pwd->b[10] = msa_clt_u_df(DF_BYTE, pws->b[10], pwt->b[10]);
1463 pwd->b[11] = msa_clt_u_df(DF_BYTE, pws->b[11], pwt->b[11]);
1464 pwd->b[12] = msa_clt_u_df(DF_BYTE, pws->b[12], pwt->b[12]);
1465 pwd->b[13] = msa_clt_u_df(DF_BYTE, pws->b[13], pwt->b[13]);
1466 pwd->b[14] = msa_clt_u_df(DF_BYTE, pws->b[14], pwt->b[14]);
1467 pwd->b[15] = msa_clt_u_df(DF_BYTE, pws->b[15], pwt->b[15]);
1468 }
1469
1470 void helper_msa_clt_u_h(CPUMIPSState *env,
1471 uint32_t wd, uint32_t ws, uint32_t wt)
1472 {
1473 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1474 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1475 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1476
1477 pwd->h[0] = msa_clt_u_df(DF_HALF, pws->h[0], pwt->h[0]);
1478 pwd->h[1] = msa_clt_u_df(DF_HALF, pws->h[1], pwt->h[1]);
1479 pwd->h[2] = msa_clt_u_df(DF_HALF, pws->h[2], pwt->h[2]);
1480 pwd->h[3] = msa_clt_u_df(DF_HALF, pws->h[3], pwt->h[3]);
1481 pwd->h[4] = msa_clt_u_df(DF_HALF, pws->h[4], pwt->h[4]);
1482 pwd->h[5] = msa_clt_u_df(DF_HALF, pws->h[5], pwt->h[5]);
1483 pwd->h[6] = msa_clt_u_df(DF_HALF, pws->h[6], pwt->h[6]);
1484 pwd->h[7] = msa_clt_u_df(DF_HALF, pws->h[7], pwt->h[7]);
1485 }
1486
1487 void helper_msa_clt_u_w(CPUMIPSState *env,
1488 uint32_t wd, uint32_t ws, uint32_t wt)
1489 {
1490 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1491 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1492 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1493
1494 pwd->w[0] = msa_clt_u_df(DF_WORD, pws->w[0], pwt->w[0]);
1495 pwd->w[1] = msa_clt_u_df(DF_WORD, pws->w[1], pwt->w[1]);
1496 pwd->w[2] = msa_clt_u_df(DF_WORD, pws->w[2], pwt->w[2]);
1497 pwd->w[3] = msa_clt_u_df(DF_WORD, pws->w[3], pwt->w[3]);
1498 }
1499
1500 void helper_msa_clt_u_d(CPUMIPSState *env,
1501 uint32_t wd, uint32_t ws, uint32_t wt)
1502 {
1503 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1504 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1505 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1506
1507 pwd->d[0] = msa_clt_u_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
1508 pwd->d[1] = msa_clt_u_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
1509 }
1510
1511
1512 /*
1513 * Int Divide
1514 * ----------
1515 *
1516 * +---------------+----------------------------------------------------------+
1517 * | DIV_S.B | Vector Signed Divide (byte) |
1518 * | DIV_S.H | Vector Signed Divide (halfword) |
1519 * | DIV_S.W | Vector Signed Divide (word) |
1520 * | DIV_S.D | Vector Signed Divide (doubleword) |
1521 * | DIV_U.B | Vector Unsigned Divide (byte) |
1522 * | DIV_U.H | Vector Unsigned Divide (halfword) |
1523 * | DIV_U.W | Vector Unsigned Divide (word) |
1524 * | DIV_U.D | Vector Unsigned Divide (doubleword) |
1525 * +---------------+----------------------------------------------------------+
1526 */
1527
1528
1529 static inline int64_t msa_div_s_df(uint32_t df, int64_t arg1, int64_t arg2)
1530 {
1531 if (arg1 == DF_MIN_INT(df) && arg2 == -1) {
1532 return DF_MIN_INT(df);
1533 }
1534 return arg2 ? arg1 / arg2
1535 : arg1 >= 0 ? -1 : 1;
1536 }
1537
1538 void helper_msa_div_s_b(CPUMIPSState *env,
1539 uint32_t wd, uint32_t ws, uint32_t wt)
1540 {
1541 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1542 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1543 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1544
1545 pwd->b[0] = msa_div_s_df(DF_BYTE, pws->b[0], pwt->b[0]);
1546 pwd->b[1] = msa_div_s_df(DF_BYTE, pws->b[1], pwt->b[1]);
1547 pwd->b[2] = msa_div_s_df(DF_BYTE, pws->b[2], pwt->b[2]);
1548 pwd->b[3] = msa_div_s_df(DF_BYTE, pws->b[3], pwt->b[3]);
1549 pwd->b[4] = msa_div_s_df(DF_BYTE, pws->b[4], pwt->b[4]);
1550 pwd->b[5] = msa_div_s_df(DF_BYTE, pws->b[5], pwt->b[5]);
1551 pwd->b[6] = msa_div_s_df(DF_BYTE, pws->b[6], pwt->b[6]);
1552 pwd->b[7] = msa_div_s_df(DF_BYTE, pws->b[7], pwt->b[7]);
1553 pwd->b[8] = msa_div_s_df(DF_BYTE, pws->b[8], pwt->b[8]);
1554 pwd->b[9] = msa_div_s_df(DF_BYTE, pws->b[9], pwt->b[9]);
1555 pwd->b[10] = msa_div_s_df(DF_BYTE, pws->b[10], pwt->b[10]);
1556 pwd->b[11] = msa_div_s_df(DF_BYTE, pws->b[11], pwt->b[11]);
1557 pwd->b[12] = msa_div_s_df(DF_BYTE, pws->b[12], pwt->b[12]);
1558 pwd->b[13] = msa_div_s_df(DF_BYTE, pws->b[13], pwt->b[13]);
1559 pwd->b[14] = msa_div_s_df(DF_BYTE, pws->b[14], pwt->b[14]);
1560 pwd->b[15] = msa_div_s_df(DF_BYTE, pws->b[15], pwt->b[15]);
1561 }
1562
1563 void helper_msa_div_s_h(CPUMIPSState *env,
1564 uint32_t wd, uint32_t ws, uint32_t wt)
1565 {
1566 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1567 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1568 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1569
1570 pwd->h[0] = msa_div_s_df(DF_HALF, pws->h[0], pwt->h[0]);
1571 pwd->h[1] = msa_div_s_df(DF_HALF, pws->h[1], pwt->h[1]);
1572 pwd->h[2] = msa_div_s_df(DF_HALF, pws->h[2], pwt->h[2]);
1573 pwd->h[3] = msa_div_s_df(DF_HALF, pws->h[3], pwt->h[3]);
1574 pwd->h[4] = msa_div_s_df(DF_HALF, pws->h[4], pwt->h[4]);
1575 pwd->h[5] = msa_div_s_df(DF_HALF, pws->h[5], pwt->h[5]);
1576 pwd->h[6] = msa_div_s_df(DF_HALF, pws->h[6], pwt->h[6]);
1577 pwd->h[7] = msa_div_s_df(DF_HALF, pws->h[7], pwt->h[7]);
1578 }
1579
1580 void helper_msa_div_s_w(CPUMIPSState *env,
1581 uint32_t wd, uint32_t ws, uint32_t wt)
1582 {
1583 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1584 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1585 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1586
1587 pwd->w[0] = msa_div_s_df(DF_WORD, pws->w[0], pwt->w[0]);
1588 pwd->w[1] = msa_div_s_df(DF_WORD, pws->w[1], pwt->w[1]);
1589 pwd->w[2] = msa_div_s_df(DF_WORD, pws->w[2], pwt->w[2]);
1590 pwd->w[3] = msa_div_s_df(DF_WORD, pws->w[3], pwt->w[3]);
1591 }
1592
1593 void helper_msa_div_s_d(CPUMIPSState *env,
1594 uint32_t wd, uint32_t ws, uint32_t wt)
1595 {
1596 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1597 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1598 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1599
1600 pwd->d[0] = msa_div_s_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
1601 pwd->d[1] = msa_div_s_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
1602 }
1603
1604 static inline int64_t msa_div_u_df(uint32_t df, int64_t arg1, int64_t arg2)
1605 {
1606 uint64_t u_arg1 = UNSIGNED(arg1, df);
1607 uint64_t u_arg2 = UNSIGNED(arg2, df);
1608 return arg2 ? u_arg1 / u_arg2 : -1;
1609 }
1610
1611 void helper_msa_div_u_b(CPUMIPSState *env,
1612 uint32_t wd, uint32_t ws, uint32_t wt)
1613 {
1614 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1615 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1616 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1617
1618 pwd->b[0] = msa_div_u_df(DF_BYTE, pws->b[0], pwt->b[0]);
1619 pwd->b[1] = msa_div_u_df(DF_BYTE, pws->b[1], pwt->b[1]);
1620 pwd->b[2] = msa_div_u_df(DF_BYTE, pws->b[2], pwt->b[2]);
1621 pwd->b[3] = msa_div_u_df(DF_BYTE, pws->b[3], pwt->b[3]);
1622 pwd->b[4] = msa_div_u_df(DF_BYTE, pws->b[4], pwt->b[4]);
1623 pwd->b[5] = msa_div_u_df(DF_BYTE, pws->b[5], pwt->b[5]);
1624 pwd->b[6] = msa_div_u_df(DF_BYTE, pws->b[6], pwt->b[6]);
1625 pwd->b[7] = msa_div_u_df(DF_BYTE, pws->b[7], pwt->b[7]);
1626 pwd->b[8] = msa_div_u_df(DF_BYTE, pws->b[8], pwt->b[8]);
1627 pwd->b[9] = msa_div_u_df(DF_BYTE, pws->b[9], pwt->b[9]);
1628 pwd->b[10] = msa_div_u_df(DF_BYTE, pws->b[10], pwt->b[10]);
1629 pwd->b[11] = msa_div_u_df(DF_BYTE, pws->b[11], pwt->b[11]);
1630 pwd->b[12] = msa_div_u_df(DF_BYTE, pws->b[12], pwt->b[12]);
1631 pwd->b[13] = msa_div_u_df(DF_BYTE, pws->b[13], pwt->b[13]);
1632 pwd->b[14] = msa_div_u_df(DF_BYTE, pws->b[14], pwt->b[14]);
1633 pwd->b[15] = msa_div_u_df(DF_BYTE, pws->b[15], pwt->b[15]);
1634 }
1635
1636 void helper_msa_div_u_h(CPUMIPSState *env,
1637 uint32_t wd, uint32_t ws, uint32_t wt)
1638 {
1639 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1640 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1641 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1642
1643 pwd->h[0] = msa_div_u_df(DF_HALF, pws->h[0], pwt->h[0]);
1644 pwd->h[1] = msa_div_u_df(DF_HALF, pws->h[1], pwt->h[1]);
1645 pwd->h[2] = msa_div_u_df(DF_HALF, pws->h[2], pwt->h[2]);
1646 pwd->h[3] = msa_div_u_df(DF_HALF, pws->h[3], pwt->h[3]);
1647 pwd->h[4] = msa_div_u_df(DF_HALF, pws->h[4], pwt->h[4]);
1648 pwd->h[5] = msa_div_u_df(DF_HALF, pws->h[5], pwt->h[5]);
1649 pwd->h[6] = msa_div_u_df(DF_HALF, pws->h[6], pwt->h[6]);
1650 pwd->h[7] = msa_div_u_df(DF_HALF, pws->h[7], pwt->h[7]);
1651 }
1652
1653 void helper_msa_div_u_w(CPUMIPSState *env,
1654 uint32_t wd, uint32_t ws, uint32_t wt)
1655 {
1656 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1657 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1658 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1659
1660 pwd->w[0] = msa_div_u_df(DF_WORD, pws->w[0], pwt->w[0]);
1661 pwd->w[1] = msa_div_u_df(DF_WORD, pws->w[1], pwt->w[1]);
1662 pwd->w[2] = msa_div_u_df(DF_WORD, pws->w[2], pwt->w[2]);
1663 pwd->w[3] = msa_div_u_df(DF_WORD, pws->w[3], pwt->w[3]);
1664 }
1665
1666 void helper_msa_div_u_d(CPUMIPSState *env,
1667 uint32_t wd, uint32_t ws, uint32_t wt)
1668 {
1669 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1670 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1671 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1672
1673 pwd->d[0] = msa_div_u_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
1674 pwd->d[1] = msa_div_u_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
1675 }
1676
1677
1678 /*
1679 * Int Dot Product
1680 * ---------------
1681 *
1682 * +---------------+----------------------------------------------------------+
1683 * | DOTP_S.H | Vector Signed Dot Product (halfword) |
1684 * | DOTP_S.W | Vector Signed Dot Product (word) |
1685 * | DOTP_S.D | Vector Signed Dot Product (doubleword) |
1686 * | DOTP_U.H | Vector Unsigned Dot Product (halfword) |
1687 * | DOTP_U.W | Vector Unsigned Dot Product (word) |
1688 * | DOTP_U.D | Vector Unsigned Dot Product (doubleword) |
1689 * | DPADD_S.H | Vector Signed Dot Product (halfword) |
1690 * | DPADD_S.W | Vector Signed Dot Product (word) |
1691 * | DPADD_S.D | Vector Signed Dot Product (doubleword) |
1692 * | DPADD_U.H | Vector Unsigned Dot Product (halfword) |
1693 * | DPADD_U.W | Vector Unsigned Dot Product (word) |
1694 * | DPADD_U.D | Vector Unsigned Dot Product (doubleword) |
1695 * | DPSUB_S.H | Vector Signed Dot Product (halfword) |
1696 * | DPSUB_S.W | Vector Signed Dot Product (word) |
1697 * | DPSUB_S.D | Vector Signed Dot Product (doubleword) |
1698 * | DPSUB_U.H | Vector Unsigned Dot Product (halfword) |
1699 * | DPSUB_U.W | Vector Unsigned Dot Product (word) |
1700 * | DPSUB_U.D | Vector Unsigned Dot Product (doubleword) |
1701 * +---------------+----------------------------------------------------------+
1702 */
1703
1704 /* TODO: insert Int Dot Product group helpers here */
1705
1706
1707 /*
1708 * Int Max Min
1709 * -----------
1710 *
1711 * +---------------+----------------------------------------------------------+
1712 * | MAX_A.B | Vector Maximum Based on Absolute Value (byte) |
1713 * | MAX_A.H | Vector Maximum Based on Absolute Value (halfword) |
1714 * | MAX_A.W | Vector Maximum Based on Absolute Value (word) |
1715 * | MAX_A.D | Vector Maximum Based on Absolute Value (doubleword) |
1716 * | MAX_S.B | Vector Signed Maximum (byte) |
1717 * | MAX_S.H | Vector Signed Maximum (halfword) |
1718 * | MAX_S.W | Vector Signed Maximum (word) |
1719 * | MAX_S.D | Vector Signed Maximum (doubleword) |
1720 * | MAX_U.B | Vector Unsigned Maximum (byte) |
1721 * | MAX_U.H | Vector Unsigned Maximum (halfword) |
1722 * | MAX_U.W | Vector Unsigned Maximum (word) |
1723 * | MAX_U.D | Vector Unsigned Maximum (doubleword) |
1724 * | MIN_A.B | Vector Minimum Based on Absolute Value (byte) |
1725 * | MIN_A.H | Vector Minimum Based on Absolute Value (halfword) |
1726 * | MIN_A.W | Vector Minimum Based on Absolute Value (word) |
1727 * | MIN_A.D | Vector Minimum Based on Absolute Value (doubleword) |
1728 * | MIN_S.B | Vector Signed Minimum (byte) |
1729 * | MIN_S.H | Vector Signed Minimum (halfword) |
1730 * | MIN_S.W | Vector Signed Minimum (word) |
1731 * | MIN_S.D | Vector Signed Minimum (doubleword) |
1732 * | MIN_U.B | Vector Unsigned Minimum (byte) |
1733 * | MIN_U.H | Vector Unsigned Minimum (halfword) |
1734 * | MIN_U.W | Vector Unsigned Minimum (word) |
1735 * | MIN_U.D | Vector Unsigned Minimum (doubleword) |
1736 * +---------------+----------------------------------------------------------+
1737 */
1738
1739 /* TODO: insert Int Max Min group helpers here */
1740
1741
1742 /*
1743 * Int Modulo
1744 * ----------
1745 *
1746 * +---------------+----------------------------------------------------------+
1747 * | MOD_S.B | Vector Signed Modulo (byte) |
1748 * | MOD_S.H | Vector Signed Modulo (halfword) |
1749 * | MOD_S.W | Vector Signed Modulo (word) |
1750 * | MOD_S.D | Vector Signed Modulo (doubleword) |
1751 * | MOD_U.B | Vector Unsigned Modulo (byte) |
1752 * | MOD_U.H | Vector Unsigned Modulo (halfword) |
1753 * | MOD_U.W | Vector Unsigned Modulo (word) |
1754 * | MOD_U.D | Vector Unsigned Modulo (doubleword) |
1755 * +---------------+----------------------------------------------------------+
1756 */
1757
1758 static inline int64_t msa_mod_s_df(uint32_t df, int64_t arg1, int64_t arg2)
1759 {
1760 if (arg1 == DF_MIN_INT(df) && arg2 == -1) {
1761 return 0;
1762 }
1763 return arg2 ? arg1 % arg2 : arg1;
1764 }
1765
1766 void helper_msa_mod_s_b(CPUMIPSState *env,
1767 uint32_t wd, uint32_t ws, uint32_t wt)
1768 {
1769 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1770 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1771 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1772
1773 pwd->b[0] = msa_mod_s_df(DF_BYTE, pws->b[0], pwt->b[0]);
1774 pwd->b[1] = msa_mod_s_df(DF_BYTE, pws->b[1], pwt->b[1]);
1775 pwd->b[2] = msa_mod_s_df(DF_BYTE, pws->b[2], pwt->b[2]);
1776 pwd->b[3] = msa_mod_s_df(DF_BYTE, pws->b[3], pwt->b[3]);
1777 pwd->b[4] = msa_mod_s_df(DF_BYTE, pws->b[4], pwt->b[4]);
1778 pwd->b[5] = msa_mod_s_df(DF_BYTE, pws->b[5], pwt->b[5]);
1779 pwd->b[6] = msa_mod_s_df(DF_BYTE, pws->b[6], pwt->b[6]);
1780 pwd->b[7] = msa_mod_s_df(DF_BYTE, pws->b[7], pwt->b[7]);
1781 pwd->b[8] = msa_mod_s_df(DF_BYTE, pws->b[8], pwt->b[8]);
1782 pwd->b[9] = msa_mod_s_df(DF_BYTE, pws->b[9], pwt->b[9]);
1783 pwd->b[10] = msa_mod_s_df(DF_BYTE, pws->b[10], pwt->b[10]);
1784 pwd->b[11] = msa_mod_s_df(DF_BYTE, pws->b[11], pwt->b[11]);
1785 pwd->b[12] = msa_mod_s_df(DF_BYTE, pws->b[12], pwt->b[12]);
1786 pwd->b[13] = msa_mod_s_df(DF_BYTE, pws->b[13], pwt->b[13]);
1787 pwd->b[14] = msa_mod_s_df(DF_BYTE, pws->b[14], pwt->b[14]);
1788 pwd->b[15] = msa_mod_s_df(DF_BYTE, pws->b[15], pwt->b[15]);
1789 }
1790
1791 void helper_msa_mod_s_h(CPUMIPSState *env,
1792 uint32_t wd, uint32_t ws, uint32_t wt)
1793 {
1794 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1795 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1796 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1797
1798 pwd->h[0] = msa_mod_s_df(DF_HALF, pws->h[0], pwt->h[0]);
1799 pwd->h[1] = msa_mod_s_df(DF_HALF, pws->h[1], pwt->h[1]);
1800 pwd->h[2] = msa_mod_s_df(DF_HALF, pws->h[2], pwt->h[2]);
1801 pwd->h[3] = msa_mod_s_df(DF_HALF, pws->h[3], pwt->h[3]);
1802 pwd->h[4] = msa_mod_s_df(DF_HALF, pws->h[4], pwt->h[4]);
1803 pwd->h[5] = msa_mod_s_df(DF_HALF, pws->h[5], pwt->h[5]);
1804 pwd->h[6] = msa_mod_s_df(DF_HALF, pws->h[6], pwt->h[6]);
1805 pwd->h[7] = msa_mod_s_df(DF_HALF, pws->h[7], pwt->h[7]);
1806 }
1807
1808 void helper_msa_mod_s_w(CPUMIPSState *env,
1809 uint32_t wd, uint32_t ws, uint32_t wt)
1810 {
1811 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1812 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1813 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1814
1815 pwd->w[0] = msa_mod_s_df(DF_WORD, pws->w[0], pwt->w[0]);
1816 pwd->w[1] = msa_mod_s_df(DF_WORD, pws->w[1], pwt->w[1]);
1817 pwd->w[2] = msa_mod_s_df(DF_WORD, pws->w[2], pwt->w[2]);
1818 pwd->w[3] = msa_mod_s_df(DF_WORD, pws->w[3], pwt->w[3]);
1819 }
1820
1821 void helper_msa_mod_s_d(CPUMIPSState *env,
1822 uint32_t wd, uint32_t ws, uint32_t wt)
1823 {
1824 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1825 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1826 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1827
1828 pwd->d[0] = msa_mod_s_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
1829 pwd->d[1] = msa_mod_s_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
1830 }
1831
1832 static inline int64_t msa_mod_u_df(uint32_t df, int64_t arg1, int64_t arg2)
1833 {
1834 uint64_t u_arg1 = UNSIGNED(arg1, df);
1835 uint64_t u_arg2 = UNSIGNED(arg2, df);
1836 return u_arg2 ? u_arg1 % u_arg2 : u_arg1;
1837 }
1838
1839 void helper_msa_mod_u_b(CPUMIPSState *env,
1840 uint32_t wd, uint32_t ws, uint32_t wt)
1841 {
1842 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1843 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1844 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1845
1846 pwd->b[0] = msa_mod_u_df(DF_BYTE, pws->b[0], pwt->b[0]);
1847 pwd->b[1] = msa_mod_u_df(DF_BYTE, pws->b[1], pwt->b[1]);
1848 pwd->b[2] = msa_mod_u_df(DF_BYTE, pws->b[2], pwt->b[2]);
1849 pwd->b[3] = msa_mod_u_df(DF_BYTE, pws->b[3], pwt->b[3]);
1850 pwd->b[4] = msa_mod_u_df(DF_BYTE, pws->b[4], pwt->b[4]);
1851 pwd->b[5] = msa_mod_u_df(DF_BYTE, pws->b[5], pwt->b[5]);
1852 pwd->b[6] = msa_mod_u_df(DF_BYTE, pws->b[6], pwt->b[6]);
1853 pwd->b[7] = msa_mod_u_df(DF_BYTE, pws->b[7], pwt->b[7]);
1854 pwd->b[8] = msa_mod_u_df(DF_BYTE, pws->b[8], pwt->b[8]);
1855 pwd->b[9] = msa_mod_u_df(DF_BYTE, pws->b[9], pwt->b[9]);
1856 pwd->b[10] = msa_mod_u_df(DF_BYTE, pws->b[10], pwt->b[10]);
1857 pwd->b[11] = msa_mod_u_df(DF_BYTE, pws->b[11], pwt->b[11]);
1858 pwd->b[12] = msa_mod_u_df(DF_BYTE, pws->b[12], pwt->b[12]);
1859 pwd->b[13] = msa_mod_u_df(DF_BYTE, pws->b[13], pwt->b[13]);
1860 pwd->b[14] = msa_mod_u_df(DF_BYTE, pws->b[14], pwt->b[14]);
1861 pwd->b[15] = msa_mod_u_df(DF_BYTE, pws->b[15], pwt->b[15]);
1862 }
1863
1864 void helper_msa_mod_u_h(CPUMIPSState *env,
1865 uint32_t wd, uint32_t ws, uint32_t wt)
1866 {
1867 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1868 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1869 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1870
1871 pwd->h[0] = msa_mod_u_df(DF_HALF, pws->h[0], pwt->h[0]);
1872 pwd->h[1] = msa_mod_u_df(DF_HALF, pws->h[1], pwt->h[1]);
1873 pwd->h[2] = msa_mod_u_df(DF_HALF, pws->h[2], pwt->h[2]);
1874 pwd->h[3] = msa_mod_u_df(DF_HALF, pws->h[3], pwt->h[3]);
1875 pwd->h[4] = msa_mod_u_df(DF_HALF, pws->h[4], pwt->h[4]);
1876 pwd->h[5] = msa_mod_u_df(DF_HALF, pws->h[5], pwt->h[5]);
1877 pwd->h[6] = msa_mod_u_df(DF_HALF, pws->h[6], pwt->h[6]);
1878 pwd->h[7] = msa_mod_u_df(DF_HALF, pws->h[7], pwt->h[7]);
1879 }
1880
1881 void helper_msa_mod_u_w(CPUMIPSState *env,
1882 uint32_t wd, uint32_t ws, uint32_t wt)
1883 {
1884 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1885 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1886 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1887
1888 pwd->w[0] = msa_mod_u_df(DF_WORD, pws->w[0], pwt->w[0]);
1889 pwd->w[1] = msa_mod_u_df(DF_WORD, pws->w[1], pwt->w[1]);
1890 pwd->w[2] = msa_mod_u_df(DF_WORD, pws->w[2], pwt->w[2]);
1891 pwd->w[3] = msa_mod_u_df(DF_WORD, pws->w[3], pwt->w[3]);
1892 }
1893
1894 void helper_msa_mod_u_d(CPUMIPSState *env,
1895 uint32_t wd, uint32_t ws, uint32_t wt)
1896 {
1897 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1898 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1899 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1900
1901 pwd->d[0] = msa_mod_u_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
1902 pwd->d[1] = msa_mod_u_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
1903 }
1904
1905
1906 /*
1907 * Int Multiply
1908 * ------------
1909 *
1910 * +---------------+----------------------------------------------------------+
1911 * | MADDV.B | Vector Multiply and Add (byte) |
1912 * | MADDV.H | Vector Multiply and Add (halfword) |
1913 * | MADDV.W | Vector Multiply and Add (word) |
1914 * | MADDV.D | Vector Multiply and Add (doubleword) |
1915 * | MSUBV.B | Vector Multiply and Subtract (byte) |
1916 * | MSUBV.H | Vector Multiply and Subtract (halfword) |
1917 * | MSUBV.W | Vector Multiply and Subtract (word) |
1918 * | MSUBV.D | Vector Multiply and Subtract (doubleword) |
1919 * | MULV.B | Vector Multiply (byte) |
1920 * | MULV.H | Vector Multiply (halfword) |
1921 * | MULV.W | Vector Multiply (word) |
1922 * | MULV.D | Vector Multiply (doubleword) |
1923 * +---------------+----------------------------------------------------------+
1924 */
1925
1926 /* TODO: insert Int Multiply group helpers here */
1927
1928
1929 /*
1930 * Int Subtract
1931 * ------------
1932 *
1933 * +---------------+----------------------------------------------------------+
1934 * | ASUB_S.B | Vector Absolute Values of Signed Subtract (byte) |
1935 * | ASUB_S.H | Vector Absolute Values of Signed Subtract (halfword) |
1936 * | ASUB_S.W | Vector Absolute Values of Signed Subtract (word) |
1937 * | ASUB_S.D | Vector Absolute Values of Signed Subtract (doubleword) |
1938 * | ASUB_U.B | Vector Absolute Values of Unsigned Subtract (byte) |
1939 * | ASUB_U.H | Vector Absolute Values of Unsigned Subtract (halfword) |
1940 * | ASUB_U.W | Vector Absolute Values of Unsigned Subtract (word) |
1941 * | ASUB_U.D | Vector Absolute Values of Unsigned Subtract (doubleword) |
1942 * | HSUB_S.H | Vector Signed Horizontal Subtract (halfword) |
1943 * | HSUB_S.W | Vector Signed Horizontal Subtract (word) |
1944 * | HSUB_S.D | Vector Signed Horizontal Subtract (doubleword) |
1945 * | HSUB_U.H | Vector Unigned Horizontal Subtract (halfword) |
1946 * | HSUB_U.W | Vector Unigned Horizontal Subtract (word) |
1947 * | HSUB_U.D | Vector Unigned Horizontal Subtract (doubleword) |
1948 * | SUBS_S.B | Vector Signed Saturated Subtract (of Signed) (byte) |
1949 * | SUBS_S.H | Vector Signed Saturated Subtract (of Signed) (halfword) |
1950 * | SUBS_S.W | Vector Signed Saturated Subtract (of Signed) (word) |
1951 * | SUBS_S.D | Vector Signed Saturated Subtract (of Signed) (doubleword)|
1952 * | SUBS_U.B | Vector Unsigned Saturated Subtract (of Uns.) (byte) |
1953 * | SUBS_U.H | Vector Unsigned Saturated Subtract (of Uns.) (halfword) |
1954 * | SUBS_U.W | Vector Unsigned Saturated Subtract (of Uns.) (word) |
1955 * | SUBS_U.D | Vector Unsigned Saturated Subtract (of Uns.) (doubleword)|
1956 * | SUBSUS_U.B | Vector Uns. Sat. Subtract (of S. from Uns.) (byte) |
1957 * | SUBSUS_U.H | Vector Uns. Sat. Subtract (of S. from Uns.) (halfword) |
1958 * | SUBSUS_U.W | Vector Uns. Sat. Subtract (of S. from Uns.) (word) |
1959 * | SUBSUS_U.D | Vector Uns. Sat. Subtract (of S. from Uns.) (doubleword) |
1960 * | SUBSUU_S.B | Vector Signed Saturated Subtract (of Uns.) (byte) |
1961 * | SUBSUU_S.H | Vector Signed Saturated Subtract (of Uns.) (halfword) |
1962 * | SUBSUU_S.W | Vector Signed Saturated Subtract (of Uns.) (word) |
1963 * | SUBSUU_S.D | Vector Signed Saturated Subtract (of Uns.) (doubleword) |
1964 * | SUBV.B | Vector Subtract (byte) |
1965 * | SUBV.H | Vector Subtract (halfword) |
1966 * | SUBV.W | Vector Subtract (word) |
1967 * | SUBV.D | Vector Subtract (doubleword) |
1968 * +---------------+----------------------------------------------------------+
1969 */
1970
1971 /* TODO: insert Int Subtract group helpers here */
1972
1973
1974 /*
1975 * Interleave
1976 * ----------
1977 *
1978 * +---------------+----------------------------------------------------------+
1979 * | ILVEV.B | Vector Interleave Even (byte) |
1980 * | ILVEV.H | Vector Interleave Even (halfword) |
1981 * | ILVEV.W | Vector Interleave Even (word) |
1982 * | ILVEV.D | Vector Interleave Even (doubleword) |
1983 * | ILVOD.B | Vector Interleave Odd (byte) |
1984 * | ILVOD.H | Vector Interleave Odd (halfword) |
1985 * | ILVOD.W | Vector Interleave Odd (word) |
1986 * | ILVOD.D | Vector Interleave Odd (doubleword) |
1987 * | ILVL.B | Vector Interleave Left (byte) |
1988 * | ILVL.H | Vector Interleave Left (halfword) |
1989 * | ILVL.W | Vector Interleave Left (word) |
1990 * | ILVL.D | Vector Interleave Left (doubleword) |
1991 * | ILVR.B | Vector Interleave Right (byte) |
1992 * | ILVR.H | Vector Interleave Right (halfword) |
1993 * | ILVR.W | Vector Interleave Right (word) |
1994 * | ILVR.D | Vector Interleave Right (doubleword) |
1995 * +---------------+----------------------------------------------------------+
1996 */
1997
1998 /* TODO: insert Interleave group helpers here */
1999
2000
2001 /*
2002 * Logic
2003 * -----
2004 *
2005 * +---------------+----------------------------------------------------------+
2006 * | AND.V | Vector Logical And |
2007 * | NOR.V | Vector Logical Negated Or |
2008 * | OR.V | Vector Logical Or |
2009 * | XOR.V | Vector Logical Exclusive Or |
2010 * +---------------+----------------------------------------------------------+
2011 */
2012
2013
2014 void helper_msa_and_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
2015 {
2016 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2017 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2018 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2019
2020 pwd->d[0] = pws->d[0] & pwt->d[0];
2021 pwd->d[1] = pws->d[1] & pwt->d[1];
2022 }
2023
2024 void helper_msa_nor_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
2025 {
2026 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2027 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2028 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2029
2030 pwd->d[0] = ~(pws->d[0] | pwt->d[0]);
2031 pwd->d[1] = ~(pws->d[1] | pwt->d[1]);
2032 }
2033
2034 void helper_msa_or_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
2035 {
2036 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2037 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2038 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2039
2040 pwd->d[0] = pws->d[0] | pwt->d[0];
2041 pwd->d[1] = pws->d[1] | pwt->d[1];
2042 }
2043
2044 void helper_msa_xor_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
2045 {
2046 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2047 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2048 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2049
2050 pwd->d[0] = pws->d[0] ^ pwt->d[0];
2051 pwd->d[1] = pws->d[1] ^ pwt->d[1];
2052 }
2053
2054
2055 /*
2056 * Move
2057 * ----
2058 *
2059 * +---------------+----------------------------------------------------------+
2060 * | MOVE.V | Vector Move |
2061 * +---------------+----------------------------------------------------------+
2062 */
2063
2064 static inline void msa_move_v(wr_t *pwd, wr_t *pws)
2065 {
2066 pwd->d[0] = pws->d[0];
2067 pwd->d[1] = pws->d[1];
2068 }
2069
2070 void helper_msa_move_v(CPUMIPSState *env, uint32_t wd, uint32_t ws)
2071 {
2072 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2073 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2074
2075 msa_move_v(pwd, pws);
2076 }
2077
2078
2079 /*
2080 * Pack
2081 * ----
2082 *
2083 * +---------------+----------------------------------------------------------+
2084 * | PCKEV.B | Vector Pack Even (byte) |
2085 * | PCKEV.H | Vector Pack Even (halfword) |
2086 * | PCKEV.W | Vector Pack Even (word) |
2087 * | PCKEV.D | Vector Pack Even (doubleword) |
2088 * | PCKOD.B | Vector Pack Odd (byte) |
2089 * | PCKOD.H | Vector Pack Odd (halfword) |
2090 * | PCKOD.W | Vector Pack Odd (word) |
2091 * | PCKOD.D | Vector Pack Odd (doubleword) |
2092 * | VSHF.B | Vector Data Preserving Shuffle (byte) |
2093 * | VSHF.H | Vector Data Preserving Shuffle (halfword) |
2094 * | VSHF.W | Vector Data Preserving Shuffle (word) |
2095 * | VSHF.D | Vector Data Preserving Shuffle (doubleword) |
2096 * +---------------+----------------------------------------------------------+
2097 */
2098
2099 /* TODO: insert Pack group helpers here */
2100
2101
2102 /*
2103 * Shift
2104 * -----
2105 *
2106 * +---------------+----------------------------------------------------------+
2107 * | SLL.B | Vector Shift Left (byte) |
2108 * | SLL.H | Vector Shift Left (halfword) |
2109 * | SLL.W | Vector Shift Left (word) |
2110 * | SLL.D | Vector Shift Left (doubleword) |
2111 * | SRA.B | Vector Shift Right Arithmetic (byte) |
2112 * | SRA.H | Vector Shift Right Arithmetic (halfword) |
2113 * | SRA.W | Vector Shift Right Arithmetic (word) |
2114 * | SRA.D | Vector Shift Right Arithmetic (doubleword) |
2115 * | SRAR.B | Vector Shift Right Arithmetic Rounded (byte) |
2116 * | SRAR.H | Vector Shift Right Arithmetic Rounded (halfword) |
2117 * | SRAR.W | Vector Shift Right Arithmetic Rounded (word) |
2118 * | SRAR.D | Vector Shift Right Arithmetic Rounded (doubleword) |
2119 * | SRL.B | Vector Shift Right Logical (byte) |
2120 * | SRL.H | Vector Shift Right Logical (halfword) |
2121 * | SRL.W | Vector Shift Right Logical (word) |
2122 * | SRL.D | Vector Shift Right Logical (doubleword) |
2123 * | SRLR.B | Vector Shift Right Logical Rounded (byte) |
2124 * | SRLR.H | Vector Shift Right Logical Rounded (halfword) |
2125 * | SRLR.W | Vector Shift Right Logical Rounded (word) |
2126 * | SRLR.D | Vector Shift Right Logical Rounded (doubleword) |
2127 * +---------------+----------------------------------------------------------+
2128 */
2129
2130 /* TODO: insert Shift group helpers here */
2131
2132
2133 #define MSA_FN_IMM8(FUNC, DEST, OPERATION) \
2134 void helper_msa_ ## FUNC(CPUMIPSState *env, uint32_t wd, uint32_t ws, \
2135 uint32_t i8) \
2136 { \
2137 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
2138 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
2139 uint32_t i; \
2140 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
2141 DEST = OPERATION; \
2142 } \
2143 }
2144
2145 MSA_FN_IMM8(andi_b, pwd->b[i], pws->b[i] & i8)
2146 MSA_FN_IMM8(ori_b, pwd->b[i], pws->b[i] | i8)
2147 MSA_FN_IMM8(nori_b, pwd->b[i], ~(pws->b[i] | i8))
2148 MSA_FN_IMM8(xori_b, pwd->b[i], pws->b[i] ^ i8)
2149
2150 #define BIT_MOVE_IF_NOT_ZERO(dest, arg1, arg2, df) \
2151 UNSIGNED(((dest & (~arg2)) | (arg1 & arg2)), df)
2152 MSA_FN_IMM8(bmnzi_b, pwd->b[i],
2153 BIT_MOVE_IF_NOT_ZERO(pwd->b[i], pws->b[i], i8, DF_BYTE))
2154
2155 #define BIT_MOVE_IF_ZERO(dest, arg1, arg2, df) \
2156 UNSIGNED((dest & arg2) | (arg1 & (~arg2)), df)
2157 MSA_FN_IMM8(bmzi_b, pwd->b[i],
2158 BIT_MOVE_IF_ZERO(pwd->b[i], pws->b[i], i8, DF_BYTE))
2159
2160 #define BIT_SELECT(dest, arg1, arg2, df) \
2161 UNSIGNED((arg1 & (~dest)) | (arg2 & dest), df)
2162 MSA_FN_IMM8(bseli_b, pwd->b[i],
2163 BIT_SELECT(pwd->b[i], pws->b[i], i8, DF_BYTE))
2164
2165 #undef BIT_SELECT
2166 #undef BIT_MOVE_IF_ZERO
2167 #undef BIT_MOVE_IF_NOT_ZERO
2168 #undef MSA_FN_IMM8
2169
2170 #define SHF_POS(i, imm) (((i) & 0xfc) + (((imm) >> (2 * ((i) & 0x03))) & 0x03))
2171
2172 void helper_msa_shf_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2173 uint32_t ws, uint32_t imm)
2174 {
2175 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2176 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2177 wr_t wx, *pwx = &wx;
2178 uint32_t i;
2179
2180 switch (df) {
2181 case DF_BYTE:
2182 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
2183 pwx->b[i] = pws->b[SHF_POS(i, imm)];
2184 }
2185 break;
2186 case DF_HALF:
2187 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
2188 pwx->h[i] = pws->h[SHF_POS(i, imm)];
2189 }
2190 break;
2191 case DF_WORD:
2192 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2193 pwx->w[i] = pws->w[SHF_POS(i, imm)];
2194 }
2195 break;
2196 default:
2197 assert(0);
2198 }
2199 msa_move_v(pwd, pwx);
2200 }
2201
2202 static inline int64_t msa_addv_df(uint32_t df, int64_t arg1, int64_t arg2)
2203 {
2204 return arg1 + arg2;
2205 }
2206
2207 static inline int64_t msa_subv_df(uint32_t df, int64_t arg1, int64_t arg2)
2208 {
2209 return arg1 - arg2;
2210 }
2211
2212 static inline int64_t msa_max_s_df(uint32_t df, int64_t arg1, int64_t arg2)
2213 {
2214 return arg1 > arg2 ? arg1 : arg2;
2215 }
2216
2217 static inline int64_t msa_max_u_df(uint32_t df, int64_t arg1, int64_t arg2)
2218 {
2219 uint64_t u_arg1 = UNSIGNED(arg1, df);
2220 uint64_t u_arg2 = UNSIGNED(arg2, df);
2221 return u_arg1 > u_arg2 ? arg1 : arg2;
2222 }
2223
2224 static inline int64_t msa_min_s_df(uint32_t df, int64_t arg1, int64_t arg2)
2225 {
2226 return arg1 < arg2 ? arg1 : arg2;
2227 }
2228
2229 static inline int64_t msa_min_u_df(uint32_t df, int64_t arg1, int64_t arg2)
2230 {
2231 uint64_t u_arg1 = UNSIGNED(arg1, df);
2232 uint64_t u_arg2 = UNSIGNED(arg2, df);
2233 return u_arg1 < u_arg2 ? arg1 : arg2;
2234 }
2235
2236 #define MSA_BINOP_IMM_DF(helper, func) \
2237 void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, \
2238 uint32_t wd, uint32_t ws, int32_t u5) \
2239 { \
2240 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
2241 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
2242 uint32_t i; \
2243 \
2244 switch (df) { \
2245 case DF_BYTE: \
2246 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
2247 pwd->b[i] = msa_ ## func ## _df(df, pws->b[i], u5); \
2248 } \
2249 break; \
2250 case DF_HALF: \
2251 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
2252 pwd->h[i] = msa_ ## func ## _df(df, pws->h[i], u5); \
2253 } \
2254 break; \
2255 case DF_WORD: \
2256 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
2257 pwd->w[i] = msa_ ## func ## _df(df, pws->w[i], u5); \
2258 } \
2259 break; \
2260 case DF_DOUBLE: \
2261 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
2262 pwd->d[i] = msa_ ## func ## _df(df, pws->d[i], u5); \
2263 } \
2264 break; \
2265 default: \
2266 assert(0); \
2267 } \
2268 }
2269
2270 MSA_BINOP_IMM_DF(addvi, addv)
2271 MSA_BINOP_IMM_DF(subvi, subv)
2272 MSA_BINOP_IMM_DF(ceqi, ceq)
2273 MSA_BINOP_IMM_DF(clei_s, cle_s)
2274 MSA_BINOP_IMM_DF(clei_u, cle_u)
2275 MSA_BINOP_IMM_DF(clti_s, clt_s)
2276 MSA_BINOP_IMM_DF(clti_u, clt_u)
2277 MSA_BINOP_IMM_DF(maxi_s, max_s)
2278 MSA_BINOP_IMM_DF(maxi_u, max_u)
2279 MSA_BINOP_IMM_DF(mini_s, min_s)
2280 MSA_BINOP_IMM_DF(mini_u, min_u)
2281 #undef MSA_BINOP_IMM_DF
2282
2283 void helper_msa_ldi_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2284 int32_t s10)
2285 {
2286 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2287 uint32_t i;
2288
2289 switch (df) {
2290 case DF_BYTE:
2291 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
2292 pwd->b[i] = (int8_t)s10;
2293 }
2294 break;
2295 case DF_HALF:
2296 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
2297 pwd->h[i] = (int16_t)s10;
2298 }
2299 break;
2300 case DF_WORD:
2301 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2302 pwd->w[i] = (int32_t)s10;
2303 }
2304 break;
2305 case DF_DOUBLE:
2306 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2307 pwd->d[i] = (int64_t)s10;
2308 }
2309 break;
2310 default:
2311 assert(0);
2312 }
2313 }
2314
2315 static inline int64_t msa_sll_df(uint32_t df, int64_t arg1, int64_t arg2)
2316 {
2317 int32_t b_arg2 = BIT_POSITION(arg2, df);
2318 return arg1 << b_arg2;
2319 }
2320
2321 static inline int64_t msa_sra_df(uint32_t df, int64_t arg1, int64_t arg2)
2322 {
2323 int32_t b_arg2 = BIT_POSITION(arg2, df);
2324 return arg1 >> b_arg2;
2325 }
2326
2327 static inline int64_t msa_srl_df(uint32_t df, int64_t arg1, int64_t arg2)
2328 {
2329 uint64_t u_arg1 = UNSIGNED(arg1, df);
2330 int32_t b_arg2 = BIT_POSITION(arg2, df);
2331 return u_arg1 >> b_arg2;
2332 }
2333
2334 static inline int64_t msa_sat_s_df(uint32_t df, int64_t arg, uint32_t m)
2335 {
2336 return arg < M_MIN_INT(m + 1) ? M_MIN_INT(m + 1) :
2337 arg > M_MAX_INT(m + 1) ? M_MAX_INT(m + 1) :
2338 arg;
2339 }
2340
2341 static inline int64_t msa_sat_u_df(uint32_t df, int64_t arg, uint32_t m)
2342 {
2343 uint64_t u_arg = UNSIGNED(arg, df);
2344 return u_arg < M_MAX_UINT(m + 1) ? u_arg :
2345 M_MAX_UINT(m + 1);
2346 }
2347
2348 static inline int64_t msa_srar_df(uint32_t df, int64_t arg1, int64_t arg2)
2349 {
2350 int32_t b_arg2 = BIT_POSITION(arg2, df);
2351 if (b_arg2 == 0) {
2352 return arg1;
2353 } else {
2354 int64_t r_bit = (arg1 >> (b_arg2 - 1)) & 1;
2355 return (arg1 >> b_arg2) + r_bit;
2356 }
2357 }
2358
2359 static inline int64_t msa_srlr_df(uint32_t df, int64_t arg1, int64_t arg2)
2360 {
2361 uint64_t u_arg1 = UNSIGNED(arg1, df);
2362 int32_t b_arg2 = BIT_POSITION(arg2, df);
2363 if (b_arg2 == 0) {
2364 return u_arg1;
2365 } else {
2366 uint64_t r_bit = (u_arg1 >> (b_arg2 - 1)) & 1;
2367 return (u_arg1 >> b_arg2) + r_bit;
2368 }
2369 }
2370
2371 #define MSA_BINOP_IMMU_DF(helper, func) \
2372 void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, uint32_t wd, \
2373 uint32_t ws, uint32_t u5) \
2374 { \
2375 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
2376 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
2377 uint32_t i; \
2378 \
2379 switch (df) { \
2380 case DF_BYTE: \
2381 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
2382 pwd->b[i] = msa_ ## func ## _df(df, pws->b[i], u5); \
2383 } \
2384 break; \
2385 case DF_HALF: \
2386 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
2387 pwd->h[i] = msa_ ## func ## _df(df, pws->h[i], u5); \
2388 } \
2389 break; \
2390 case DF_WORD: \
2391 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
2392 pwd->w[i] = msa_ ## func ## _df(df, pws->w[i], u5); \
2393 } \
2394 break; \
2395 case DF_DOUBLE: \
2396 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
2397 pwd->d[i] = msa_ ## func ## _df(df, pws->d[i], u5); \
2398 } \
2399 break; \
2400 default: \
2401 assert(0); \
2402 } \
2403 }
2404
2405 MSA_BINOP_IMMU_DF(slli, sll)
2406 MSA_BINOP_IMMU_DF(srai, sra)
2407 MSA_BINOP_IMMU_DF(srli, srl)
2408 MSA_BINOP_IMMU_DF(bclri, bclr)
2409 MSA_BINOP_IMMU_DF(bseti, bset)
2410 MSA_BINOP_IMMU_DF(bnegi, bneg)
2411 MSA_BINOP_IMMU_DF(sat_s, sat_s)
2412 MSA_BINOP_IMMU_DF(sat_u, sat_u)
2413 MSA_BINOP_IMMU_DF(srari, srar)
2414 MSA_BINOP_IMMU_DF(srlri, srlr)
2415 #undef MSA_BINOP_IMMU_DF
2416
2417 #define MSA_TEROP_IMMU_DF(helper, func) \
2418 void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, \
2419 uint32_t wd, uint32_t ws, uint32_t u5) \
2420 { \
2421 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
2422 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
2423 uint32_t i; \
2424 \
2425 switch (df) { \
2426 case DF_BYTE: \
2427 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
2428 pwd->b[i] = msa_ ## func ## _df(df, pwd->b[i], pws->b[i], \
2429 u5); \
2430 } \
2431 break; \
2432 case DF_HALF: \
2433 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
2434 pwd->h[i] = msa_ ## func ## _df(df, pwd->h[i], pws->h[i], \
2435 u5); \
2436 } \
2437 break; \
2438 case DF_WORD: \
2439 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
2440 pwd->w[i] = msa_ ## func ## _df(df, pwd->w[i], pws->w[i], \
2441 u5); \
2442 } \
2443 break; \
2444 case DF_DOUBLE: \
2445 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
2446 pwd->d[i] = msa_ ## func ## _df(df, pwd->d[i], pws->d[i], \
2447 u5); \
2448 } \
2449 break; \
2450 default: \
2451 assert(0); \
2452 } \
2453 }
2454
2455 MSA_TEROP_IMMU_DF(binsli, binsl)
2456 MSA_TEROP_IMMU_DF(binsri, binsr)
2457 #undef MSA_TEROP_IMMU_DF
2458
2459 static inline int64_t msa_max_a_df(uint32_t df, int64_t arg1, int64_t arg2)
2460 {
2461 uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
2462 uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
2463 return abs_arg1 > abs_arg2 ? arg1 : arg2;
2464 }
2465
2466 static inline int64_t msa_min_a_df(uint32_t df, int64_t arg1, int64_t arg2)
2467 {
2468 uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
2469 uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
2470 return abs_arg1 < abs_arg2 ? arg1 : arg2;
2471 }
2472
2473 static inline int64_t msa_add_a_df(uint32_t df, int64_t arg1, int64_t arg2)
2474 {
2475 uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
2476 uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
2477 return abs_arg1 + abs_arg2;
2478 }
2479
2480 static inline int64_t msa_adds_a_df(uint32_t df, int64_t arg1, int64_t arg2)
2481 {
2482 uint64_t max_int = (uint64_t)DF_MAX_INT(df);
2483 uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
2484 uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
2485 if (abs_arg1 > max_int || abs_arg2 > max_int) {
2486 return (int64_t)max_int;
2487 } else {
2488 return (abs_arg1 < max_int - abs_arg2) ? abs_arg1 + abs_arg2 : max_int;
2489 }
2490 }
2491
2492 static inline int64_t msa_adds_s_df(uint32_t df, int64_t arg1, int64_t arg2)
2493 {
2494 int64_t max_int = DF_MAX_INT(df);
2495 int64_t min_int = DF_MIN_INT(df);
2496 if (arg1 < 0) {
2497 return (min_int - arg1 < arg2) ? arg1 + arg2 : min_int;
2498 } else {
2499 return (arg2 < max_int - arg1) ? arg1 + arg2 : max_int;
2500 }
2501 }
2502
2503 static inline uint64_t msa_adds_u_df(uint32_t df, uint64_t arg1, uint64_t arg2)
2504 {
2505 uint64_t max_uint = DF_MAX_UINT(df);
2506 uint64_t u_arg1 = UNSIGNED(arg1, df);
2507 uint64_t u_arg2 = UNSIGNED(arg2, df);
2508 return (u_arg1 < max_uint - u_arg2) ? u_arg1 + u_arg2 : max_uint;
2509 }
2510
2511 static inline int64_t msa_subs_s_df(uint32_t df, int64_t arg1, int64_t arg2)
2512 {
2513 int64_t max_int = DF_MAX_INT(df);
2514 int64_t min_int = DF_MIN_INT(df);
2515 if (arg2 > 0) {
2516 return (min_int + arg2 < arg1) ? arg1 - arg2 : min_int;
2517 } else {
2518 return (arg1 < max_int + arg2) ? arg1 - arg2 : max_int;
2519 }
2520 }
2521
2522 static inline int64_t msa_subs_u_df(uint32_t df, int64_t arg1, int64_t arg2)
2523 {
2524 uint64_t u_arg1 = UNSIGNED(arg1, df);
2525 uint64_t u_arg2 = UNSIGNED(arg2, df);
2526 return (u_arg1 > u_arg2) ? u_arg1 - u_arg2 : 0;
2527 }
2528
2529 static inline int64_t msa_subsus_u_df(uint32_t df, int64_t arg1, int64_t arg2)
2530 {
2531 uint64_t u_arg1 = UNSIGNED(arg1, df);
2532 uint64_t max_uint = DF_MAX_UINT(df);
2533 if (arg2 >= 0) {
2534 uint64_t u_arg2 = (uint64_t)arg2;
2535 return (u_arg1 > u_arg2) ?
2536 (int64_t)(u_arg1 - u_arg2) :
2537 0;
2538 } else {
2539 uint64_t u_arg2 = (uint64_t)(-arg2);
2540 return (u_arg1 < max_uint - u_arg2) ?
2541 (int64_t)(u_arg1 + u_arg2) :
2542 (int64_t)max_uint;
2543 }
2544 }
2545
2546 static inline int64_t msa_subsuu_s_df(uint32_t df, int64_t arg1, int64_t arg2)
2547 {
2548 uint64_t u_arg1 = UNSIGNED(arg1, df);
2549 uint64_t u_arg2 = UNSIGNED(arg2, df);
2550 int64_t max_int = DF_MAX_INT(df);
2551 int64_t min_int = DF_MIN_INT(df);
2552 if (u_arg1 > u_arg2) {
2553 return u_arg1 - u_arg2 < (uint64_t)max_int ?
2554 (int64_t)(u_arg1 - u_arg2) :
2555 max_int;
2556 } else {
2557 return u_arg2 - u_arg1 < (uint64_t)(-min_int) ?
2558 (int64_t)(u_arg1 - u_arg2) :
2559 min_int;
2560 }
2561 }
2562
2563 static inline int64_t msa_asub_s_df(uint32_t df, int64_t arg1, int64_t arg2)
2564 {
2565 /* signed compare */
2566 return (arg1 < arg2) ?
2567 (uint64_t)(arg2 - arg1) : (uint64_t)(arg1 - arg2);
2568 }
2569
2570 static inline uint64_t msa_asub_u_df(uint32_t df, uint64_t arg1, uint64_t arg2)
2571 {
2572 uint64_t u_arg1 = UNSIGNED(arg1, df);
2573 uint64_t u_arg2 = UNSIGNED(arg2, df);
2574 /* unsigned compare */
2575 return (u_arg1 < u_arg2) ?
2576 (uint64_t)(u_arg2 - u_arg1) : (uint64_t)(u_arg1 - u_arg2);
2577 }
2578
2579 static inline int64_t msa_mulv_df(uint32_t df, int64_t arg1, int64_t arg2)
2580 {
2581 return arg1 * arg2;
2582 }
2583
2584 #define SIGNED_EVEN(a, df) \
2585 ((((int64_t)(a)) << (64 - DF_BITS(df) / 2)) >> (64 - DF_BITS(df) / 2))
2586
2587 #define UNSIGNED_EVEN(a, df) \
2588 ((((uint64_t)(a)) << (64 - DF_BITS(df) / 2)) >> (64 - DF_BITS(df) / 2))
2589
2590 #define SIGNED_ODD(a, df) \
2591 ((((int64_t)(a)) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df) / 2))
2592
2593 #define UNSIGNED_ODD(a, df) \
2594 ((((uint64_t)(a)) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df) / 2))
2595
2596 #define SIGNED_EXTRACT(e, o, a, df) \
2597 do { \
2598 e = SIGNED_EVEN(a, df); \
2599 o = SIGNED_ODD(a, df); \
2600 } while (0)
2601
2602 #define UNSIGNED_EXTRACT(e, o, a, df) \
2603 do { \
2604 e = UNSIGNED_EVEN(a, df); \
2605 o = UNSIGNED_ODD(a, df); \
2606 } while (0)
2607
2608 static inline int64_t msa_dotp_s_df(uint32_t df, int64_t arg1, int64_t arg2)
2609 {
2610 int64_t even_arg1;
2611 int64_t even_arg2;
2612 int64_t odd_arg1;
2613 int64_t odd_arg2;
2614 SIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
2615 SIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
2616 return (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
2617 }
2618
2619 static inline int64_t msa_dotp_u_df(uint32_t df, int64_t arg1, int64_t arg2)
2620 {
2621 int64_t even_arg1;
2622 int64_t even_arg2;
2623 int64_t odd_arg1;
2624 int64_t odd_arg2;
2625 UNSIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
2626 UNSIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
2627 return (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
2628 }
2629
2630 #define CONCATENATE_AND_SLIDE(s, k) \
2631 do { \
2632 for (i = 0; i < s; i++) { \
2633 v[i] = pws->b[s * k + i]; \
2634 v[i + s] = pwd->b[s * k + i]; \
2635 } \
2636 for (i = 0; i < s; i++) { \
2637 pwd->b[s * k + i] = v[i + n]; \
2638 } \
2639 } while (0)
2640
2641 static inline void msa_sld_df(uint32_t df, wr_t *pwd,
2642 wr_t *pws, target_ulong rt)
2643 {
2644 uint32_t n = rt % DF_ELEMENTS(df);
2645 uint8_t v[64];
2646 uint32_t i, k;
2647
2648 switch (df) {
2649 case DF_BYTE:
2650 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_BYTE), 0);
2651 break;
2652 case DF_HALF:
2653 for (k = 0; k < 2; k++) {
2654 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_HALF), k);
2655 }
2656 break;
2657 case DF_WORD:
2658 for (k = 0; k < 4; k++) {
2659 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_WORD), k);
2660 }
2661 break;
2662 case DF_DOUBLE:
2663 for (k = 0; k < 8; k++) {
2664 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_DOUBLE), k);
2665 }
2666 break;
2667 default:
2668 assert(0);
2669 }
2670 }
2671
2672 static inline int64_t msa_hadd_s_df(uint32_t df, int64_t arg1, int64_t arg2)
2673 {
2674 return SIGNED_ODD(arg1, df) + SIGNED_EVEN(arg2, df);
2675 }
2676
2677 static inline int64_t msa_hadd_u_df(uint32_t df, int64_t arg1, int64_t arg2)
2678 {
2679 return UNSIGNED_ODD(arg1, df) + UNSIGNED_EVEN(arg2, df);
2680 }
2681
2682 static inline int64_t msa_hsub_s_df(uint32_t df, int64_t arg1, int64_t arg2)
2683 {
2684 return SIGNED_ODD(arg1, df) - SIGNED_EVEN(arg2, df);
2685 }
2686
2687 static inline int64_t msa_hsub_u_df(uint32_t df, int64_t arg1, int64_t arg2)
2688 {
2689 return UNSIGNED_ODD(arg1, df) - UNSIGNED_EVEN(arg2, df);
2690 }
2691
2692 static inline int64_t msa_mul_q_df(uint32_t df, int64_t arg1, int64_t arg2)
2693 {
2694 int64_t q_min = DF_MIN_INT(df);
2695 int64_t q_max = DF_MAX_INT(df);
2696
2697 if (arg1 == q_min && arg2 == q_min) {
2698 return q_max;
2699 }
2700 return (arg1 * arg2) >> (DF_BITS(df) - 1);
2701 }
2702
2703 static inline int64_t msa_mulr_q_df(uint32_t df, int64_t arg1, int64_t arg2)
2704 {
2705 int64_t q_min = DF_MIN_INT(df);
2706 int64_t q_max = DF_MAX_INT(df);
2707 int64_t r_bit = 1 << (DF_BITS(df) - 2);
2708
2709 if (arg1 == q_min && arg2 == q_min) {
2710 return q_max;
2711 }
2712 return (arg1 * arg2 + r_bit) >> (DF_BITS(df) - 1);
2713 }
2714
2715 #define MSA_BINOP_DF(func) \
2716 void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, \
2717 uint32_t wd, uint32_t ws, uint32_t wt) \
2718 { \
2719 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
2720 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
2721 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
2722 \
2723 switch (df) { \
2724 case DF_BYTE: \
2725 pwd->b[0] = msa_ ## func ## _df(df, pws->b[0], pwt->b[0]); \
2726 pwd->b[1] = msa_ ## func ## _df(df, pws->b[1], pwt->b[1]); \
2727 pwd->b[2] = msa_ ## func ## _df(df, pws->b[2], pwt->b[2]); \
2728 pwd->b[3] = msa_ ## func ## _df(df, pws->b[3], pwt->b[3]); \
2729 pwd->b[4] = msa_ ## func ## _df(df, pws->b[4], pwt->b[4]); \
2730 pwd->b[5] = msa_ ## func ## _df(df, pws->b[5], pwt->b[5]); \
2731 pwd->b[6] = msa_ ## func ## _df(df, pws->b[6], pwt->b[6]); \
2732 pwd->b[7] = msa_ ## func ## _df(df, pws->b[7], pwt->b[7]); \
2733 pwd->b[8] = msa_ ## func ## _df(df, pws->b[8], pwt->b[8]); \
2734 pwd->b[9] = msa_ ## func ## _df(df, pws->b[9], pwt->b[9]); \
2735 pwd->b[10] = msa_ ## func ## _df(df, pws->b[10], pwt->b[10]); \
2736 pwd->b[11] = msa_ ## func ## _df(df, pws->b[11], pwt->b[11]); \
2737 pwd->b[12] = msa_ ## func ## _df(df, pws->b[12], pwt->b[12]); \
2738 pwd->b[13] = msa_ ## func ## _df(df, pws->b[13], pwt->b[13]); \
2739 pwd->b[14] = msa_ ## func ## _df(df, pws->b[14], pwt->b[14]); \
2740 pwd->b[15] = msa_ ## func ## _df(df, pws->b[15], pwt->b[15]); \
2741 break; \
2742 case DF_HALF: \
2743 pwd->h[0] = msa_ ## func ## _df(df, pws->h[0], pwt->h[0]); \
2744 pwd->h[1] = msa_ ## func ## _df(df, pws->h[1], pwt->h[1]); \
2745 pwd->h[2] = msa_ ## func ## _df(df, pws->h[2], pwt->h[2]); \
2746 pwd->h[3] = msa_ ## func ## _df(df, pws->h[3], pwt->h[3]); \
2747 pwd->h[4] = msa_ ## func ## _df(df, pws->h[4], pwt->h[4]); \
2748 pwd->h[5] = msa_ ## func ## _df(df, pws->h[5], pwt->h[5]); \
2749 pwd->h[6] = msa_ ## func ## _df(df, pws->h[6], pwt->h[6]); \
2750 pwd->h[7] = msa_ ## func ## _df(df, pws->h[7], pwt->h[7]); \
2751 break; \
2752 case DF_WORD: \
2753 pwd->w[0] = msa_ ## func ## _df(df, pws->w[0], pwt->w[0]); \
2754 pwd->w[1] = msa_ ## func ## _df(df, pws->w[1], pwt->w[1]); \
2755 pwd->w[2] = msa_ ## func ## _df(df, pws->w[2], pwt->w[2]); \
2756 pwd->w[3] = msa_ ## func ## _df(df, pws->w[3], pwt->w[3]); \
2757 break; \
2758 case DF_DOUBLE: \
2759 pwd->d[0] = msa_ ## func ## _df(df, pws->d[0], pwt->d[0]); \
2760 pwd->d[1] = msa_ ## func ## _df(df, pws->d[1], pwt->d[1]); \
2761 break; \
2762 default: \
2763 assert(0); \
2764 } \
2765 }
2766
2767 MSA_BINOP_DF(sll)
2768 MSA_BINOP_DF(sra)
2769 MSA_BINOP_DF(srl)
2770 MSA_BINOP_DF(addv)
2771 MSA_BINOP_DF(subv)
2772 MSA_BINOP_DF(max_s)
2773 MSA_BINOP_DF(max_u)
2774 MSA_BINOP_DF(min_s)
2775 MSA_BINOP_DF(min_u)
2776 MSA_BINOP_DF(max_a)
2777 MSA_BINOP_DF(min_a)
2778 MSA_BINOP_DF(add_a)
2779 MSA_BINOP_DF(adds_a)
2780 MSA_BINOP_DF(adds_s)
2781 MSA_BINOP_DF(adds_u)
2782 MSA_BINOP_DF(subs_s)
2783 MSA_BINOP_DF(subs_u)
2784 MSA_BINOP_DF(subsus_u)
2785 MSA_BINOP_DF(subsuu_s)
2786 MSA_BINOP_DF(asub_s)
2787 MSA_BINOP_DF(asub_u)
2788 MSA_BINOP_DF(mulv)
2789 MSA_BINOP_DF(dotp_s)
2790 MSA_BINOP_DF(dotp_u)
2791 MSA_BINOP_DF(srar)
2792 MSA_BINOP_DF(srlr)
2793 MSA_BINOP_DF(hadd_s)
2794 MSA_BINOP_DF(hadd_u)
2795 MSA_BINOP_DF(hsub_s)
2796 MSA_BINOP_DF(hsub_u)
2797
2798 MSA_BINOP_DF(mul_q)
2799 MSA_BINOP_DF(mulr_q)
2800 #undef MSA_BINOP_DF
2801
2802 void helper_msa_sld_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2803 uint32_t ws, uint32_t rt)
2804 {
2805 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2806 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2807
2808 msa_sld_df(df, pwd, pws, env->active_tc.gpr[rt]);
2809 }
2810
2811 static inline int64_t msa_maddv_df(uint32_t df, int64_t dest, int64_t arg1,
2812 int64_t arg2)
2813 {
2814 return dest + arg1 * arg2;
2815 }
2816
2817 static inline int64_t msa_msubv_df(uint32_t df, int64_t dest, int64_t arg1,
2818 int64_t arg2)
2819 {
2820 return dest - arg1 * arg2;
2821 }
2822
2823 static inline int64_t msa_dpadd_s_df(uint32_t df, int64_t dest, int64_t arg1,
2824 int64_t arg2)
2825 {
2826 int64_t even_arg1;
2827 int64_t even_arg2;
2828 int64_t odd_arg1;
2829 int64_t odd_arg2;
2830 SIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
2831 SIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
2832 return dest + (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
2833 }
2834
2835 static inline int64_t msa_dpadd_u_df(uint32_t df, int64_t dest, int64_t arg1,
2836 int64_t arg2)
2837 {
2838 int64_t even_arg1;
2839 int64_t even_arg2;
2840 int64_t odd_arg1;
2841 int64_t odd_arg2;
2842 UNSIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
2843 UNSIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
2844 return dest + (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
2845 }
2846
2847 static inline int64_t msa_dpsub_s_df(uint32_t df, int64_t dest, int64_t arg1,
2848 int64_t arg2)
2849 {
2850 int64_t even_arg1;
2851 int64_t even_arg2;
2852 int64_t odd_arg1;
2853 int64_t odd_arg2;
2854 SIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
2855 SIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
2856 return dest - ((even_arg1 * even_arg2) + (odd_arg1 * odd_arg2));
2857 }
2858
2859 static inline int64_t msa_dpsub_u_df(uint32_t df, int64_t dest, int64_t arg1,
2860 int64_t arg2)
2861 {
2862 int64_t even_arg1;
2863 int64_t even_arg2;
2864 int64_t odd_arg1;
2865 int64_t odd_arg2;
2866 UNSIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
2867 UNSIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
2868 return dest - ((even_arg1 * even_arg2) + (odd_arg1 * odd_arg2));
2869 }
2870
2871 static inline int64_t msa_madd_q_df(uint32_t df, int64_t dest, int64_t arg1,
2872 int64_t arg2)
2873 {
2874 int64_t q_prod, q_ret;
2875
2876 int64_t q_max = DF_MAX_INT(df);
2877 int64_t q_min = DF_MIN_INT(df);
2878
2879 q_prod = arg1 * arg2;
2880 q_ret = ((dest << (DF_BITS(df) - 1)) + q_prod) >> (DF_BITS(df) - 1);
2881
2882 return (q_ret < q_min) ? q_min : (q_max < q_ret) ? q_max : q_ret;
2883 }
2884
2885 static inline int64_t msa_msub_q_df(uint32_t df, int64_t dest, int64_t arg1,
2886 int64_t arg2)
2887 {
2888 int64_t q_prod, q_ret;
2889
2890 int64_t q_max = DF_MAX_INT(df);
2891 int64_t q_min = DF_MIN_INT(df);
2892
2893 q_prod = arg1 * arg2;
2894 q_ret = ((dest << (DF_BITS(df) - 1)) - q_prod) >> (DF_BITS(df) - 1);
2895
2896 return (q_ret < q_min) ? q_min : (q_max < q_ret) ? q_max : q_ret;
2897 }
2898
2899 static inline int64_t msa_maddr_q_df(uint32_t df, int64_t dest, int64_t arg1,
2900 int64_t arg2)
2901 {
2902 int64_t q_prod, q_ret;
2903
2904 int64_t q_max = DF_MAX_INT(df);
2905 int64_t q_min = DF_MIN_INT(df);
2906 int64_t r_bit = 1 << (DF_BITS(df) - 2);
2907
2908 q_prod = arg1 * arg2;
2909 q_ret = ((dest << (DF_BITS(df) - 1)) + q_prod + r_bit) >> (DF_BITS(df) - 1);
2910
2911 return (q_ret < q_min) ? q_min : (q_max < q_ret) ? q_max : q_ret;
2912 }
2913
2914 static inline int64_t msa_msubr_q_df(uint32_t df, int64_t dest, int64_t arg1,
2915 int64_t arg2)
2916 {
2917 int64_t q_prod, q_ret;
2918
2919 int64_t q_max = DF_MAX_INT(df);
2920 int64_t q_min = DF_MIN_INT(df);
2921 int64_t r_bit = 1 << (DF_BITS(df) - 2);
2922
2923 q_prod = arg1 * arg2;
2924 q_ret = ((dest << (DF_BITS(df) - 1)) - q_prod + r_bit) >> (DF_BITS(df) - 1);
2925
2926 return (q_ret < q_min) ? q_min : (q_max < q_ret) ? q_max : q_ret;
2927 }
2928
2929 #define MSA_TEROP_DF(func) \
2930 void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, uint32_t wd, \
2931 uint32_t ws, uint32_t wt) \
2932 { \
2933 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
2934 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
2935 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
2936 \
2937 switch (df) { \
2938 case DF_BYTE: \
2939 pwd->b[0] = msa_ ## func ## _df(df, pwd->b[0], pws->b[0], \
2940 pwt->b[0]); \
2941 pwd->b[1] = msa_ ## func ## _df(df, pwd->b[1], pws->b[1], \
2942 pwt->b[1]); \
2943 pwd->b[2] = msa_ ## func ## _df(df, pwd->b[2], pws->b[2], \
2944 pwt->b[2]); \
2945 pwd->b[3] = msa_ ## func ## _df(df, pwd->b[3], pws->b[3], \
2946 pwt->b[3]); \
2947 pwd->b[4] = msa_ ## func ## _df(df, pwd->b[4], pws->b[4], \
2948 pwt->b[4]); \
2949 pwd->b[5] = msa_ ## func ## _df(df, pwd->b[5], pws->b[5], \
2950 pwt->b[5]); \
2951 pwd->b[6] = msa_ ## func ## _df(df, pwd->b[6], pws->b[6], \
2952 pwt->b[6]); \
2953 pwd->b[7] = msa_ ## func ## _df(df, pwd->b[7], pws->b[7], \
2954 pwt->b[7]); \
2955 pwd->b[8] = msa_ ## func ## _df(df, pwd->b[8], pws->b[8], \
2956 pwt->b[8]); \
2957 pwd->b[9] = msa_ ## func ## _df(df, pwd->b[9], pws->b[9], \
2958 pwt->b[9]); \
2959 pwd->b[10] = msa_ ## func ## _df(df, pwd->b[10], pws->b[10], \
2960 pwt->b[10]); \
2961 pwd->b[11] = msa_ ## func ## _df(df, pwd->b[11], pws->b[11], \
2962 pwt->b[11]); \
2963 pwd->b[12] = msa_ ## func ## _df(df, pwd->b[12], pws->b[12], \
2964 pwt->b[12]); \
2965 pwd->b[13] = msa_ ## func ## _df(df, pwd->b[13], pws->b[13], \
2966 pwt->b[13]); \
2967 pwd->b[14] = msa_ ## func ## _df(df, pwd->b[14], pws->b[14], \
2968 pwt->b[14]); \
2969 pwd->b[15] = msa_ ## func ## _df(df, pwd->b[15], pws->b[15], \
2970 pwt->b[15]); \
2971 break; \
2972 case DF_HALF: \
2973 pwd->h[0] = msa_ ## func ## _df(df, pwd->h[0], pws->h[0], pwt->h[0]); \
2974 pwd->h[1] = msa_ ## func ## _df(df, pwd->h[1], pws->h[1], pwt->h[1]); \
2975 pwd->h[2] = msa_ ## func ## _df(df, pwd->h[2], pws->h[2], pwt->h[2]); \
2976 pwd->h[3] = msa_ ## func ## _df(df, pwd->h[3], pws->h[3], pwt->h[3]); \
2977 pwd->h[4] = msa_ ## func ## _df(df, pwd->h[4], pws->h[4], pwt->h[4]); \
2978 pwd->h[5] = msa_ ## func ## _df(df, pwd->h[5], pws->h[5], pwt->h[5]); \
2979 pwd->h[6] = msa_ ## func ## _df(df, pwd->h[6], pws->h[6], pwt->h[6]); \
2980 pwd->h[7] = msa_ ## func ## _df(df, pwd->h[7], pws->h[7], pwt->h[7]); \
2981 break; \
2982 case DF_WORD: \
2983 pwd->w[0] = msa_ ## func ## _df(df, pwd->w[0], pws->w[0], pwt->w[0]); \
2984 pwd->w[1] = msa_ ## func ## _df(df, pwd->w[1], pws->w[1], pwt->w[1]); \
2985 pwd->w[2] = msa_ ## func ## _df(df, pwd->w[2], pws->w[2], pwt->w[2]); \
2986 pwd->w[3] = msa_ ## func ## _df(df, pwd->w[3], pws->w[3], pwt->w[3]); \
2987 break; \
2988 case DF_DOUBLE: \
2989 pwd->d[0] = msa_ ## func ## _df(df, pwd->d[0], pws->d[0], pwt->d[0]); \
2990 pwd->d[1] = msa_ ## func ## _df(df, pwd->d[1], pws->d[1], pwt->d[1]); \
2991 break; \
2992 default: \
2993 assert(0); \
2994 } \
2995 }
2996
2997 MSA_TEROP_DF(maddv)
2998 MSA_TEROP_DF(msubv)
2999 MSA_TEROP_DF(dpadd_s)
3000 MSA_TEROP_DF(dpadd_u)
3001 MSA_TEROP_DF(dpsub_s)
3002 MSA_TEROP_DF(dpsub_u)
3003 MSA_TEROP_DF(binsl)
3004 MSA_TEROP_DF(binsr)
3005 MSA_TEROP_DF(madd_q)
3006 MSA_TEROP_DF(msub_q)
3007 MSA_TEROP_DF(maddr_q)
3008 MSA_TEROP_DF(msubr_q)
3009 #undef MSA_TEROP_DF
3010
3011 static inline void msa_splat_df(uint32_t df, wr_t *pwd,
3012 wr_t *pws, target_ulong rt)
3013 {
3014 uint32_t n = rt % DF_ELEMENTS(df);
3015 uint32_t i;
3016
3017 switch (df) {
3018 case DF_BYTE:
3019 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
3020 pwd->b[i] = pws->b[n];
3021 }
3022 break;
3023 case DF_HALF:
3024 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
3025 pwd->h[i] = pws->h[n];
3026 }
3027 break;
3028 case DF_WORD:
3029 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3030 pwd->w[i] = pws->w[n];
3031 }
3032 break;
3033 case DF_DOUBLE:
3034 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3035 pwd->d[i] = pws->d[n];
3036 }
3037 break;
3038 default:
3039 assert(0);
3040 }
3041 }
3042
3043 void helper_msa_splat_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3044 uint32_t ws, uint32_t rt)
3045 {
3046 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3047 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3048
3049 msa_splat_df(df, pwd, pws, env->active_tc.gpr[rt]);
3050 }
3051
3052 #define MSA_DO_B MSA_DO(b)
3053 #define MSA_DO_H MSA_DO(h)
3054 #define MSA_DO_W MSA_DO(w)
3055 #define MSA_DO_D MSA_DO(d)
3056
3057 #define MSA_LOOP_B MSA_LOOP(B)
3058 #define MSA_LOOP_H MSA_LOOP(H)
3059 #define MSA_LOOP_W MSA_LOOP(W)
3060 #define MSA_LOOP_D MSA_LOOP(D)
3061
3062 #define MSA_LOOP_COND_B MSA_LOOP_COND(DF_BYTE)
3063 #define MSA_LOOP_COND_H MSA_LOOP_COND(DF_HALF)
3064 #define MSA_LOOP_COND_W MSA_LOOP_COND(DF_WORD)
3065 #define MSA_LOOP_COND_D MSA_LOOP_COND(DF_DOUBLE)
3066
3067 #define MSA_LOOP(DF) \
3068 do { \
3069 for (i = 0; i < (MSA_LOOP_COND_ ## DF) ; i++) { \
3070 MSA_DO_ ## DF; \
3071 } \
3072 } while (0)
3073
3074 #define MSA_FN_DF(FUNC) \
3075 void helper_msa_##FUNC(CPUMIPSState *env, uint32_t df, uint32_t wd, \
3076 uint32_t ws, uint32_t wt) \
3077 { \
3078 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
3079 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
3080 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
3081 wr_t wx, *pwx = &wx; \
3082 uint32_t i; \
3083 switch (df) { \
3084 case DF_BYTE: \
3085 MSA_LOOP_B; \
3086 break; \
3087 case DF_HALF: \
3088 MSA_LOOP_H; \
3089 break; \
3090 case DF_WORD: \
3091 MSA_LOOP_W; \
3092 break; \
3093 case DF_DOUBLE: \
3094 MSA_LOOP_D; \
3095 break; \
3096 default: \
3097 assert(0); \
3098 } \
3099 msa_move_v(pwd, pwx); \
3100 }
3101
3102 #define MSA_LOOP_COND(DF) \
3103 (DF_ELEMENTS(DF) / 2)
3104
3105 #define Rb(pwr, i) (pwr->b[i])
3106 #define Lb(pwr, i) (pwr->b[i + DF_ELEMENTS(DF_BYTE) / 2])
3107 #define Rh(pwr, i) (pwr->h[i])
3108 #define Lh(pwr, i) (pwr->h[i + DF_ELEMENTS(DF_HALF) / 2])
3109 #define Rw(pwr, i) (pwr->w[i])
3110 #define Lw(pwr, i) (pwr->w[i + DF_ELEMENTS(DF_WORD) / 2])
3111 #define Rd(pwr, i) (pwr->d[i])
3112 #define Ld(pwr, i) (pwr->d[i + DF_ELEMENTS(DF_DOUBLE) / 2])
3113
3114 #undef MSA_LOOP_COND
3115
3116 #define MSA_LOOP_COND(DF) \
3117 (DF_ELEMENTS(DF))
3118
3119 #define MSA_DO(DF) \
3120 do { \
3121 uint32_t n = DF_ELEMENTS(df); \
3122 uint32_t k = (pwd->DF[i] & 0x3f) % (2 * n); \
3123 pwx->DF[i] = \
3124 (pwd->DF[i] & 0xc0) ? 0 : k < n ? pwt->DF[k] : pws->DF[k - n]; \
3125 } while (0)
3126 MSA_FN_DF(vshf_df)
3127 #undef MSA_DO
3128 #undef MSA_LOOP_COND
3129 #undef MSA_FN_DF
3130
3131
3132 void helper_msa_ilvev_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3133 uint32_t ws, uint32_t wt)
3134 {
3135 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3136 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3137 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3138
3139 switch (df) {
3140 case DF_BYTE:
3141 #if defined(HOST_WORDS_BIGENDIAN)
3142 pwd->b[8] = pws->b[9];
3143 pwd->b[9] = pwt->b[9];
3144 pwd->b[10] = pws->b[11];
3145 pwd->b[11] = pwt->b[11];
3146 pwd->b[12] = pws->b[13];
3147 pwd->b[13] = pwt->b[13];
3148 pwd->b[14] = pws->b[15];
3149 pwd->b[15] = pwt->b[15];
3150 pwd->b[0] = pws->b[1];
3151 pwd->b[1] = pwt->b[1];
3152 pwd->b[2] = pws->b[3];
3153 pwd->b[3] = pwt->b[3];
3154 pwd->b[4] = pws->b[5];
3155 pwd->b[5] = pwt->b[5];
3156 pwd->b[6] = pws->b[7];
3157 pwd->b[7] = pwt->b[7];
3158 #else
3159 pwd->b[15] = pws->b[14];
3160 pwd->b[14] = pwt->b[14];
3161 pwd->b[13] = pws->b[12];
3162 pwd->b[12] = pwt->b[12];
3163 pwd->b[11] = pws->b[10];
3164 pwd->b[10] = pwt->b[10];
3165 pwd->b[9] = pws->b[8];
3166 pwd->b[8] = pwt->b[8];
3167 pwd->b[7] = pws->b[6];
3168 pwd->b[6] = pwt->b[6];
3169 pwd->b[5] = pws->b[4];
3170 pwd->b[4] = pwt->b[4];
3171 pwd->b[3] = pws->b[2];
3172 pwd->b[2] = pwt->b[2];
3173 pwd->b[1] = pws->b[0];
3174 pwd->b[0] = pwt->b[0];
3175 #endif
3176 break;
3177 case DF_HALF:
3178 #if defined(HOST_WORDS_BIGENDIAN)
3179 pwd->h[4] = pws->h[5];
3180 pwd->h[5] = pwt->h[5];
3181 pwd->h[6] = pws->h[7];
3182 pwd->h[7] = pwt->h[7];
3183 pwd->h[0] = pws->h[1];
3184 pwd->h[1] = pwt->h[1];
3185 pwd->h[2] = pws->h[3];
3186 pwd->h[3] = pwt->h[3];
3187 #else
3188 pwd->h[7] = pws->h[6];
3189 pwd->h[6] = pwt->h[6];
3190 pwd->h[5] = pws->h[4];
3191 pwd->h[4] = pwt->h[4];
3192 pwd->h[3] = pws->h[2];
3193 pwd->h[2] = pwt->h[2];
3194 pwd->h[1] = pws->h[0];
3195 pwd->h[0] = pwt->h[0];
3196 #endif
3197 break;
3198 case DF_WORD:
3199 #if defined(HOST_WORDS_BIGENDIAN)
3200 pwd->w[2] = pws->w[3];
3201 pwd->w[3] = pwt->w[3];
3202 pwd->w[0] = pws->w[1];
3203 pwd->w[1] = pwt->w[1];
3204 #else
3205 pwd->w[3] = pws->w[2];
3206 pwd->w[2] = pwt->w[2];
3207 pwd->w[1] = pws->w[0];
3208 pwd->w[0] = pwt->w[0];
3209 #endif
3210 break;
3211 case DF_DOUBLE:
3212 pwd->d[1] = pws->d[0];
3213 pwd->d[0] = pwt->d[0];
3214 break;
3215 default:
3216 assert(0);
3217 }
3218 }
3219
3220 void helper_msa_ilvod_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3221 uint32_t ws, uint32_t wt)
3222 {
3223 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3224 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3225 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3226
3227 switch (df) {
3228 case DF_BYTE:
3229 #if defined(HOST_WORDS_BIGENDIAN)
3230 pwd->b[7] = pwt->b[6];
3231 pwd->b[6] = pws->b[6];
3232 pwd->b[5] = pwt->b[4];
3233 pwd->b[4] = pws->b[4];
3234 pwd->b[3] = pwt->b[2];
3235 pwd->b[2] = pws->b[2];
3236 pwd->b[1] = pwt->b[0];
3237 pwd->b[0] = pws->b[0];
3238 pwd->b[15] = pwt->b[14];
3239 pwd->b[14] = pws->b[14];
3240 pwd->b[13] = pwt->b[12];
3241 pwd->b[12] = pws->b[12];
3242 pwd->b[11] = pwt->b[10];
3243 pwd->b[10] = pws->b[10];
3244 pwd->b[9] = pwt->b[8];
3245 pwd->b[8] = pws->b[8];
3246 #else
3247 pwd->b[0] = pwt->b[1];
3248 pwd->b[1] = pws->b[1];
3249 pwd->b[2] = pwt->b[3];
3250 pwd->b[3] = pws->b[3];
3251 pwd->b[4] = pwt->b[5];
3252 pwd->b[5] = pws->b[5];
3253 pwd->b[6] = pwt->b[7];
3254 pwd->b[7] = pws->b[7];
3255 pwd->b[8] = pwt->b[9];
3256 pwd->b[9] = pws->b[9];
3257 pwd->b[10] = pwt->b[11];
3258 pwd->b[11] = pws->b[11];
3259 pwd->b[12] = pwt->b[13];
3260 pwd->b[13] = pws->b[13];
3261 pwd->b[14] = pwt->b[15];
3262 pwd->b[15] = pws->b[15];
3263 #endif
3264 break;
3265 case DF_HALF:
3266 #if defined(HOST_WORDS_BIGENDIAN)
3267 pwd->h[3] = pwt->h[2];
3268 pwd->h[2] = pws->h[2];
3269 pwd->h[1] = pwt->h[0];
3270 pwd->h[0] = pws->h[0];
3271 pwd->h[7] = pwt->h[6];
3272 pwd->h[6] = pws->h[6];
3273 pwd->h[5] = pwt->h[4];
3274 pwd->h[4] = pws->h[4];
3275 #else
3276 pwd->h[0] = pwt->h[1];
3277 pwd->h[1] = pws->h[1];
3278 pwd->h[2] = pwt->h[3];
3279 pwd->h[3] = pws->h[3];
3280 pwd->h[4] = pwt->h[5];
3281 pwd->h[5] = pws->h[5];
3282 pwd->h[6] = pwt->h[7];
3283 pwd->h[7] = pws->h[7];
3284 #endif
3285 break;
3286 case DF_WORD:
3287 #if defined(HOST_WORDS_BIGENDIAN)
3288 pwd->w[1] = pwt->w[0];
3289 pwd->w[0] = pws->w[0];
3290 pwd->w[3] = pwt->w[2];
3291 pwd->w[2] = pws->w[2];
3292 #else
3293 pwd->w[0] = pwt->w[1];
3294 pwd->w[1] = pws->w[1];
3295 pwd->w[2] = pwt->w[3];
3296 pwd->w[3] = pws->w[3];
3297 #endif
3298 break;
3299 case DF_DOUBLE:
3300 pwd->d[0] = pwt->d[1];
3301 pwd->d[1] = pws->d[1];
3302 break;
3303 default:
3304 assert(0);
3305 }
3306 }
3307
3308 void helper_msa_ilvl_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3309 uint32_t ws, uint32_t wt)
3310 {
3311 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3312 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3313 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3314
3315 switch (df) {
3316 case DF_BYTE:
3317 #if defined(HOST_WORDS_BIGENDIAN)
3318 pwd->b[7] = pwt->b[15];
3319 pwd->b[6] = pws->b[15];
3320 pwd->b[5] = pwt->b[14];
3321 pwd->b[4] = pws->b[14];
3322 pwd->b[3] = pwt->b[13];
3323 pwd->b[2] = pws->b[13];
3324 pwd->b[1] = pwt->b[12];
3325 pwd->b[0] = pws->b[12];
3326 pwd->b[15] = pwt->b[11];
3327 pwd->b[14] = pws->b[11];
3328 pwd->b[13] = pwt->b[10];
3329 pwd->b[12] = pws->b[10];
3330 pwd->b[11] = pwt->b[9];
3331 pwd->b[10] = pws->b[9];
3332 pwd->b[9] = pwt->b[8];
3333 pwd->b[8] = pws->b[8];
3334 #else
3335 pwd->b[0] = pwt->b[8];
3336 pwd->b[1] = pws->b[8];
3337 pwd->b[2] = pwt->b[9];
3338 pwd->b[3] = pws->b[9];
3339 pwd->b[4] = pwt->b[10];
3340 pwd->b[5] = pws->b[10];
3341 pwd->b[6] = pwt->b[11];
3342 pwd->b[7] = pws->b[11];
3343 pwd->b[8] = pwt->b[12];
3344 pwd->b[9] = pws->b[12];
3345 pwd->b[10] = pwt->b[13];
3346 pwd->b[11] = pws->b[13];
3347 pwd->b[12] = pwt->b[14];
3348 pwd->b[13] = pws->b[14];
3349 pwd->b[14] = pwt->b[15];
3350 pwd->b[15] = pws->b[15];
3351 #endif
3352 break;
3353 case DF_HALF:
3354 #if defined(HOST_WORDS_BIGENDIAN)
3355 pwd->h[3] = pwt->h[7];
3356 pwd->h[2] = pws->h[7];
3357 pwd->h[1] = pwt->h[6];
3358 pwd->h[0] = pws->h[6];
3359 pwd->h[7] = pwt->h[5];
3360 pwd->h[6] = pws->h[5];
3361 pwd->h[5] = pwt->h[4];
3362 pwd->h[4] = pws->h[4];
3363 #else
3364 pwd->h[0] = pwt->h[4];
3365 pwd->h[1] = pws->h[4];
3366 pwd->h[2] = pwt->h[5];
3367 pwd->h[3] = pws->h[5];
3368 pwd->h[4] = pwt->h[6];
3369 pwd->h[5] = pws->h[6];
3370 pwd->h[6] = pwt->h[7];
3371 pwd->h[7] = pws->h[7];
3372 #endif
3373 break;
3374 case DF_WORD:
3375 #if defined(HOST_WORDS_BIGENDIAN)
3376 pwd->w[1] = pwt->w[3];
3377 pwd->w[0] = pws->w[3];
3378 pwd->w[3] = pwt->w[2];
3379 pwd->w[2] = pws->w[2];
3380 #else
3381 pwd->w[0] = pwt->w[2];
3382 pwd->w[1] = pws->w[2];
3383 pwd->w[2] = pwt->w[3];
3384 pwd->w[3] = pws->w[3];
3385 #endif
3386 break;
3387 case DF_DOUBLE:
3388 pwd->d[0] = pwt->d[1];
3389 pwd->d[1] = pws->d[1];
3390 break;
3391 default:
3392 assert(0);
3393 }
3394 }
3395
3396 void helper_msa_ilvr_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3397 uint32_t ws, uint32_t wt)
3398 {
3399 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3400 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3401 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3402
3403 switch (df) {
3404 case DF_BYTE:
3405 #if defined(HOST_WORDS_BIGENDIAN)
3406 pwd->b[8] = pws->b[0];
3407 pwd->b[9] = pwt->b[0];
3408 pwd->b[10] = pws->b[1];
3409 pwd->b[11] = pwt->b[1];
3410 pwd->b[12] = pws->b[2];
3411 pwd->b[13] = pwt->b[2];
3412 pwd->b[14] = pws->b[3];
3413 pwd->b[15] = pwt->b[3];
3414 pwd->b[0] = pws->b[4];
3415 pwd->b[1] = pwt->b[4];
3416 pwd->b[2] = pws->b[5];
3417 pwd->b[3] = pwt->b[5];
3418 pwd->b[4] = pws->b[6];
3419 pwd->b[5] = pwt->b[6];
3420 pwd->b[6] = pws->b[7];
3421 pwd->b[7] = pwt->b[7];
3422 #else
3423 pwd->b[15] = pws->b[7];
3424 pwd->b[14] = pwt->b[7];
3425 pwd->b[13] = pws->b[6];
3426 pwd->b[12] = pwt->b[6];
3427 pwd->b[11] = pws->b[5];
3428 pwd->b[10] = pwt->b[5];
3429 pwd->b[9] = pws->b[4];
3430 pwd->b[8] = pwt->b[4];
3431 pwd->b[7] = pws->b[3];
3432 pwd->b[6] = pwt->b[3];
3433 pwd->b[5] = pws->b[2];
3434 pwd->b[4] = pwt->b[2];
3435 pwd->b[3] = pws->b[1];
3436 pwd->b[2] = pwt->b[1];
3437 pwd->b[1] = pws->b[0];
3438 pwd->b[0] = pwt->b[0];
3439 #endif
3440 break;
3441 case DF_HALF:
3442 #if defined(HOST_WORDS_BIGENDIAN)
3443 pwd->h[4] = pws->h[0];
3444 pwd->h[5] = pwt->h[0];
3445 pwd->h[6] = pws->h[1];
3446 pwd->h[7] = pwt->h[1];
3447 pwd->h[0] = pws->h[2];
3448 pwd->h[1] = pwt->h[2];
3449 pwd->h[2] = pws->h[3];
3450 pwd->h[3] = pwt->h[3];
3451 #else
3452 pwd->h[7] = pws->h[3];
3453 pwd->h[6] = pwt->h[3];
3454 pwd->h[5] = pws->h[2];
3455 pwd->h[4] = pwt->h[2];
3456 pwd->h[3] = pws->h[1];
3457 pwd->h[2] = pwt->h[1];
3458 pwd->h[1] = pws->h[0];
3459 pwd->h[0] = pwt->h[0];
3460 #endif
3461 break;
3462 case DF_WORD:
3463 #if defined(HOST_WORDS_BIGENDIAN)
3464 pwd->w[2] = pws->w[0];
3465 pwd->w[3] = pwt->w[0];
3466 pwd->w[0] = pws->w[1];
3467 pwd->w[1] = pwt->w[1];
3468 #else
3469 pwd->w[3] = pws->w[1];
3470 pwd->w[2] = pwt->w[1];
3471 pwd->w[1] = pws->w[0];
3472 pwd->w[0] = pwt->w[0];
3473 #endif
3474 break;
3475 case DF_DOUBLE:
3476 pwd->d[1] = pws->d[0];
3477 pwd->d[0] = pwt->d[0];
3478 break;
3479 default:
3480 assert(0);
3481 }
3482 }
3483
3484 void helper_msa_pckev_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3485 uint32_t ws, uint32_t wt)
3486 {
3487 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3488 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3489 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3490
3491 switch (df) {
3492 case DF_BYTE:
3493 #if defined(HOST_WORDS_BIGENDIAN)
3494 pwd->b[8] = pws->b[9];
3495 pwd->b[10] = pws->b[13];
3496 pwd->b[12] = pws->b[1];
3497 pwd->b[14] = pws->b[5];
3498 pwd->b[0] = pwt->b[9];
3499 pwd->b[2] = pwt->b[13];
3500 pwd->b[4] = pwt->b[1];
3501 pwd->b[6] = pwt->b[5];
3502 pwd->b[9] = pws->b[11];
3503 pwd->b[13] = pws->b[3];
3504 pwd->b[1] = pwt->b[11];
3505 pwd->b[5] = pwt->b[3];
3506 pwd->b[11] = pws->b[15];
3507 pwd->b[3] = pwt->b[15];
3508 pwd->b[15] = pws->b[7];
3509 pwd->b[7] = pwt->b[7];
3510 #else
3511 pwd->b[15] = pws->b[14];
3512 pwd->b[13] = pws->b[10];
3513 pwd->b[11] = pws->b[6];
3514 pwd->b[9] = pws->b[2];
3515 pwd->b[7] = pwt->b[14];
3516 pwd->b[5] = pwt->b[10];
3517 pwd->b[3] = pwt->b[6];
3518 pwd->b[1] = pwt->b[2];
3519 pwd->b[14] = pws->b[12];
3520 pwd->b[10] = pws->b[4];
3521 pwd->b[6] = pwt->b[12];
3522 pwd->b[2] = pwt->b[4];
3523 pwd->b[12] = pws->b[8];
3524 pwd->b[4] = pwt->b[8];
3525 pwd->b[8] = pws->b[0];
3526 pwd->b[0] = pwt->b[0];
3527 #endif
3528 break;
3529 case DF_HALF:
3530 #if defined(HOST_WORDS_BIGENDIAN)
3531 pwd->h[4] = pws->h[5];
3532 pwd->h[6] = pws->h[1];
3533 pwd->h[0] = pwt->h[5];
3534 pwd->h[2] = pwt->h[1];
3535 pwd->h[5] = pws->h[7];
3536 pwd->h[1] = pwt->h[7];
3537 pwd->h[7] = pws->h[3];
3538 pwd->h[3] = pwt->h[3];
3539 #else
3540 pwd->h[7] = pws->h[6];
3541 pwd->h[5] = pws->h[2];
3542 pwd->h[3] = pwt->h[6];
3543 pwd->h[1] = pwt->h[2];
3544 pwd->h[6] = pws->h[4];
3545 pwd->h[2] = pwt->h[4];
3546 pwd->h[4] = pws->h[0];
3547 pwd->h[0] = pwt->h[0];
3548 #endif
3549 break;
3550 case DF_WORD:
3551 #if defined(HOST_WORDS_BIGENDIAN)
3552 pwd->w[2] = pws->w[3];
3553 pwd->w[0] = pwt->w[3];
3554 pwd->w[3] = pws->w[1];
3555 pwd->w[1] = pwt->w[1];
3556 #else
3557 pwd->w[3] = pws->w[2];
3558 pwd->w[1] = pwt->w[2];
3559 pwd->w[2] = pws->w[0];
3560 pwd->w[0] = pwt->w[0];
3561 #endif
3562 break;
3563 case DF_DOUBLE:
3564 pwd->d[1] = pws->d[0];
3565 pwd->d[0] = pwt->d[0];
3566 break;
3567 default:
3568 assert(0);
3569 }
3570 }
3571
3572 void helper_msa_pckod_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3573 uint32_t ws, uint32_t wt)
3574 {
3575 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3576 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3577 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3578
3579 switch (df) {
3580 case DF_BYTE:
3581 #if defined(HOST_WORDS_BIGENDIAN)
3582 pwd->b[7] = pwt->b[6];
3583 pwd->b[5] = pwt->b[2];
3584 pwd->b[3] = pwt->b[14];
3585 pwd->b[1] = pwt->b[10];
3586 pwd->b[15] = pws->b[6];
3587 pwd->b[13] = pws->b[2];
3588 pwd->b[11] = pws->b[14];
3589 pwd->b[9] = pws->b[10];
3590 pwd->b[6] = pwt->b[4];
3591 pwd->b[2] = pwt->b[12];
3592 pwd->b[14] = pws->b[4];
3593 pwd->b[10] = pws->b[12];
3594 pwd->b[4] = pwt->b[0];
3595 pwd->b[12] = pws->b[0];
3596 pwd->b[0] = pwt->b[8];
3597 pwd->b[8] = pws->b[8];
3598 #else
3599 pwd->b[0] = pwt->b[1];
3600 pwd->b[2] = pwt->b[5];
3601 pwd->b[4] = pwt->b[9];
3602 pwd->b[6] = pwt->b[13];
3603 pwd->b[8] = pws->b[1];
3604 pwd->b[10] = pws->b[5];
3605 pwd->b[12] = pws->b[9];
3606 pwd->b[14] = pws->b[13];
3607 pwd->b[1] = pwt->b[3];
3608 pwd->b[5] = pwt->b[11];
3609 pwd->b[9] = pws->b[3];
3610 pwd->b[13] = pws->b[11];
3611 pwd->b[3] = pwt->b[7];
3612 pwd->b[11] = pws->b[7];
3613 pwd->b[7] = pwt->b[15];
3614 pwd->b[15] = pws->b[15];
3615 #endif
3616 break;
3617 case DF_HALF:
3618 #if defined(HOST_WORDS_BIGENDIAN)
3619 pwd->h[3] = pwt->h[2];
3620 pwd->h[1] = pwt->h[6];
3621 pwd->h[7] = pws->h[2];
3622 pwd->h[5] = pws->h[6];
3623 pwd->h[2] = pwt->h[0];
3624 pwd->h[6] = pws->h[0];
3625 pwd->h[0] = pwt->h[4];
3626 pwd->h[4] = pws->h[4];
3627 #else
3628 pwd->h[0] = pwt->h[1];
3629 pwd->h[2] = pwt->h[5];
3630 pwd->h[4] = pws->h[1];
3631 pwd->h[6] = pws->h[5];
3632 pwd->h[1] = pwt->h[3];
3633 pwd->h[5] = pws->h[3];
3634 pwd->h[3] = pwt->h[7];
3635 pwd->h[7] = pws->h[7];
3636 #endif
3637 break;
3638 case DF_WORD:
3639 #if defined(HOST_WORDS_BIGENDIAN)
3640 pwd->w[1] = pwt->w[0];
3641 pwd->w[3] = pws->w[0];
3642 pwd->w[0] = pwt->w[2];
3643 pwd->w[2] = pws->w[2];
3644 #else
3645 pwd->w[0] = pwt->w[1];
3646 pwd->w[2] = pws->w[1];
3647 pwd->w[1] = pwt->w[3];
3648 pwd->w[3] = pws->w[3];
3649 #endif
3650 break;
3651 case DF_DOUBLE:
3652 pwd->d[0] = pwt->d[1];
3653 pwd->d[1] = pws->d[1];
3654 break;
3655 default:
3656 assert(0);
3657 }
3658 }
3659
3660
3661 void helper_msa_sldi_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3662 uint32_t ws, uint32_t n)
3663 {
3664 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3665 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3666
3667 msa_sld_df(df, pwd, pws, n);
3668 }
3669
3670 void helper_msa_splati_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3671 uint32_t ws, uint32_t n)
3672 {
3673 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3674 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3675
3676 msa_splat_df(df, pwd, pws, n);
3677 }
3678
3679 void helper_msa_copy_s_b(CPUMIPSState *env, uint32_t rd,
3680 uint32_t ws, uint32_t n)
3681 {
3682 n %= 16;
3683 #if defined(HOST_WORDS_BIGENDIAN)
3684 if (n < 8) {
3685 n = 8 - n - 1;
3686 } else {
3687 n = 24 - n - 1;
3688 }
3689 #endif
3690 env->active_tc.gpr[rd] = (int8_t)env->active_fpu.fpr[ws].wr.b[n];
3691 }
3692
3693 void helper_msa_copy_s_h(CPUMIPSState *env, uint32_t rd,
3694 uint32_t ws, uint32_t n)
3695 {
3696 n %= 8;
3697 #if defined(HOST_WORDS_BIGENDIAN)
3698 if (n < 4) {
3699 n = 4 - n - 1;
3700 } else {
3701 n = 12 - n - 1;
3702 }
3703 #endif
3704 env->active_tc.gpr[rd] = (int16_t)env->active_fpu.fpr[ws].wr.h[n];
3705 }
3706
3707 void helper_msa_copy_s_w(CPUMIPSState *env, uint32_t rd,
3708 uint32_t ws, uint32_t n)
3709 {
3710 n %= 4;
3711 #if defined(HOST_WORDS_BIGENDIAN)
3712 if (n < 2) {
3713 n = 2 - n - 1;
3714 } else {
3715 n = 6 - n - 1;
3716 }
3717 #endif
3718 env->active_tc.gpr[rd] = (int32_t)env->active_fpu.fpr[ws].wr.w[n];
3719 }
3720
3721 void helper_msa_copy_s_d(CPUMIPSState *env, uint32_t rd,
3722 uint32_t ws, uint32_t n)
3723 {
3724 n %= 2;
3725 env->active_tc.gpr[rd] = (int64_t)env->active_fpu.fpr[ws].wr.d[n];
3726 }
3727
3728 void helper_msa_copy_u_b(CPUMIPSState *env, uint32_t rd,
3729 uint32_t ws, uint32_t n)
3730 {
3731 n %= 16;
3732 #if defined(HOST_WORDS_BIGENDIAN)
3733 if (n < 8) {
3734 n = 8 - n - 1;
3735 } else {
3736 n = 24 - n - 1;
3737 }
3738 #endif
3739 env->active_tc.gpr[rd] = (uint8_t)env->active_fpu.fpr[ws].wr.b[n];
3740 }
3741
3742 void helper_msa_copy_u_h(CPUMIPSState *env, uint32_t rd,
3743 uint32_t ws, uint32_t n)
3744 {
3745 n %= 8;
3746 #if defined(HOST_WORDS_BIGENDIAN)
3747 if (n < 4) {
3748 n = 4 - n - 1;
3749 } else {
3750 n = 12 - n - 1;
3751 }
3752 #endif
3753 env->active_tc.gpr[rd] = (uint16_t)env->active_fpu.fpr[ws].wr.h[n];
3754 }
3755
3756 void helper_msa_copy_u_w(CPUMIPSState *env, uint32_t rd,
3757 uint32_t ws, uint32_t n)
3758 {
3759 n %= 4;
3760 #if defined(HOST_WORDS_BIGENDIAN)
3761 if (n < 2) {
3762 n = 2 - n - 1;
3763 } else {
3764 n = 6 - n - 1;
3765 }
3766 #endif
3767 env->active_tc.gpr[rd] = (uint32_t)env->active_fpu.fpr[ws].wr.w[n];
3768 }
3769
3770 void helper_msa_insert_b(CPUMIPSState *env, uint32_t wd,
3771 uint32_t rs_num, uint32_t n)
3772 {
3773 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3774 target_ulong rs = env->active_tc.gpr[rs_num];
3775 n %= 16;
3776 #if defined(HOST_WORDS_BIGENDIAN)
3777 if (n < 8) {
3778 n = 8 - n - 1;
3779 } else {
3780 n = 24 - n - 1;
3781 }
3782 #endif
3783 pwd->b[n] = (int8_t)rs;
3784 }
3785
3786 void helper_msa_insert_h(CPUMIPSState *env, uint32_t wd,
3787 uint32_t rs_num, uint32_t n)
3788 {
3789 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3790 target_ulong rs = env->active_tc.gpr[rs_num];
3791 n %= 8;
3792 #if defined(HOST_WORDS_BIGENDIAN)
3793 if (n < 4) {
3794 n = 4 - n - 1;
3795 } else {
3796 n = 12 - n - 1;
3797 }
3798 #endif
3799 pwd->h[n] = (int16_t)rs;
3800 }
3801
3802 void helper_msa_insert_w(CPUMIPSState *env, uint32_t wd,
3803 uint32_t rs_num, uint32_t n)
3804 {
3805 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3806 target_ulong rs = env->active_tc.gpr[rs_num];
3807 n %= 4;
3808 #if defined(HOST_WORDS_BIGENDIAN)
3809 if (n < 2) {
3810 n = 2 - n - 1;
3811 } else {
3812 n = 6 - n - 1;
3813 }
3814 #endif
3815 pwd->w[n] = (int32_t)rs;
3816 }
3817
3818 void helper_msa_insert_d(CPUMIPSState *env, uint32_t wd,
3819 uint32_t rs_num, uint32_t n)
3820 {
3821 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3822 target_ulong rs = env->active_tc.gpr[rs_num];
3823 n %= 2;
3824 pwd->d[n] = (int64_t)rs;
3825 }
3826
3827 void helper_msa_insve_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3828 uint32_t ws, uint32_t n)
3829 {
3830 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3831 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3832
3833 switch (df) {
3834 case DF_BYTE:
3835 pwd->b[n] = (int8_t)pws->b[0];
3836 break;
3837 case DF_HALF:
3838 pwd->h[n] = (int16_t)pws->h[0];
3839 break;
3840 case DF_WORD:
3841 pwd->w[n] = (int32_t)pws->w[0];
3842 break;
3843 case DF_DOUBLE:
3844 pwd->d[n] = (int64_t)pws->d[0];
3845 break;
3846 default:
3847 assert(0);
3848 }
3849 }
3850
3851 void helper_msa_ctcmsa(CPUMIPSState *env, target_ulong elm, uint32_t cd)
3852 {
3853 switch (cd) {
3854 case 0:
3855 break;
3856 case 1:
3857 env->active_tc.msacsr = (int32_t)elm & MSACSR_MASK;
3858 restore_msa_fp_status(env);
3859 /* check exception */
3860 if ((GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED)
3861 & GET_FP_CAUSE(env->active_tc.msacsr)) {
3862 do_raise_exception(env, EXCP_MSAFPE, GETPC());
3863 }
3864 break;
3865 }
3866 }
3867
3868 target_ulong helper_msa_cfcmsa(CPUMIPSState *env, uint32_t cs)
3869 {
3870 switch (cs) {
3871 case 0:
3872 return env->msair;
3873 case 1:
3874 return env->active_tc.msacsr & MSACSR_MASK;
3875 }
3876 return 0;
3877 }
3878
3879 void helper_msa_fill_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3880 uint32_t rs)
3881 {
3882 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3883 uint32_t i;
3884
3885 switch (df) {
3886 case DF_BYTE:
3887 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
3888 pwd->b[i] = (int8_t)env->active_tc.gpr[rs];
3889 }
3890 break;
3891 case DF_HALF:
3892 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
3893 pwd->h[i] = (int16_t)env->active_tc.gpr[rs];
3894 }
3895 break;
3896 case DF_WORD:
3897 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3898 pwd->w[i] = (int32_t)env->active_tc.gpr[rs];
3899 }
3900 break;
3901 case DF_DOUBLE:
3902 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3903 pwd->d[i] = (int64_t)env->active_tc.gpr[rs];
3904 }
3905 break;
3906 default:
3907 assert(0);
3908 }
3909 }
3910
3911
3912 #define FLOAT_ONE32 make_float32(0x3f8 << 20)
3913 #define FLOAT_ONE64 make_float64(0x3ffULL << 52)
3914
3915 #define FLOAT_SNAN16(s) (float16_default_nan(s) ^ 0x0220)
3916 /* 0x7c20 */
3917 #define FLOAT_SNAN32(s) (float32_default_nan(s) ^ 0x00400020)
3918 /* 0x7f800020 */
3919 #define FLOAT_SNAN64(s) (float64_default_nan(s) ^ 0x0008000000000020ULL)
3920 /* 0x7ff0000000000020 */
3921
3922 static inline void clear_msacsr_cause(CPUMIPSState *env)
3923 {
3924 SET_FP_CAUSE(env->active_tc.msacsr, 0);
3925 }
3926
3927 static inline void check_msacsr_cause(CPUMIPSState *env, uintptr_t retaddr)
3928 {
3929 if ((GET_FP_CAUSE(env->active_tc.msacsr) &
3930 (GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED)) == 0) {
3931 UPDATE_FP_FLAGS(env->active_tc.msacsr,
3932 GET_FP_CAUSE(env->active_tc.msacsr));
3933 } else {
3934 do_raise_exception(env, EXCP_MSAFPE, retaddr);
3935 }
3936 }
3937
3938 /* Flush-to-zero use cases for update_msacsr() */
3939 #define CLEAR_FS_UNDERFLOW 1
3940 #define CLEAR_IS_INEXACT 2
3941 #define RECIPROCAL_INEXACT 4
3942
3943 static inline int update_msacsr(CPUMIPSState *env, int action, int denormal)
3944 {
3945 int ieee_ex;
3946
3947 int c;
3948 int cause;
3949 int enable;
3950
3951 ieee_ex = get_float_exception_flags(&env->active_tc.msa_fp_status);
3952
3953 /* QEMU softfloat does not signal all underflow cases */
3954 if (denormal) {
3955 ieee_ex |= float_flag_underflow;
3956 }
3957
3958 c = ieee_ex_to_mips(ieee_ex);
3959 enable = GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED;
3960
3961 /* Set Inexact (I) when flushing inputs to zero */
3962 if ((ieee_ex & float_flag_input_denormal) &&
3963 (env->active_tc.msacsr & MSACSR_FS_MASK) != 0) {
3964 if (action & CLEAR_IS_INEXACT) {
3965 c &= ~FP_INEXACT;
3966 } else {
3967 c |= FP_INEXACT;
3968 }
3969 }
3970
3971 /* Set Inexact (I) and Underflow (U) when flushing outputs to zero */
3972 if ((ieee_ex & float_flag_output_denormal) &&
3973 (env->active_tc.msacsr & MSACSR_FS_MASK) != 0) {
3974 c |= FP_INEXACT;
3975 if (action & CLEAR_FS_UNDERFLOW) {
3976 c &= ~FP_UNDERFLOW;
3977 } else {
3978 c |= FP_UNDERFLOW;
3979 }
3980 }
3981
3982 /* Set Inexact (I) when Overflow (O) is not enabled */
3983 if ((c & FP_OVERFLOW) != 0 && (enable & FP_OVERFLOW) == 0) {
3984 c |= FP_INEXACT;
3985 }
3986
3987 /* Clear Exact Underflow when Underflow (U) is not enabled */
3988 if ((c & FP_UNDERFLOW) != 0 && (enable & FP_UNDERFLOW) == 0 &&
3989 (c & FP_INEXACT) == 0) {
3990 c &= ~FP_UNDERFLOW;
3991 }
3992
3993 /*
3994 * Reciprocal operations set only Inexact when valid and not
3995 * divide by zero
3996 */
3997 if ((action & RECIPROCAL_INEXACT) &&
3998 (c & (FP_INVALID | FP_DIV0)) == 0) {
3999 c = FP_INEXACT;
4000 }
4001
4002 cause = c & enable; /* all current enabled exceptions */
4003
4004 if (cause == 0) {
4005 /*
4006 * No enabled exception, update the MSACSR Cause
4007 * with all current exceptions
4008 */
4009 SET_FP_CAUSE(env->active_tc.msacsr,
4010 (GET_FP_CAUSE(env->active_tc.msacsr) | c));
4011 } else {
4012 /* Current exceptions are enabled */
4013 if ((env->active_tc.msacsr & MSACSR_NX_MASK) == 0) {
4014 /*
4015 * Exception(s) will trap, update MSACSR Cause
4016 * with all enabled exceptions
4017 */
4018 SET_FP_CAUSE(env->active_tc.msacsr,
4019 (GET_FP_CAUSE(env->active_tc.msacsr) | c));
4020 }
4021 }
4022
4023 return c;
4024 }
4025
4026 static inline int get_enabled_exceptions(const CPUMIPSState *env, int c)
4027 {
4028 int enable = GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED;
4029 return c & enable;
4030 }
4031
4032 static inline float16 float16_from_float32(int32_t a, flag ieee,
4033 float_status *status)
4034 {
4035 float16 f_val;
4036
4037 f_val = float32_to_float16((float32)a, ieee, status);
4038
4039 return a < 0 ? (f_val | (1 << 15)) : f_val;
4040 }
4041
4042 static inline float32 float32_from_float64(int64_t a, float_status *status)
4043 {
4044 float32 f_val;
4045
4046 f_val = float64_to_float32((float64)a, status);
4047
4048 return a < 0 ? (f_val | (1 << 31)) : f_val;
4049 }
4050
4051 static inline float32 float32_from_float16(int16_t a, flag ieee,
4052 float_status *status)
4053 {
4054 float32 f_val;
4055
4056 f_val = float16_to_float32((float16)a, ieee, status);
4057
4058 return a < 0 ? (f_val | (1 << 31)) : f_val;
4059 }
4060
4061 static inline float64 float64_from_float32(int32_t a, float_status *status)
4062 {
4063 float64 f_val;
4064
4065 f_val = float32_to_float64((float64)a, status);
4066
4067 return a < 0 ? (f_val | (1ULL << 63)) : f_val;
4068 }
4069
4070 static inline float32 float32_from_q16(int16_t a, float_status *status)
4071 {
4072 float32 f_val;
4073
4074 /* conversion as integer and scaling */
4075 f_val = int32_to_float32(a, status);
4076 f_val = float32_scalbn(f_val, -15, status);
4077
4078 return f_val;
4079 }
4080
4081 static inline float64 float64_from_q32(int32_t a, float_status *status)
4082 {
4083 float64 f_val;
4084
4085 /* conversion as integer and scaling */
4086 f_val = int32_to_float64(a, status);
4087 f_val = float64_scalbn(f_val, -31, status);
4088
4089 return f_val;
4090 }
4091
4092 static inline int16_t float32_to_q16(float32 a, float_status *status)
4093 {
4094 int32_t q_val;
4095 int32_t q_min = 0xffff8000;
4096 int32_t q_max = 0x00007fff;
4097
4098 int ieee_ex;
4099
4100 if (float32_is_any_nan(a)) {
4101 float_raise(float_flag_invalid, status);
4102 return 0;
4103 }
4104
4105 /* scaling */
4106 a = float32_scalbn(a, 15, status);
4107
4108 ieee_ex = get_float_exception_flags(status);
4109 set_float_exception_flags(ieee_ex & (~float_flag_underflow)
4110 , status);
4111
4112 if (ieee_ex & float_flag_overflow) {
4113 float_raise(float_flag_inexact, status);
4114 return (int32_t)a < 0 ? q_min : q_max;
4115 }
4116
4117 /* conversion to int */
4118 q_val = float32_to_int32(a, status);
4119
4120 ieee_ex = get_float_exception_flags(status);
4121 set_float_exception_flags(ieee_ex & (~float_flag_underflow)
4122 , status);
4123
4124 if (ieee_ex & float_flag_invalid) {
4125 set_float_exception_flags(ieee_ex & (~float_flag_invalid)
4126 , status);
4127 float_raise(float_flag_overflow | float_flag_inexact, status);
4128 return (int32_t)a < 0 ? q_min : q_max;
4129 }
4130
4131 if (q_val < q_min) {
4132 float_raise(float_flag_overflow | float_flag_inexact, status);
4133 return (int16_t)q_min;
4134 }
4135
4136 if (q_max < q_val) {
4137 float_raise(float_flag_overflow | float_flag_inexact, status);
4138 return (int16_t)q_max;
4139 }
4140
4141 return (int16_t)q_val;
4142 }
4143
4144 static inline int32_t float64_to_q32(float64 a, float_status *status)
4145 {
4146 int64_t q_val;
4147 int64_t q_min = 0xffffffff80000000LL;
4148 int64_t q_max = 0x000000007fffffffLL;
4149
4150 int ieee_ex;
4151
4152 if (float64_is_any_nan(a)) {
4153 float_raise(float_flag_invalid, status);
4154 return 0;
4155 }
4156
4157 /* scaling */
4158 a = float64_scalbn(a, 31, status);
4159
4160 ieee_ex = get_float_exception_flags(status);
4161 set_float_exception_flags(ieee_ex & (~float_flag_underflow)
4162 , status);
4163
4164 if (ieee_ex & float_flag_overflow) {
4165 float_raise(float_flag_inexact, status);
4166 return (int64_t)a < 0 ? q_min : q_max;
4167 }
4168
4169 /* conversion to integer */
4170 q_val = float64_to_int64(a, status);
4171
4172 ieee_ex = get_float_exception_flags(status);
4173 set_float_exception_flags(ieee_ex & (~float_flag_underflow)
4174 , status);
4175
4176 if (ieee_ex & float_flag_invalid) {
4177 set_float_exception_flags(ieee_ex & (~float_flag_invalid)
4178 , status);
4179 float_raise(float_flag_overflow | float_flag_inexact, status);
4180 return (int64_t)a < 0 ? q_min : q_max;
4181 }
4182
4183 if (q_val < q_min) {
4184 float_raise(float_flag_overflow | float_flag_inexact, status);
4185 return (int32_t)q_min;
4186 }
4187
4188 if (q_max < q_val) {
4189 float_raise(float_flag_overflow | float_flag_inexact, status);
4190 return (int32_t)q_max;
4191 }
4192
4193 return (int32_t)q_val;
4194 }
4195
4196 #define MSA_FLOAT_COND(DEST, OP, ARG1, ARG2, BITS, QUIET) \
4197 do { \
4198 float_status *status = &env->active_tc.msa_fp_status; \
4199 int c; \
4200 int64_t cond; \
4201 set_float_exception_flags(0, status); \
4202 if (!QUIET) { \
4203 cond = float ## BITS ## _ ## OP(ARG1, ARG2, status); \
4204 } else { \
4205 cond = float ## BITS ## _ ## OP ## _quiet(ARG1, ARG2, status); \
4206 } \
4207 DEST = cond ? M_MAX_UINT(BITS) : 0; \
4208 c = update_msacsr(env, CLEAR_IS_INEXACT, 0); \
4209 \
4210 if (get_enabled_exceptions(env, c)) { \
4211 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
4212 } \
4213 } while (0)
4214
4215 #define MSA_FLOAT_AF(DEST, ARG1, ARG2, BITS, QUIET) \
4216 do { \
4217 MSA_FLOAT_COND(DEST, eq, ARG1, ARG2, BITS, QUIET); \
4218 if ((DEST & M_MAX_UINT(BITS)) == M_MAX_UINT(BITS)) { \
4219 DEST = 0; \
4220 } \
4221 } while (0)
4222
4223 #define MSA_FLOAT_UEQ(DEST, ARG1, ARG2, BITS, QUIET) \
4224 do { \
4225 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
4226 if (DEST == 0) { \
4227 MSA_FLOAT_COND(DEST, eq, ARG1, ARG2, BITS, QUIET); \
4228 } \
4229 } while (0)
4230
4231 #define MSA_FLOAT_NE(DEST, ARG1, ARG2, BITS, QUIET) \
4232 do { \
4233 MSA_FLOAT_COND(DEST, lt, ARG1, ARG2, BITS, QUIET); \
4234 if (DEST == 0) { \
4235 MSA_FLOAT_COND(DEST, lt, ARG2, ARG1, BITS, QUIET); \
4236 } \
4237 } while (0)
4238
4239 #define MSA_FLOAT_UNE(DEST, ARG1, ARG2, BITS, QUIET) \
4240 do { \
4241 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
4242 if (DEST == 0) { \
4243 MSA_FLOAT_COND(DEST, lt, ARG1, ARG2, BITS, QUIET); \
4244 if (DEST == 0) { \
4245 MSA_FLOAT_COND(DEST, lt, ARG2, ARG1, BITS, QUIET); \
4246 } \
4247 } \
4248 } while (0)
4249
4250 #define MSA_FLOAT_ULE(DEST, ARG1, ARG2, BITS, QUIET) \
4251 do { \
4252 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
4253 if (DEST == 0) { \
4254 MSA_FLOAT_COND(DEST, le, ARG1, ARG2, BITS, QUIET); \
4255 } \
4256 } while (0)
4257
4258 #define MSA_FLOAT_ULT(DEST, ARG1, ARG2, BITS, QUIET) \
4259 do { \
4260 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
4261 if (DEST == 0) { \
4262 MSA_FLOAT_COND(DEST, lt, ARG1, ARG2, BITS, QUIET); \
4263 } \
4264 } while (0)
4265
4266 #define MSA_FLOAT_OR(DEST, ARG1, ARG2, BITS, QUIET) \
4267 do { \
4268 MSA_FLOAT_COND(DEST, le, ARG1, ARG2, BITS, QUIET); \
4269 if (DEST == 0) { \
4270 MSA_FLOAT_COND(DEST, le, ARG2, ARG1, BITS, QUIET); \
4271 } \
4272 } while (0)
4273
4274 static inline void compare_af(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
4275 wr_t *pwt, uint32_t df, int quiet,
4276 uintptr_t retaddr)
4277 {
4278 wr_t wx, *pwx = &wx;
4279 uint32_t i;
4280
4281 clear_msacsr_cause(env);
4282
4283 switch (df) {
4284 case DF_WORD:
4285 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
4286 MSA_FLOAT_AF(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
4287 }
4288 break;
4289 case DF_DOUBLE:
4290 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
4291 MSA_FLOAT_AF(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
4292 }
4293 break;
4294 default:
4295 assert(0);
4296 }
4297
4298 check_msacsr_cause(env, retaddr);
4299
4300 msa_move_v(pwd, pwx);
4301 }
4302
4303 static inline void compare_un(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
4304 wr_t *pwt, uint32_t df, int quiet,
4305 uintptr_t retaddr)
4306 {
4307 wr_t wx, *pwx = &wx;
4308 uint32_t i;
4309
4310 clear_msacsr_cause(env);
4311
4312 switch (df) {
4313 case DF_WORD:
4314 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
4315 MSA_FLOAT_COND(pwx->w[i], unordered, pws->w[i], pwt->w[i], 32,
4316 quiet);
4317 }
4318 break;
4319 case DF_DOUBLE:
4320 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
4321 MSA_FLOAT_COND(pwx->d[i], unordered, pws->d[i], pwt->d[i], 64,
4322 quiet);
4323 }
4324 break;
4325 default:
4326 assert(0);
4327 }
4328
4329 check_msacsr_cause(env, retaddr);
4330
4331 msa_move_v(pwd, pwx);
4332 }
4333
4334 static inline void compare_eq(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
4335 wr_t *pwt, uint32_t df, int quiet,
4336 uintptr_t retaddr)
4337 {
4338 wr_t wx, *pwx = &wx;
4339 uint32_t i;
4340
4341 clear_msacsr_cause(env);
4342
4343 switch (df) {
4344 case DF_WORD:
4345 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
4346 MSA_FLOAT_COND(pwx->w[i], eq, pws->w[i], pwt->w[i], 32, quiet);
4347 }
4348 break;
4349 case DF_DOUBLE:
4350 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
4351 MSA_FLOAT_COND(pwx->d[i], eq, pws->d[i], pwt->d[i], 64, quiet);
4352 }
4353 break;
4354 default:
4355 assert(0);
4356 }
4357
4358 check_msacsr_cause(env, retaddr);
4359
4360 msa_move_v(pwd, pwx);
4361 }
4362
4363 static inline void compare_ueq(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
4364 wr_t *pwt, uint32_t df, int quiet,
4365 uintptr_t retaddr)
4366 {
4367 wr_t wx, *pwx = &wx;
4368 uint32_t i;
4369
4370 clear_msacsr_cause(env);
4371
4372 switch (df) {
4373 case DF_WORD:
4374 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
4375 MSA_FLOAT_UEQ(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
4376 }
4377 break;
4378 case DF_DOUBLE:
4379 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
4380 MSA_FLOAT_UEQ(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
4381 }
4382 break;
4383 default:
4384 assert(0);
4385 }
4386
4387 check_msacsr_cause(env, retaddr);
4388
4389 msa_move_v(pwd, pwx);
4390 }
4391
4392 static inline void compare_lt(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
4393 wr_t *pwt, uint32_t df, int quiet,
4394 uintptr_t retaddr)
4395 {
4396 wr_t wx, *pwx = &wx;
4397 uint32_t i;
4398
4399 clear_msacsr_cause(env);
4400
4401 switch (df) {
4402 case DF_WORD:
4403 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
4404 MSA_FLOAT_COND(pwx->w[i], lt, pws->w[i], pwt->w[i], 32, quiet);
4405 }
4406 break;
4407 case DF_DOUBLE:
4408 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
4409 MSA_FLOAT_COND(pwx->d[i], lt, pws->d[i], pwt->d[i], 64, quiet);
4410 }
4411 break;
4412 default:
4413 assert(0);
4414 }
4415
4416 check_msacsr_cause(env, retaddr);
4417
4418 msa_move_v(pwd, pwx);
4419 }
4420
4421 static inline void compare_ult(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
4422 wr_t *pwt, uint32_t df, int quiet,
4423 uintptr_t retaddr)
4424 {
4425 wr_t wx, *pwx = &wx;
4426 uint32_t i;
4427
4428 clear_msacsr_cause(env);
4429
4430 switch (df) {
4431 case DF_WORD:
4432 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
4433 MSA_FLOAT_ULT(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
4434 }
4435 break;
4436 case DF_DOUBLE:
4437 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
4438 MSA_FLOAT_ULT(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
4439 }
4440 break;
4441 default:
4442 assert(0);
4443 }
4444
4445 check_msacsr_cause(env, retaddr);
4446
4447 msa_move_v(pwd, pwx);
4448 }
4449
4450 static inline void compare_le(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
4451 wr_t *pwt, uint32_t df, int quiet,
4452 uintptr_t retaddr)
4453 {
4454 wr_t wx, *pwx = &wx;
4455 uint32_t i;
4456
4457 clear_msacsr_cause(env);
4458
4459 switch (df) {
4460 case DF_WORD:
4461 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
4462 MSA_FLOAT_COND(pwx->w[i], le, pws->w[i], pwt->w[i], 32, quiet);
4463 }
4464 break;
4465 case DF_DOUBLE:
4466 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
4467 MSA_FLOAT_COND(pwx->d[i], le, pws->d[i], pwt->d[i], 64, quiet);
4468 }
4469 break;
4470 default:
4471 assert(0);
4472 }
4473
4474 check_msacsr_cause(env, retaddr);
4475
4476 msa_move_v(pwd, pwx);
4477 }
4478
4479 static inline void compare_ule(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
4480 wr_t *pwt, uint32_t df, int quiet,
4481 uintptr_t retaddr)
4482 {
4483 wr_t wx, *pwx = &wx;
4484 uint32_t i;
4485
4486 clear_msacsr_cause(env);
4487
4488 switch (df) {
4489 case DF_WORD:
4490 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
4491 MSA_FLOAT_ULE(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
4492 }
4493 break;
4494 case DF_DOUBLE:
4495 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
4496 MSA_FLOAT_ULE(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
4497 }
4498 break;
4499 default:
4500 assert(0);
4501 }
4502
4503 check_msacsr_cause(env, retaddr);
4504
4505 msa_move_v(pwd, pwx);
4506 }
4507
4508 static inline void compare_or(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
4509 wr_t *pwt, uint32_t df, int quiet,
4510 uintptr_t retaddr)
4511 {
4512 wr_t wx, *pwx = &wx;
4513 uint32_t i;
4514
4515 clear_msacsr_cause(env);
4516
4517 switch (df) {
4518 case DF_WORD:
4519 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
4520 MSA_FLOAT_OR(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
4521 }
4522 break;
4523 case DF_DOUBLE:
4524 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
4525 MSA_FLOAT_OR(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
4526 }
4527 break;
4528 default:
4529 assert(0);
4530 }
4531
4532 check_msacsr_cause(env, retaddr);
4533
4534 msa_move_v(pwd, pwx);
4535 }
4536
4537 static inline void compare_une(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
4538 wr_t *pwt, uint32_t df, int quiet,
4539 uintptr_t retaddr)
4540 {
4541 wr_t wx, *pwx = &wx;
4542 uint32_t i;
4543
4544 clear_msacsr_cause(env);
4545
4546 switch (df) {
4547 case DF_WORD:
4548 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
4549 MSA_FLOAT_UNE(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
4550 }
4551 break;
4552 case DF_DOUBLE:
4553 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
4554 MSA_FLOAT_UNE(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
4555 }
4556 break;
4557 default:
4558 assert(0);
4559 }
4560
4561 check_msacsr_cause(env, retaddr);
4562
4563 msa_move_v(pwd, pwx);
4564 }
4565
4566 static inline void compare_ne(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
4567 wr_t *pwt, uint32_t df, int quiet,
4568 uintptr_t retaddr)
4569 {
4570 wr_t wx, *pwx = &wx;
4571 uint32_t i;
4572
4573 clear_msacsr_cause(env);
4574
4575 switch (df) {
4576 case DF_WORD:
4577 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
4578 MSA_FLOAT_NE(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
4579 }
4580 break;
4581 case DF_DOUBLE:
4582 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
4583 MSA_FLOAT_NE(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
4584 }
4585 break;
4586 default:
4587 assert(0);
4588 }
4589
4590 check_msacsr_cause(env, retaddr);
4591
4592 msa_move_v(pwd, pwx);
4593 }
4594
4595 void helper_msa_fcaf_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
4596 uint32_t ws, uint32_t wt)
4597 {
4598 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4599 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
4600 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
4601 compare_af(env, pwd, pws, pwt, df, 1, GETPC());
4602 }
4603
4604 void helper_msa_fcun_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
4605 uint32_t ws, uint32_t wt)
4606 {
4607 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4608 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
4609 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
4610 compare_un(env, pwd, pws, pwt, df, 1, GETPC());
4611 }
4612
4613 void helper_msa_fceq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
4614 uint32_t ws, uint32_t wt)
4615 {
4616 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4617 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
4618 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
4619 compare_eq(env, pwd, pws, pwt, df, 1, GETPC());
4620 }
4621
4622 void helper_msa_fcueq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
4623 uint32_t ws, uint32_t wt)
4624 {
4625 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4626 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
4627 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
4628 compare_ueq(env, pwd, pws, pwt, df, 1, GETPC());
4629 }
4630
4631 void helper_msa_fclt_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
4632 uint32_t ws, uint32_t wt)
4633 {
4634 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4635 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
4636 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
4637 compare_lt(env, pwd, pws, pwt, df, 1, GETPC());
4638 }
4639
4640 void helper_msa_fcult_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
4641 uint32_t ws, uint32_t wt)
4642 {
4643 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4644 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
4645 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
4646 compare_ult(env, pwd, pws, pwt, df, 1, GETPC());
4647 }
4648
4649 void helper_msa_fcle_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
4650 uint32_t ws, uint32_t wt)
4651 {
4652 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4653 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
4654 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
4655 compare_le(env, pwd, pws, pwt, df, 1, GETPC());
4656 }
4657
4658 void helper_msa_fcule_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
4659 uint32_t ws, uint32_t wt)
4660 {
4661 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4662 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
4663 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
4664 compare_ule(env, pwd, pws, pwt, df, 1, GETPC());
4665 }
4666
4667 void helper_msa_fsaf_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
4668 uint32_t ws, uint32_t wt)
4669 {
4670 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4671 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
4672 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
4673 compare_af(env, pwd, pws, pwt, df, 0, GETPC());
4674 }
4675
4676 void helper_msa_fsun_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
4677 uint32_t ws, uint32_t wt)
4678 {
4679 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4680 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
4681 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
4682 compare_un(env, pwd, pws, pwt, df, 0, GETPC());
4683 }
4684
4685 void helper_msa_fseq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
4686 uint32_t ws, uint32_t wt)
4687 {
4688 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4689 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
4690 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
4691 compare_eq(env, pwd, pws, pwt, df, 0, GETPC());
4692 }
4693
4694 void helper_msa_fsueq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
4695 uint32_t ws, uint32_t wt)
4696 {
4697 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4698 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
4699 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
4700 compare_ueq(env, pwd, pws, pwt, df, 0, GETPC());
4701 }
4702
4703 void helper_msa_fslt_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
4704 uint32_t ws, uint32_t wt)
4705 {
4706 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4707 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
4708 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
4709 compare_lt(env, pwd, pws, pwt, df, 0, GETPC());
4710 }
4711
4712 void helper_msa_fsult_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
4713 uint32_t ws, uint32_t wt)
4714 {
4715 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4716 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
4717 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
4718 compare_ult(env, pwd, pws, pwt, df, 0, GETPC());
4719 }
4720
4721 void helper_msa_fsle_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
4722 uint32_t ws, uint32_t wt)
4723 {
4724 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4725 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
4726 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
4727 compare_le(env, pwd, pws, pwt, df, 0, GETPC());
4728 }
4729
4730 void helper_msa_fsule_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
4731 uint32_t ws, uint32_t wt)
4732 {
4733 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4734 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
4735 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
4736 compare_ule(env, pwd, pws, pwt, df, 0, GETPC());
4737 }
4738
4739 void helper_msa_fcor_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
4740 uint32_t ws, uint32_t wt)
4741 {
4742 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4743 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
4744 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
4745 compare_or(env, pwd, pws, pwt, df, 1, GETPC());
4746 }
4747
4748 void helper_msa_fcune_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
4749 uint32_t ws, uint32_t wt)
4750 {
4751 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4752 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
4753 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
4754 compare_une(env, pwd, pws, pwt, df, 1, GETPC());
4755 }
4756
4757 void helper_msa_fcne_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
4758 uint32_t ws, uint32_t wt)
4759 {
4760 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4761 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
4762 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
4763 compare_ne(env, pwd, pws, pwt, df, 1, GETPC());
4764 }
4765
4766 void helper_msa_fsor_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
4767 uint32_t ws, uint32_t wt)
4768 {
4769 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4770 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
4771 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
4772 compare_or(env, pwd, pws, pwt, df, 0, GETPC());
4773 }
4774
4775 void helper_msa_fsune_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
4776 uint32_t ws, uint32_t wt)
4777 {
4778 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4779 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
4780 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
4781 compare_une(env, pwd, pws, pwt, df, 0, GETPC());
4782 }
4783
4784 void helper_msa_fsne_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
4785 uint32_t ws, uint32_t wt)
4786 {
4787 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4788 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
4789 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
4790 compare_ne(env, pwd, pws, pwt, df, 0, GETPC());
4791 }
4792
4793 #define float16_is_zero(ARG) 0
4794 #define float16_is_zero_or_denormal(ARG) 0
4795
4796 #define IS_DENORMAL(ARG, BITS) \
4797 (!float ## BITS ## _is_zero(ARG) \
4798 && float ## BITS ## _is_zero_or_denormal(ARG))
4799
4800 #define MSA_FLOAT_BINOP(DEST, OP, ARG1, ARG2, BITS) \
4801 do { \
4802 float_status *status = &env->active_tc.msa_fp_status; \
4803 int c; \
4804 \
4805 set_float_exception_flags(0, status); \
4806 DEST = float ## BITS ## _ ## OP(ARG1, ARG2, status); \
4807 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
4808 \
4809 if (get_enabled_exceptions(env, c)) { \
4810 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
4811 } \
4812 } while (0)
4813
4814 void helper_msa_fadd_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
4815 uint32_t ws, uint32_t wt)
4816 {
4817 wr_t wx, *pwx = &wx;
4818 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4819 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
4820 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
4821 uint32_t i;
4822
4823 clear_msacsr_cause(env);
4824
4825 switch (df) {
4826 case DF_WORD:
4827 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
4828 MSA_FLOAT_BINOP(pwx->w[i], add, pws->w[i], pwt->w[i], 32);
4829 }
4830 break;
4831 case DF_DOUBLE:
4832 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
4833 MSA_FLOAT_BINOP(pwx->d[i], add, pws->d[i], pwt->d[i], 64);
4834 }
4835 break;
4836 default:
4837 assert(0);
4838 }
4839
4840 check_msacsr_cause(env, GETPC());
4841 msa_move_v(pwd, pwx);
4842 }
4843
4844 void helper_msa_fsub_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
4845 uint32_t ws, uint32_t wt)
4846 {
4847 wr_t wx, *pwx = &wx;
4848 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4849 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
4850 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
4851 uint32_t i;
4852
4853 clear_msacsr_cause(env);
4854
4855 switch (df) {
4856 case DF_WORD:
4857 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
4858 MSA_FLOAT_BINOP(pwx->w[i], sub, pws->w[i], pwt->w[i], 32);
4859 }
4860 break;
4861 case DF_DOUBLE:
4862 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
4863 MSA_FLOAT_BINOP(pwx->d[i], sub, pws->d[i], pwt->d[i], 64);
4864 }
4865 break;
4866 default:
4867 assert(0);
4868 }
4869
4870 check_msacsr_cause(env, GETPC());
4871 msa_move_v(pwd, pwx);
4872 }
4873
4874 void helper_msa_fmul_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
4875 uint32_t ws, uint32_t wt)
4876 {
4877 wr_t wx, *pwx = &wx;
4878 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4879 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
4880 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
4881 uint32_t i;
4882
4883 clear_msacsr_cause(env);
4884
4885 switch (df) {
4886 case DF_WORD:
4887 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
4888 MSA_FLOAT_BINOP(pwx->w[i], mul, pws->w[i], pwt->w[i], 32);
4889 }
4890 break;
4891 case DF_DOUBLE:
4892 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
4893 MSA_FLOAT_BINOP(pwx->d[i], mul, pws->d[i], pwt->d[i], 64);
4894 }
4895 break;
4896 default:
4897 assert(0);
4898 }
4899
4900 check_msacsr_cause(env, GETPC());
4901
4902 msa_move_v(pwd, pwx);
4903 }
4904
4905 void helper_msa_fdiv_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
4906 uint32_t ws, uint32_t wt)
4907 {
4908 wr_t wx, *pwx = &wx;
4909 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4910 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
4911 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
4912 uint32_t i;
4913
4914 clear_msacsr_cause(env);
4915
4916 switch (df) {
4917 case DF_WORD:
4918 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
4919 MSA_FLOAT_BINOP(pwx->w[i], div, pws->w[i], pwt->w[i], 32);
4920 }
4921 break;
4922 case DF_DOUBLE:
4923 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
4924 MSA_FLOAT_BINOP(pwx->d[i], div, pws->d[i], pwt->d[i], 64);
4925 }
4926 break;
4927 default:
4928 assert(0);
4929 }
4930
4931 check_msacsr_cause(env, GETPC());
4932
4933 msa_move_v(pwd, pwx);
4934 }
4935
4936 #define MSA_FLOAT_MULADD(DEST, ARG1, ARG2, ARG3, NEGATE, BITS) \
4937 do { \
4938 float_status *status = &env->active_tc.msa_fp_status; \
4939 int c; \
4940 \
4941 set_float_exception_flags(0, status); \
4942 DEST = float ## BITS ## _muladd(ARG2, ARG3, ARG1, NEGATE, status); \
4943 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
4944 \
4945 if (get_enabled_exceptions(env, c)) { \
4946 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
4947 } \
4948 } while (0)
4949
4950 void helper_msa_fmadd_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
4951 uint32_t ws, uint32_t wt)
4952 {
4953 wr_t wx, *pwx = &wx;
4954 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4955 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
4956 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
4957 uint32_t i;
4958
4959 clear_msacsr_cause(env);
4960
4961 switch (df) {
4962 case DF_WORD:
4963 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
4964 MSA_FLOAT_MULADD(pwx->w[i], pwd->w[i],
4965 pws->w[i], pwt->w[i], 0, 32);
4966 }
4967 break;
4968 case DF_DOUBLE:
4969 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
4970 MSA_FLOAT_MULADD(pwx->d[i], pwd->d[i],
4971 pws->d[i], pwt->d[i], 0, 64);
4972 }
4973 break;
4974 default:
4975 assert(0);
4976 }
4977
4978 check_msacsr_cause(env, GETPC());
4979
4980 msa_move_v(pwd, pwx);
4981 }
4982
4983 void helper_msa_fmsub_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
4984 uint32_t ws, uint32_t wt)
4985 {
4986 wr_t wx, *pwx = &wx;
4987 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4988 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
4989 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
4990 uint32_t i;
4991
4992 clear_msacsr_cause(env);
4993
4994 switch (df) {
4995 case DF_WORD:
4996 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
4997 MSA_FLOAT_MULADD(pwx->w[i], pwd->w[i],
4998 pws->w[i], pwt->w[i],
4999 float_muladd_negate_product, 32);
5000 }
5001 break;
5002 case DF_DOUBLE:
5003 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
5004 MSA_FLOAT_MULADD(pwx->d[i], pwd->d[i],
5005 pws->d[i], pwt->d[i],
5006 float_muladd_negate_product, 64);
5007 }
5008 break;
5009 default:
5010 assert(0);
5011 }
5012
5013 check_msacsr_cause(env, GETPC());
5014
5015 msa_move_v(pwd, pwx);
5016 }
5017
5018 void helper_msa_fexp2_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
5019 uint32_t ws, uint32_t wt)
5020 {
5021 wr_t wx, *pwx = &wx;
5022 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
5023 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
5024 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
5025 uint32_t i;
5026
5027 clear_msacsr_cause(env);
5028
5029 switch (df) {
5030 case DF_WORD:
5031 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
5032 MSA_FLOAT_BINOP(pwx->w[i], scalbn, pws->w[i],
5033 pwt->w[i] > 0x200 ? 0x200 :
5034 pwt->w[i] < -0x200 ? -0x200 : pwt->w[i],
5035 32);
5036 }
5037 break;
5038 case DF_DOUBLE:
5039 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
5040 MSA_FLOAT_BINOP(pwx->d[i], scalbn, pws->d[i],
5041 pwt->d[i] > 0x1000 ? 0x1000 :
5042 pwt->d[i] < -0x1000 ? -0x1000 : pwt->d[i],
5043 64);
5044 }
5045 break;
5046 default:
5047 assert(0);
5048 }
5049
5050 check_msacsr_cause(env, GETPC());
5051
5052 msa_move_v(pwd, pwx);
5053 }
5054
5055 #define MSA_FLOAT_UNOP(DEST, OP, ARG, BITS) \
5056 do { \
5057 float_status *status = &env->active_tc.msa_fp_status; \
5058 int c; \
5059 \
5060 set_float_exception_flags(0, status); \
5061 DEST = float ## BITS ## _ ## OP(ARG, status); \
5062 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
5063 \
5064 if (get_enabled_exceptions(env, c)) { \
5065 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
5066 } \
5067 } while (0)
5068
5069 void helper_msa_fexdo_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
5070 uint32_t ws, uint32_t wt)
5071 {
5072 wr_t wx, *pwx = &wx;
5073 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
5074 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
5075 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
5076 uint32_t i;
5077
5078 clear_msacsr_cause(env);
5079
5080 switch (df) {
5081 case DF_WORD:
5082 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
5083 /*
5084 * Half precision floats come in two formats: standard
5085 * IEEE and "ARM" format. The latter gains extra exponent
5086 * range by omitting the NaN/Inf encodings.
5087 */
5088 flag ieee = 1;
5089
5090 MSA_FLOAT_BINOP(Lh(pwx, i), from_float32, pws->w[i], ieee, 16);
5091 MSA_FLOAT_BINOP(Rh(pwx, i), from_float32, pwt->w[i], ieee, 16);
5092 }
5093 break;
5094 case DF_DOUBLE:
5095 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
5096 MSA_FLOAT_UNOP(Lw(pwx, i), from_float64, pws->d[i], 32);
5097 MSA_FLOAT_UNOP(Rw(pwx, i), from_float64, pwt->d[i], 32);
5098 }
5099 break;
5100 default:
5101 assert(0);
5102 }
5103
5104 check_msacsr_cause(env, GETPC());
5105 msa_move_v(pwd, pwx);
5106 }
5107
5108 #define MSA_FLOAT_UNOP_XD(DEST, OP, ARG, BITS, XBITS) \
5109 do { \
5110 float_status *status = &env->active_tc.msa_fp_status; \
5111 int c; \
5112 \
5113 set_float_exception_flags(0, status); \
5114 DEST = float ## BITS ## _ ## OP(ARG, status); \
5115 c = update_msacsr(env, CLEAR_FS_UNDERFLOW, 0); \
5116 \
5117 if (get_enabled_exceptions(env, c)) { \
5118 DEST = ((FLOAT_SNAN ## XBITS(status) >> 6) << 6) | c; \
5119 } \
5120 } while (0)
5121
5122 void helper_msa_ftq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
5123 uint32_t ws, uint32_t wt)
5124 {
5125 wr_t wx, *pwx = &wx;
5126 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
5127 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
5128 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
5129 uint32_t i;
5130
5131 clear_msacsr_cause(env);
5132
5133 switch (df) {
5134 case DF_WORD:
5135 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
5136 MSA_FLOAT_UNOP_XD(Lh(pwx, i), to_q16, pws->w[i], 32, 16);
5137 MSA_FLOAT_UNOP_XD(Rh(pwx, i), to_q16, pwt->w[i], 32, 16);
5138 }
5139 break;
5140 case DF_DOUBLE:
5141 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
5142 MSA_FLOAT_UNOP_XD(Lw(pwx, i), to_q32, pws->d[i], 64, 32);
5143 MSA_FLOAT_UNOP_XD(Rw(pwx, i), to_q32, pwt->d[i], 64, 32);
5144 }
5145 break;
5146 default:
5147 assert(0);
5148 }
5149
5150 check_msacsr_cause(env, GETPC());
5151
5152 msa_move_v(pwd, pwx);
5153 }
5154
5155 #define NUMBER_QNAN_PAIR(ARG1, ARG2, BITS, STATUS) \
5156 !float ## BITS ## _is_any_nan(ARG1) \
5157 && float ## BITS ## _is_quiet_nan(ARG2, STATUS)
5158
5159 #define MSA_FLOAT_MAXOP(DEST, OP, ARG1, ARG2, BITS) \
5160 do { \
5161 float_status *status = &env->active_tc.msa_fp_status; \
5162 int c; \
5163 \
5164 set_float_exception_flags(0, status); \
5165 DEST = float ## BITS ## _ ## OP(ARG1, ARG2, status); \
5166 c = update_msacsr(env, 0, 0); \
5167 \
5168 if (get_enabled_exceptions(env, c)) { \
5169 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
5170 } \
5171 } while (0)
5172
5173 #define FMAXMIN_A(F, G, X, _S, _T, BITS, STATUS) \
5174 do { \
5175 uint## BITS ##_t S = _S, T = _T; \
5176 uint## BITS ##_t as, at, xs, xt, xd; \
5177 if (NUMBER_QNAN_PAIR(S, T, BITS, STATUS)) { \
5178 T = S; \
5179 } \
5180 else if (NUMBER_QNAN_PAIR(T, S, BITS, STATUS)) { \
5181 S = T; \
5182 } \
5183 as = float## BITS ##_abs(S); \
5184 at = float## BITS ##_abs(T); \
5185 MSA_FLOAT_MAXOP(xs, F, S, T, BITS); \
5186 MSA_FLOAT_MAXOP(xt, G, S, T, BITS); \
5187 MSA_FLOAT_MAXOP(xd, F, as, at, BITS); \
5188 X = (as == at || xd == float## BITS ##_abs(xs)) ? xs : xt; \
5189 } while (0)
5190
5191 void helper_msa_fmin_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
5192 uint32_t ws, uint32_t wt)
5193 {
5194 float_status *status = &env->active_tc.msa_fp_status;
5195 wr_t wx, *pwx = &wx;
5196 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
5197 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
5198 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
5199
5200 clear_msacsr_cause(env);
5201
5202 if (df == DF_WORD) {
5203
5204 if (NUMBER_QNAN_PAIR(pws->w[0], pwt->w[0], 32, status)) {
5205 MSA_FLOAT_MAXOP(pwx->w[0], min, pws->w[0], pws->w[0], 32);
5206 } else if (NUMBER_QNAN_PAIR(pwt->w[0], pws->w[0], 32, status)) {
5207 MSA_FLOAT_MAXOP(pwx->w[0], min, pwt->w[0], pwt->w[0], 32);
5208 } else {
5209 MSA_FLOAT_MAXOP(pwx->w[0], min, pws->w[0], pwt->w[0], 32);
5210 }
5211
5212 if (NUMBER_QNAN_PAIR(pws->w[1], pwt->w[1], 32, status)) {
5213 MSA_FLOAT_MAXOP(pwx->w[1], min, pws->w[1], pws->w[1], 32);
5214 } else if (NUMBER_QNAN_PAIR(pwt->w[1], pws->w[1], 32, status)) {
5215 MSA_FLOAT_MAXOP(pwx->w[1], min, pwt->w[1], pwt->w[1], 32);
5216 } else {
5217 MSA_FLOAT_MAXOP(pwx->w[1], min, pws->w[1], pwt->w[1], 32);
5218 }
5219
5220 if (NUMBER_QNAN_PAIR(pws->w[2], pwt->w[2], 32, status)) {
5221 MSA_FLOAT_MAXOP(pwx->w[2], min, pws->w[2], pws->w[2], 32);
5222 } else if (NUMBER_QNAN_PAIR(pwt->w[2], pws->w[2], 32, status)) {
5223 MSA_FLOAT_MAXOP(pwx->w[2], min, pwt->w[2], pwt->w[2], 32);
5224 } else {
5225 MSA_FLOAT_MAXOP(pwx->w[2], min, pws->w[2], pwt->w[2], 32);
5226 }
5227
5228 if (NUMBER_QNAN_PAIR(pws->w[3], pwt->w[3], 32, status)) {
5229 MSA_FLOAT_MAXOP(pwx->w[3], min, pws->w[3], pws->w[3], 32);
5230 } else if (NUMBER_QNAN_PAIR(pwt->w[3], pws->w[3], 32, status)) {
5231 MSA_FLOAT_MAXOP(pwx->w[3], min, pwt->w[3], pwt->w[3], 32);
5232 } else {
5233 MSA_FLOAT_MAXOP(pwx->w[3], min, pws->w[3], pwt->w[3], 32);
5234 }
5235
5236 } else if (df == DF_DOUBLE) {
5237
5238 if (NUMBER_QNAN_PAIR(pws->d[0], pwt->d[0], 64, status)) {
5239 MSA_FLOAT_MAXOP(pwx->d[0], min, pws->d[0], pws->d[0], 64);
5240 } else if (NUMBER_QNAN_PAIR(pwt->d[0], pws->d[0], 64, status)) {
5241 MSA_FLOAT_MAXOP(pwx->d[0], min, pwt->d[0], pwt->d[0], 64);
5242 } else {
5243 MSA_FLOAT_MAXOP(pwx->d[0], min, pws->d[0], pwt->d[0], 64);
5244 }
5245
5246 if (NUMBER_QNAN_PAIR(pws->d[1], pwt->d[1], 64, status)) {
5247 MSA_FLOAT_MAXOP(pwx->d[1], min, pws->d[1], pws->d[1], 64);
5248 } else if (NUMBER_QNAN_PAIR(pwt->d[1], pws->d[1], 64, status)) {
5249 MSA_FLOAT_MAXOP(pwx->d[1], min, pwt->d[1], pwt->d[1], 64);
5250 } else {
5251 MSA_FLOAT_MAXOP(pwx->d[1], min, pws->d[1], pwt->d[1], 64);
5252 }
5253
5254 } else {
5255
5256 assert(0);
5257
5258 }
5259
5260 check_msacsr_cause(env, GETPC());
5261
5262 msa_move_v(pwd, pwx);
5263 }
5264
5265 void helper_msa_fmin_a_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
5266 uint32_t ws, uint32_t wt)
5267 {
5268 float_status *status = &env->active_tc.msa_fp_status;
5269 wr_t wx, *pwx = &wx;
5270 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
5271 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
5272 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
5273
5274 clear_msacsr_cause(env);
5275
5276 if (df == DF_WORD) {
5277 FMAXMIN_A(min, max, pwx->w[0], pws->w[0], pwt->w[0], 32, status);
5278 FMAXMIN_A(min, max, pwx->w[1], pws->w[1], pwt->w[1], 32, status);
5279 FMAXMIN_A(min, max, pwx->w[2], pws->w[2], pwt->w[2], 32, status);
5280 FMAXMIN_A(min, max, pwx->w[3], pws->w[3], pwt->w[3], 32, status);
5281 } else if (df == DF_DOUBLE) {
5282 FMAXMIN_A(min, max, pwx->d[0], pws->d[0], pwt->d[0], 64, status);
5283 FMAXMIN_A(min, max, pwx->d[1], pws->d[1], pwt->d[1], 64, status);
5284 } else {
5285 assert(0);
5286 }
5287
5288 check_msacsr_cause(env, GETPC());
5289
5290 msa_move_v(pwd, pwx);
5291 }
5292
5293 void helper_msa_fmax_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
5294 uint32_t ws, uint32_t wt)
5295 {
5296 float_status *status = &env->active_tc.msa_fp_status;
5297 wr_t wx, *pwx = &wx;
5298 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
5299 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
5300 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
5301
5302 clear_msacsr_cause(env);
5303
5304 if (df == DF_WORD) {
5305
5306 if (NUMBER_QNAN_PAIR(pws->w[0], pwt->w[0], 32, status)) {
5307 MSA_FLOAT_MAXOP(pwx->w[0], max, pws->w[0], pws->w[0], 32);
5308 } else if (NUMBER_QNAN_PAIR(pwt->w[0], pws->w[0], 32, status)) {
5309 MSA_FLOAT_MAXOP(pwx->w[0], max, pwt->w[0], pwt->w[0], 32);
5310 } else {
5311 MSA_FLOAT_MAXOP(pwx->w[0], max, pws->w[0], pwt->w[0], 32);
5312 }
5313
5314 if (NUMBER_QNAN_PAIR(pws->w[1], pwt->w[1], 32, status)) {
5315 MSA_FLOAT_MAXOP(pwx->w[1], max, pws->w[1], pws->w[1], 32);
5316 } else if (NUMBER_QNAN_PAIR(pwt->w[1], pws->w[1], 32, status)) {
5317 MSA_FLOAT_MAXOP(pwx->w[1], max, pwt->w[1], pwt->w[1], 32);
5318 } else {
5319 MSA_FLOAT_MAXOP(pwx->w[1], max, pws->w[1], pwt->w[1], 32);
5320 }
5321
5322 if (NUMBER_QNAN_PAIR(pws->w[2], pwt->w[2], 32, status)) {
5323 MSA_FLOAT_MAXOP(pwx->w[2], max, pws->w[2], pws->w[2], 32);
5324 } else if (NUMBER_QNAN_PAIR(pwt->w[2], pws->w[2], 32, status)) {
5325 MSA_FLOAT_MAXOP(pwx->w[2], max, pwt->w[2], pwt->w[2], 32);
5326 } else {
5327 MSA_FLOAT_MAXOP(pwx->w[2], max, pws->w[2], pwt->w[2], 32);
5328 }
5329
5330 if (NUMBER_QNAN_PAIR(pws->w[3], pwt->w[3], 32, status)) {
5331 MSA_FLOAT_MAXOP(pwx->w[3], max, pws->w[3], pws->w[3], 32);
5332 } else if (NUMBER_QNAN_PAIR(pwt->w[3], pws->w[3], 32, status)) {
5333 MSA_FLOAT_MAXOP(pwx->w[3], max, pwt->w[3], pwt->w[3], 32);
5334 } else {
5335 MSA_FLOAT_MAXOP(pwx->w[3], max, pws->w[3], pwt->w[3], 32);
5336 }
5337
5338 } else if (df == DF_DOUBLE) {
5339
5340 if (NUMBER_QNAN_PAIR(pws->d[0], pwt->d[0], 64, status)) {
5341 MSA_FLOAT_MAXOP(pwx->d[0], max, pws->d[0], pws->d[0], 64);
5342 } else if (NUMBER_QNAN_PAIR(pwt->d[0], pws->d[0], 64, status)) {
5343 MSA_FLOAT_MAXOP(pwx->d[0], max, pwt->d[0], pwt->d[0], 64);
5344 } else {
5345 MSA_FLOAT_MAXOP(pwx->d[0], max, pws->d[0], pwt->d[0], 64);
5346 }
5347
5348 if (NUMBER_QNAN_PAIR(pws->d[1], pwt->d[1], 64, status)) {
5349 MSA_FLOAT_MAXOP(pwx->d[1], max, pws->d[1], pws->d[1], 64);
5350 } else if (NUMBER_QNAN_PAIR(pwt->d[1], pws->d[1], 64, status)) {
5351 MSA_FLOAT_MAXOP(pwx->d[1], max, pwt->d[1], pwt->d[1], 64);
5352 } else {
5353 MSA_FLOAT_MAXOP(pwx->d[1], max, pws->d[1], pwt->d[1], 64);
5354 }
5355
5356 } else {
5357
5358 assert(0);
5359
5360 }
5361
5362 check_msacsr_cause(env, GETPC());
5363
5364 msa_move_v(pwd, pwx);
5365 }
5366
5367 void helper_msa_fmax_a_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
5368 uint32_t ws, uint32_t wt)
5369 {
5370 float_status *status = &env->active_tc.msa_fp_status;
5371 wr_t wx, *pwx = &wx;
5372 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
5373 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
5374 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
5375
5376 clear_msacsr_cause(env);
5377
5378 if (df == DF_WORD) {
5379 FMAXMIN_A(max, min, pwx->w[0], pws->w[0], pwt->w[0], 32, status);
5380 FMAXMIN_A(max, min, pwx->w[1], pws->w[1], pwt->w[1], 32, status);
5381 FMAXMIN_A(max, min, pwx->w[2], pws->w[2], pwt->w[2], 32, status);
5382 FMAXMIN_A(max, min, pwx->w[3], pws->w[3], pwt->w[3], 32, status);
5383 } else if (df == DF_DOUBLE) {
5384 FMAXMIN_A(max, min, pwx->d[0], pws->d[0], pwt->d[0], 64, status);
5385 FMAXMIN_A(max, min, pwx->d[1], pws->d[1], pwt->d[1], 64, status);
5386 } else {
5387 assert(0);
5388 }
5389
5390 check_msacsr_cause(env, GETPC());
5391
5392 msa_move_v(pwd, pwx);
5393 }
5394
5395 void helper_msa_fclass_df(CPUMIPSState *env, uint32_t df,
5396 uint32_t wd, uint32_t ws)
5397 {
5398 float_status *status = &env->active_tc.msa_fp_status;
5399
5400 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
5401 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
5402 if (df == DF_WORD) {
5403 pwd->w[0] = float_class_s(pws->w[0], status);
5404 pwd->w[1] = float_class_s(pws->w[1], status);
5405 pwd->w[2] = float_class_s(pws->w[2], status);
5406 pwd->w[3] = float_class_s(pws->w[3], status);
5407 } else if (df == DF_DOUBLE) {
5408 pwd->d[0] = float_class_d(pws->d[0], status);
5409 pwd->d[1] = float_class_d(pws->d[1], status);
5410 } else {
5411 assert(0);
5412 }
5413 }
5414
5415 #define MSA_FLOAT_UNOP0(DEST, OP, ARG, BITS) \
5416 do { \
5417 float_status *status = &env->active_tc.msa_fp_status; \
5418 int c; \
5419 \
5420 set_float_exception_flags(0, status); \
5421 DEST = float ## BITS ## _ ## OP(ARG, status); \
5422 c = update_msacsr(env, CLEAR_FS_UNDERFLOW, 0); \
5423 \
5424 if (get_enabled_exceptions(env, c)) { \
5425 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
5426 } else if (float ## BITS ## _is_any_nan(ARG)) { \
5427 DEST = 0; \
5428 } \
5429 } while (0)
5430
5431 void helper_msa_ftrunc_s_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
5432 uint32_t ws)
5433 {
5434 wr_t wx, *pwx = &wx;
5435 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
5436 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
5437 uint32_t i;
5438
5439 clear_msacsr_cause(env);
5440
5441 switch (df) {
5442 case DF_WORD:
5443 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
5444 MSA_FLOAT_UNOP0(pwx->w[i], to_int32_round_to_zero, pws->w[i], 32);
5445 }
5446 break;
5447 case DF_DOUBLE:
5448 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
5449 MSA_FLOAT_UNOP0(pwx->d[i], to_int64_round_to_zero, pws->d[i], 64);
5450 }
5451 break;
5452 default:
5453 assert(0);
5454 }
5455
5456 check_msacsr_cause(env, GETPC());
5457
5458 msa_move_v(pwd, pwx);
5459 }
5460
5461 void helper_msa_ftrunc_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
5462 uint32_t ws)
5463 {
5464 wr_t wx, *pwx = &wx;
5465 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
5466 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
5467 uint32_t i;
5468
5469 clear_msacsr_cause(env);
5470
5471 switch (df) {
5472 case DF_WORD:
5473 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
5474 MSA_FLOAT_UNOP0(pwx->w[i], to_uint32_round_to_zero, pws->w[i], 32);
5475 }
5476 break;
5477 case DF_DOUBLE:
5478 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
5479 MSA_FLOAT_UNOP0(pwx->d[i], to_uint64_round_to_zero, pws->d[i], 64);
5480 }
5481 break;
5482 default:
5483 assert(0);
5484 }
5485
5486 check_msacsr_cause(env, GETPC());
5487
5488 msa_move_v(pwd, pwx);
5489 }
5490
5491 void helper_msa_fsqrt_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
5492 uint32_t ws)
5493 {
5494 wr_t wx, *pwx = &wx;
5495 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
5496 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
5497 uint32_t i;
5498
5499 clear_msacsr_cause(env);
5500
5501 switch (df) {
5502 case DF_WORD:
5503 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
5504 MSA_FLOAT_UNOP(pwx->w[i], sqrt, pws->w[i], 32);
5505 }
5506 break;
5507 case DF_DOUBLE:
5508 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
5509 MSA_FLOAT_UNOP(pwx->d[i], sqrt, pws->d[i], 64);
5510 }
5511 break;
5512 default:
5513 assert(0);
5514 }
5515
5516 check_msacsr_cause(env, GETPC());
5517
5518 msa_move_v(pwd, pwx);
5519 }
5520
5521 #define MSA_FLOAT_RECIPROCAL(DEST, ARG, BITS) \
5522 do { \
5523 float_status *status = &env->active_tc.msa_fp_status; \
5524 int c; \
5525 \
5526 set_float_exception_flags(0, status); \
5527 DEST = float ## BITS ## _ ## div(FLOAT_ONE ## BITS, ARG, status); \
5528 c = update_msacsr(env, float ## BITS ## _is_infinity(ARG) || \
5529 float ## BITS ## _is_quiet_nan(DEST, status) ? \
5530 0 : RECIPROCAL_INEXACT, \
5531 IS_DENORMAL(DEST, BITS)); \
5532 \
5533 if (get_enabled_exceptions(env, c)) { \
5534 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
5535 } \
5536 } while (0)
5537
5538 void helper_msa_frsqrt_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
5539 uint32_t ws)
5540 {
5541 wr_t wx, *pwx = &wx;
5542 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
5543 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
5544 uint32_t i;
5545
5546 clear_msacsr_cause(env);
5547
5548 switch (df) {
5549 case DF_WORD:
5550 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
5551 MSA_FLOAT_RECIPROCAL(pwx->w[i], float32_sqrt(pws->w[i],
5552 &env->active_tc.msa_fp_status), 32);
5553 }
5554 break;
5555 case DF_DOUBLE:
5556 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
5557 MSA_FLOAT_RECIPROCAL(pwx->d[i], float64_sqrt(pws->d[i],
5558 &env->active_tc.msa_fp_status), 64);
5559 }
5560 break;
5561 default:
5562 assert(0);
5563 }
5564
5565 check_msacsr_cause(env, GETPC());
5566
5567 msa_move_v(pwd, pwx);
5568 }
5569
5570 void helper_msa_frcp_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
5571 uint32_t ws)
5572 {
5573 wr_t wx, *pwx = &wx;
5574 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
5575 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
5576 uint32_t i;
5577
5578 clear_msacsr_cause(env);
5579
5580 switch (df) {
5581 case DF_WORD:
5582 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
5583 MSA_FLOAT_RECIPROCAL(pwx->w[i], pws->w[i], 32);
5584 }
5585 break;
5586 case DF_DOUBLE:
5587 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
5588 MSA_FLOAT_RECIPROCAL(pwx->d[i], pws->d[i], 64);
5589 }
5590 break;
5591 default:
5592 assert(0);
5593 }
5594
5595 check_msacsr_cause(env, GETPC());
5596
5597 msa_move_v(pwd, pwx);
5598 }
5599
5600 void helper_msa_frint_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
5601 uint32_t ws)
5602 {
5603 wr_t wx, *pwx = &wx;
5604 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
5605 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
5606 uint32_t i;
5607
5608 clear_msacsr_cause(env);
5609
5610 switch (df) {
5611 case DF_WORD:
5612 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
5613 MSA_FLOAT_UNOP(pwx->w[i], round_to_int, pws->w[i], 32);
5614 }
5615 break;
5616 case DF_DOUBLE:
5617 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
5618 MSA_FLOAT_UNOP(pwx->d[i], round_to_int, pws->d[i], 64);
5619 }
5620 break;
5621 default:
5622 assert(0);
5623 }
5624
5625 check_msacsr_cause(env, GETPC());
5626
5627 msa_move_v(pwd, pwx);
5628 }
5629
5630 #define MSA_FLOAT_LOGB(DEST, ARG, BITS) \
5631 do { \
5632 float_status *status = &env->active_tc.msa_fp_status; \
5633 int c; \
5634 \
5635 set_float_exception_flags(0, status); \
5636 set_float_rounding_mode(float_round_down, status); \
5637 DEST = float ## BITS ## _ ## log2(ARG, status); \
5638 DEST = float ## BITS ## _ ## round_to_int(DEST, status); \
5639 set_float_rounding_mode(ieee_rm[(env->active_tc.msacsr & \
5640 MSACSR_RM_MASK) >> MSACSR_RM], \
5641 status); \
5642 \
5643 set_float_exception_flags(get_float_exception_flags(status) & \
5644 (~float_flag_inexact), \
5645 status); \
5646 \
5647 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
5648 \
5649 if (get_enabled_exceptions(env, c)) { \
5650 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
5651 } \
5652 } while (0)
5653
5654 void helper_msa_flog2_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
5655 uint32_t ws)
5656 {
5657 wr_t wx, *pwx = &wx;
5658 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
5659 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
5660 uint32_t i;
5661
5662 clear_msacsr_cause(env);
5663
5664 switch (df) {
5665 case DF_WORD:
5666 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
5667 MSA_FLOAT_LOGB(pwx->w[i], pws->w[i], 32);
5668 }
5669 break;
5670 case DF_DOUBLE:
5671 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
5672 MSA_FLOAT_LOGB(pwx->d[i], pws->d[i], 64);
5673 }
5674 break;
5675 default:
5676 assert(0);
5677 }
5678
5679 check_msacsr_cause(env, GETPC());
5680
5681 msa_move_v(pwd, pwx);
5682 }
5683
5684 void helper_msa_fexupl_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
5685 uint32_t ws)
5686 {
5687 wr_t wx, *pwx = &wx;
5688 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
5689 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
5690 uint32_t i;
5691
5692 clear_msacsr_cause(env);
5693
5694 switch (df) {
5695 case DF_WORD:
5696 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
5697 /*
5698 * Half precision floats come in two formats: standard
5699 * IEEE and "ARM" format. The latter gains extra exponent
5700 * range by omitting the NaN/Inf encodings.
5701 */
5702 flag ieee = 1;
5703
5704 MSA_FLOAT_BINOP(pwx->w[i], from_float16, Lh(pws, i), ieee, 32);
5705 }
5706 break;
5707 case DF_DOUBLE:
5708 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
5709 MSA_FLOAT_UNOP(pwx->d[i], from_float32, Lw(pws, i), 64);
5710 }
5711 break;
5712 default:
5713 assert(0);
5714 }
5715
5716 check_msacsr_cause(env, GETPC());
5717 msa_move_v(pwd, pwx);
5718 }
5719
5720 void helper_msa_fexupr_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
5721 uint32_t ws)
5722 {
5723 wr_t wx, *pwx = &wx;
5724 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
5725 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
5726 uint32_t i;
5727
5728 clear_msacsr_cause(env);
5729
5730 switch (df) {
5731 case DF_WORD:
5732 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
5733 /*
5734 * Half precision floats come in two formats: standard
5735 * IEEE and "ARM" format. The latter gains extra exponent
5736 * range by omitting the NaN/Inf encodings.
5737 */
5738 flag ieee = 1;
5739
5740 MSA_FLOAT_BINOP(pwx->w[i], from_float16, Rh(pws, i), ieee, 32);
5741 }
5742 break;
5743 case DF_DOUBLE:
5744 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
5745 MSA_FLOAT_UNOP(pwx->d[i], from_float32, Rw(pws, i), 64);
5746 }
5747 break;
5748 default:
5749 assert(0);
5750 }
5751
5752 check_msacsr_cause(env, GETPC());
5753 msa_move_v(pwd, pwx);
5754 }
5755
5756 void helper_msa_ffql_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
5757 uint32_t ws)
5758 {
5759 wr_t wx, *pwx = &wx;
5760 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
5761 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
5762 uint32_t i;
5763
5764 switch (df) {
5765 case DF_WORD:
5766 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
5767 MSA_FLOAT_UNOP(pwx->w[i], from_q16, Lh(pws, i), 32);
5768 }
5769 break;
5770 case DF_DOUBLE:
5771 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
5772 MSA_FLOAT_UNOP(pwx->d[i], from_q32, Lw(pws, i), 64);
5773 }
5774 break;
5775 default:
5776 assert(0);
5777 }
5778
5779 msa_move_v(pwd, pwx);
5780 }
5781
5782 void helper_msa_ffqr_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
5783 uint32_t ws)
5784 {
5785 wr_t wx, *pwx = &wx;
5786 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
5787 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
5788 uint32_t i;
5789
5790 switch (df) {
5791 case DF_WORD:
5792 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
5793 MSA_FLOAT_UNOP(pwx->w[i], from_q16, Rh(pws, i), 32);
5794 }
5795 break;
5796 case DF_DOUBLE:
5797 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
5798 MSA_FLOAT_UNOP(pwx->d[i], from_q32, Rw(pws, i), 64);
5799 }
5800 break;
5801 default:
5802 assert(0);
5803 }
5804
5805 msa_move_v(pwd, pwx);
5806 }
5807
5808 void helper_msa_ftint_s_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
5809 uint32_t ws)
5810 {
5811 wr_t wx, *pwx = &wx;
5812 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
5813 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
5814 uint32_t i;
5815
5816 clear_msacsr_cause(env);
5817
5818 switch (df) {
5819 case DF_WORD:
5820 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
5821 MSA_FLOAT_UNOP0(pwx->w[i], to_int32, pws->w[i], 32);
5822 }
5823 break;
5824 case DF_DOUBLE:
5825 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
5826 MSA_FLOAT_UNOP0(pwx->d[i], to_int64, pws->d[i], 64);
5827 }
5828 break;
5829 default:
5830 assert(0);
5831 }
5832
5833 check_msacsr_cause(env, GETPC());
5834
5835 msa_move_v(pwd, pwx);
5836 }
5837
5838 void helper_msa_ftint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
5839 uint32_t ws)
5840 {
5841 wr_t wx, *pwx = &wx;
5842 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
5843 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
5844 uint32_t i;
5845
5846 clear_msacsr_cause(env);
5847
5848 switch (df) {
5849 case DF_WORD:
5850 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
5851 MSA_FLOAT_UNOP0(pwx->w[i], to_uint32, pws->w[i], 32);
5852 }
5853 break;
5854 case DF_DOUBLE:
5855 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
5856 MSA_FLOAT_UNOP0(pwx->d[i], to_uint64, pws->d[i], 64);
5857 }
5858 break;
5859 default:
5860 assert(0);
5861 }
5862
5863 check_msacsr_cause(env, GETPC());
5864
5865 msa_move_v(pwd, pwx);
5866 }
5867
5868 #define float32_from_int32 int32_to_float32
5869 #define float32_from_uint32 uint32_to_float32
5870
5871 #define float64_from_int64 int64_to_float64
5872 #define float64_from_uint64 uint64_to_float64
5873
5874 void helper_msa_ffint_s_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
5875 uint32_t ws)
5876 {
5877 wr_t wx, *pwx = &wx;
5878 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
5879 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
5880 uint32_t i;
5881
5882 clear_msacsr_cause(env);
5883
5884 switch (df) {
5885 case DF_WORD:
5886 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
5887 MSA_FLOAT_UNOP(pwx->w[i], from_int32, pws->w[i], 32);
5888 }
5889 break;
5890 case DF_DOUBLE:
5891 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
5892 MSA_FLOAT_UNOP(pwx->d[i], from_int64, pws->d[i], 64);
5893 }
5894 break;
5895 default:
5896 assert(0);
5897 }
5898
5899 check_msacsr_cause(env, GETPC());
5900
5901 msa_move_v(pwd, pwx);
5902 }
5903
5904 void helper_msa_ffint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
5905 uint32_t ws)
5906 {
5907 wr_t wx, *pwx = &wx;
5908 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
5909 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
5910 uint32_t i;
5911
5912 clear_msacsr_cause(env);
5913
5914 switch (df) {
5915 case DF_WORD:
5916 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
5917 MSA_FLOAT_UNOP(pwx->w[i], from_uint32, pws->w[i], 32);
5918 }
5919 break;
5920 case DF_DOUBLE:
5921 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
5922 MSA_FLOAT_UNOP(pwx->d[i], from_uint64, pws->d[i], 64);
5923 }
5924 break;
5925 default:
5926 assert(0);
5927 }
5928
5929 check_msacsr_cause(env, GETPC());
5930
5931 msa_move_v(pwd, pwx);
5932 }
AR7 emulation for QEMU