4 * Copyright (c) 2016-2020 Michael Rolnik
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
21 #include "qemu/osdep.h"
23 #include "hw/core/tcg-cpu-ops.h"
24 #include "exec/exec-all.h"
25 #include "exec/address-spaces.h"
26 #include "exec/helper-proto.h"
28 bool avr_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
31 CPUClass
*cc
= CPU_GET_CLASS(cs
);
32 AVRCPU
*cpu
= AVR_CPU(cs
);
33 CPUAVRState
*env
= &cpu
->env
;
35 if (interrupt_request
& CPU_INTERRUPT_RESET
) {
36 if (cpu_interrupts_enabled(env
)) {
37 cs
->exception_index
= EXCP_RESET
;
38 cc
->tcg_ops
->do_interrupt(cs
);
40 cs
->interrupt_request
&= ~CPU_INTERRUPT_RESET
;
45 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
46 if (cpu_interrupts_enabled(env
) && env
->intsrc
!= 0) {
47 int index
= ctz32(env
->intsrc
);
48 cs
->exception_index
= EXCP_INT(index
);
49 cc
->tcg_ops
->do_interrupt(cs
);
51 env
->intsrc
&= env
->intsrc
- 1; /* clear the interrupt */
52 cs
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
60 void avr_cpu_do_interrupt(CPUState
*cs
)
62 AVRCPU
*cpu
= AVR_CPU(cs
);
63 CPUAVRState
*env
= &cpu
->env
;
65 uint32_t ret
= env
->pc_w
;
67 int size
= avr_feature(env
, AVR_FEATURE_JMP_CALL
) ? 2 : 1;
70 if (cs
->exception_index
== EXCP_RESET
) {
72 } else if (env
->intsrc
!= 0) {
73 vector
= ctz32(env
->intsrc
) + 1;
76 if (avr_feature(env
, AVR_FEATURE_3_BYTE_PC
)) {
77 cpu_stb_data(env
, env
->sp
--, (ret
& 0x0000ff));
78 cpu_stb_data(env
, env
->sp
--, (ret
& 0x00ff00) >> 8);
79 cpu_stb_data(env
, env
->sp
--, (ret
& 0xff0000) >> 16);
80 } else if (avr_feature(env
, AVR_FEATURE_2_BYTE_PC
)) {
81 cpu_stb_data(env
, env
->sp
--, (ret
& 0x0000ff));
82 cpu_stb_data(env
, env
->sp
--, (ret
& 0x00ff00) >> 8);
84 cpu_stb_data(env
, env
->sp
--, (ret
& 0x0000ff));
87 env
->pc_w
= base
+ vector
* size
;
88 env
->sregI
= 0; /* clear Global Interrupt Flag */
90 cs
->exception_index
= -1;
93 int avr_cpu_memory_rw_debug(CPUState
*cs
, vaddr addr
, uint8_t *buf
,
94 int len
, bool is_write
)
96 return cpu_memory_rw_debug(cs
, addr
, buf
, len
, is_write
);
99 hwaddr
avr_cpu_get_phys_page_debug(CPUState
*cs
, vaddr addr
)
101 return addr
; /* I assume 1:1 address correspondance */
104 bool avr_cpu_tlb_fill(CPUState
*cs
, vaddr address
, int size
,
105 MMUAccessType access_type
, int mmu_idx
,
106 bool probe
, uintptr_t retaddr
)
109 MemTxAttrs attrs
= {};
112 address
&= TARGET_PAGE_MASK
;
114 if (mmu_idx
== MMU_CODE_IDX
) {
115 /* access to code in flash */
116 paddr
= OFFSET_CODE
+ address
;
117 prot
= PAGE_READ
| PAGE_EXEC
;
118 if (paddr
+ TARGET_PAGE_SIZE
> OFFSET_DATA
) {
119 error_report("execution left flash memory");
122 } else if (address
< NUMBER_OF_CPU_REGISTERS
+ NUMBER_OF_IO_REGISTERS
) {
124 * access to CPU registers, exit and rebuilt this TB to use full access
125 * incase it touches specially handled registers like SREG or SP
127 AVRCPU
*cpu
= AVR_CPU(cs
);
128 CPUAVRState
*env
= &cpu
->env
;
130 cpu_loop_exit_restore(cs
, retaddr
);
132 /* access to memory. nothing special */
133 paddr
= OFFSET_DATA
+ address
;
134 prot
= PAGE_READ
| PAGE_WRITE
;
137 tlb_set_page_with_attrs(cs
, address
, paddr
, attrs
, prot
,
138 mmu_idx
, TARGET_PAGE_SIZE
);
147 void helper_sleep(CPUAVRState
*env
)
149 CPUState
*cs
= env_cpu(env
);
151 cs
->exception_index
= EXCP_HLT
;
155 void helper_unsupported(CPUAVRState
*env
)
157 CPUState
*cs
= env_cpu(env
);
160 * I count not find what happens on the real platform, so
161 * it's EXCP_DEBUG for meanwhile
163 cs
->exception_index
= EXCP_DEBUG
;
164 if (qemu_loglevel_mask(LOG_UNIMP
)) {
165 qemu_log("UNSUPPORTED\n");
166 cpu_dump_state(cs
, stderr
, 0);
171 void helper_debug(CPUAVRState
*env
)
173 CPUState
*cs
= env_cpu(env
);
175 cs
->exception_index
= EXCP_DEBUG
;
179 void helper_break(CPUAVRState
*env
)
181 CPUState
*cs
= env_cpu(env
);
183 cs
->exception_index
= EXCP_DEBUG
;
187 void helper_wdr(CPUAVRState
*env
)
189 CPUState
*cs
= env_cpu(env
);
191 /* WD is not implemented yet, placeholder */
192 cs
->exception_index
= EXCP_DEBUG
;
197 * This function implements IN instruction
199 * It does the following
200 * a. if an IO register belongs to CPU, its value is read and returned
201 * b. otherwise io address is translated to mem address and physical memory
203 * c. it caches the value for sake of SBI, SBIC, SBIS & CBI implementation
206 target_ulong
helper_inb(CPUAVRState
*env
, uint32_t port
)
208 target_ulong data
= 0;
211 case 0x38: /* RAMPD */
212 data
= 0xff & (env
->rampD
>> 16);
214 case 0x39: /* RAMPX */
215 data
= 0xff & (env
->rampX
>> 16);
217 case 0x3a: /* RAMPY */
218 data
= 0xff & (env
->rampY
>> 16);
220 case 0x3b: /* RAMPZ */
221 data
= 0xff & (env
->rampZ
>> 16);
223 case 0x3c: /* EIND */
224 data
= 0xff & (env
->eind
>> 16);
227 data
= env
->sp
& 0x00ff;
232 case 0x3f: /* SREG */
233 data
= cpu_get_sreg(env
);
236 /* not a special register, pass to normal memory access */
237 data
= address_space_ldub(&address_space_memory
,
238 OFFSET_IO_REGISTERS
+ port
,
239 MEMTXATTRS_UNSPECIFIED
, NULL
);
246 * This function implements OUT instruction
248 * It does the following
249 * a. if an IO register belongs to CPU, its value is written into the register
250 * b. otherwise io address is translated to mem address and physical memory
252 * c. it caches the value for sake of SBI, SBIC, SBIS & CBI implementation
255 void helper_outb(CPUAVRState
*env
, uint32_t port
, uint32_t data
)
260 case 0x38: /* RAMPD */
261 if (avr_feature(env
, AVR_FEATURE_RAMPD
)) {
262 env
->rampD
= (data
& 0xff) << 16;
265 case 0x39: /* RAMPX */
266 if (avr_feature(env
, AVR_FEATURE_RAMPX
)) {
267 env
->rampX
= (data
& 0xff) << 16;
270 case 0x3a: /* RAMPY */
271 if (avr_feature(env
, AVR_FEATURE_RAMPY
)) {
272 env
->rampY
= (data
& 0xff) << 16;
275 case 0x3b: /* RAMPZ */
276 if (avr_feature(env
, AVR_FEATURE_RAMPZ
)) {
277 env
->rampZ
= (data
& 0xff) << 16;
280 case 0x3c: /* EIDN */
281 env
->eind
= (data
& 0xff) << 16;
284 env
->sp
= (env
->sp
& 0xff00) | (data
);
287 if (avr_feature(env
, AVR_FEATURE_2_BYTE_SP
)) {
288 env
->sp
= (env
->sp
& 0x00ff) | (data
<< 8);
291 case 0x3f: /* SREG */
292 cpu_set_sreg(env
, data
);
295 /* not a special register, pass to normal memory access */
296 address_space_stb(&address_space_memory
, OFFSET_IO_REGISTERS
+ port
,
297 data
, MEMTXATTRS_UNSPECIFIED
, NULL
);
302 * this function implements LD instruction when there is a posibility to read
303 * from a CPU register
305 target_ulong
helper_fullrd(CPUAVRState
*env
, uint32_t addr
)
309 env
->fullacc
= false;
311 if (addr
< NUMBER_OF_CPU_REGISTERS
) {
314 } else if (addr
< NUMBER_OF_CPU_REGISTERS
+ NUMBER_OF_IO_REGISTERS
) {
316 data
= helper_inb(env
, addr
- NUMBER_OF_CPU_REGISTERS
);
319 data
= address_space_ldub(&address_space_memory
, OFFSET_DATA
+ addr
,
320 MEMTXATTRS_UNSPECIFIED
, NULL
);
326 * this function implements ST instruction when there is a posibility to write
327 * into a CPU register
329 void helper_fullwr(CPUAVRState
*env
, uint32_t data
, uint32_t addr
)
331 env
->fullacc
= false;
333 /* Following logic assumes this: */
334 assert(OFFSET_CPU_REGISTERS
== OFFSET_DATA
);
335 assert(OFFSET_IO_REGISTERS
== OFFSET_CPU_REGISTERS
+
336 NUMBER_OF_CPU_REGISTERS
);
338 if (addr
< NUMBER_OF_CPU_REGISTERS
) {
341 } else if (addr
< NUMBER_OF_CPU_REGISTERS
+ NUMBER_OF_IO_REGISTERS
) {
343 helper_outb(env
, addr
- NUMBER_OF_CPU_REGISTERS
, data
);
346 address_space_stb(&address_space_memory
, OFFSET_DATA
+ addr
, data
,
347 MEMTXATTRS_UNSPECIFIED
, NULL
);