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fdc: add drive type option
[qemu/ar7.git] / hw / block / fdc.c
blobe89ce2d9a28fbe5fda1fd8d6e3db5b44ed756ed2
1 /*
2 * QEMU Floppy disk emulator (Intel 82078)
3 *
4 * Copyright (c) 2003, 2007 Jocelyn Mayer
5 * Copyright (c) 2008 Hervé Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * The controller is used in Sun4m systems in a slightly different
27 * way. There are changes in DOR register and DMA is not available.
28 */
29
30 #include "qemu/osdep.h"
31 #include "hw/hw.h"
32 #include "hw/block/fdc.h"
33 #include "qemu/error-report.h"
34 #include "qemu/timer.h"
35 #include "hw/isa/isa.h"
36 #include "hw/sysbus.h"
37 #include "sysemu/block-backend.h"
38 #include "sysemu/blockdev.h"
39 #include "sysemu/sysemu.h"
40 #include "qemu/log.h"
41
42 /********************************************************/
43 /* debug Floppy devices */
44 //#define DEBUG_FLOPPY
45
46 #ifdef DEBUG_FLOPPY
47 #define FLOPPY_DPRINTF(fmt, ...) \
48 do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0)
49 #else
50 #define FLOPPY_DPRINTF(fmt, ...)
51 #endif
52
53 /********************************************************/
54 /* Floppy drive emulation */
55
56 typedef enum FDriveRate {
57 FDRIVE_RATE_500K = 0x00, /* 500 Kbps */
58 FDRIVE_RATE_300K = 0x01, /* 300 Kbps */
59 FDRIVE_RATE_250K = 0x02, /* 250 Kbps */
60 FDRIVE_RATE_1M = 0x03, /* 1 Mbps */
61 } FDriveRate;
62
63 typedef struct FDFormat {
64 FloppyDriveType drive;
65 uint8_t last_sect;
66 uint8_t max_track;
67 uint8_t max_head;
68 FDriveRate rate;
69 } FDFormat;
70
71 static const FDFormat fd_formats[] = {
72 /* First entry is default format */
73 /* 1.44 MB 3"1/2 floppy disks */
74 { FLOPPY_DRIVE_TYPE_144, 18, 80, 1, FDRIVE_RATE_500K, },
75 { FLOPPY_DRIVE_TYPE_144, 20, 80, 1, FDRIVE_RATE_500K, },
76 { FLOPPY_DRIVE_TYPE_144, 21, 80, 1, FDRIVE_RATE_500K, },
77 { FLOPPY_DRIVE_TYPE_144, 21, 82, 1, FDRIVE_RATE_500K, },
78 { FLOPPY_DRIVE_TYPE_144, 21, 83, 1, FDRIVE_RATE_500K, },
79 { FLOPPY_DRIVE_TYPE_144, 22, 80, 1, FDRIVE_RATE_500K, },
80 { FLOPPY_DRIVE_TYPE_144, 23, 80, 1, FDRIVE_RATE_500K, },
81 { FLOPPY_DRIVE_TYPE_144, 24, 80, 1, FDRIVE_RATE_500K, },
82 /* 2.88 MB 3"1/2 floppy disks */
83 { FLOPPY_DRIVE_TYPE_288, 36, 80, 1, FDRIVE_RATE_1M, },
84 { FLOPPY_DRIVE_TYPE_288, 39, 80, 1, FDRIVE_RATE_1M, },
85 { FLOPPY_DRIVE_TYPE_288, 40, 80, 1, FDRIVE_RATE_1M, },
86 { FLOPPY_DRIVE_TYPE_288, 44, 80, 1, FDRIVE_RATE_1M, },
87 { FLOPPY_DRIVE_TYPE_288, 48, 80, 1, FDRIVE_RATE_1M, },
88 /* 720 kB 3"1/2 floppy disks */
89 { FLOPPY_DRIVE_TYPE_144, 9, 80, 1, FDRIVE_RATE_250K, },
90 { FLOPPY_DRIVE_TYPE_144, 10, 80, 1, FDRIVE_RATE_250K, },
91 { FLOPPY_DRIVE_TYPE_144, 10, 82, 1, FDRIVE_RATE_250K, },
92 { FLOPPY_DRIVE_TYPE_144, 10, 83, 1, FDRIVE_RATE_250K, },
93 { FLOPPY_DRIVE_TYPE_144, 13, 80, 1, FDRIVE_RATE_250K, },
94 { FLOPPY_DRIVE_TYPE_144, 14, 80, 1, FDRIVE_RATE_250K, },
95 /* 1.2 MB 5"1/4 floppy disks */
96 { FLOPPY_DRIVE_TYPE_120, 15, 80, 1, FDRIVE_RATE_500K, },
97 { FLOPPY_DRIVE_TYPE_120, 18, 80, 1, FDRIVE_RATE_500K, },
98 { FLOPPY_DRIVE_TYPE_120, 18, 82, 1, FDRIVE_RATE_500K, },
99 { FLOPPY_DRIVE_TYPE_120, 18, 83, 1, FDRIVE_RATE_500K, },
100 { FLOPPY_DRIVE_TYPE_120, 20, 80, 1, FDRIVE_RATE_500K, },
101 /* 720 kB 5"1/4 floppy disks */
102 { FLOPPY_DRIVE_TYPE_120, 9, 80, 1, FDRIVE_RATE_250K, },
103 { FLOPPY_DRIVE_TYPE_120, 11, 80, 1, FDRIVE_RATE_250K, },
104 /* 360 kB 5"1/4 floppy disks */
105 { FLOPPY_DRIVE_TYPE_120, 9, 40, 1, FDRIVE_RATE_300K, },
106 { FLOPPY_DRIVE_TYPE_120, 9, 40, 0, FDRIVE_RATE_300K, },
107 { FLOPPY_DRIVE_TYPE_120, 10, 41, 1, FDRIVE_RATE_300K, },
108 { FLOPPY_DRIVE_TYPE_120, 10, 42, 1, FDRIVE_RATE_300K, },
109 /* 320 kB 5"1/4 floppy disks */
110 { FLOPPY_DRIVE_TYPE_120, 8, 40, 1, FDRIVE_RATE_250K, },
111 { FLOPPY_DRIVE_TYPE_120, 8, 40, 0, FDRIVE_RATE_250K, },
112 /* 360 kB must match 5"1/4 better than 3"1/2... */
113 { FLOPPY_DRIVE_TYPE_144, 9, 80, 0, FDRIVE_RATE_250K, },
114 /* end */
115 { FLOPPY_DRIVE_TYPE_NONE, -1, -1, 0, 0, },
116 };
117
118 #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
119 #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
120
121 /* Will always be a fixed parameter for us */
122 #define FD_SECTOR_LEN 512
123 #define FD_SECTOR_SC 2 /* Sector size code */
124 #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
125
126 typedef struct FDCtrl FDCtrl;
127
128 /* Floppy disk drive emulation */
129 typedef enum FDiskFlags {
130 FDISK_DBL_SIDES = 0x01,
131 } FDiskFlags;
132
133 typedef struct FDrive {
134 FDCtrl *fdctrl;
135 BlockBackend *blk;
136 /* Drive status */
137 FloppyDriveType drive; /* CMOS drive type */
138 uint8_t perpendicular; /* 2.88 MB access mode */
139 /* Position */
140 uint8_t head;
141 uint8_t track;
142 uint8_t sect;
143 /* Media */
144 FloppyDriveType disk; /* Current disk type */
145 FDiskFlags flags;
146 uint8_t last_sect; /* Nb sector per track */
147 uint8_t max_track; /* Nb of tracks */
148 uint16_t bps; /* Bytes per sector */
149 uint8_t ro; /* Is read-only */
150 uint8_t media_changed; /* Is media changed */
151 uint8_t media_rate; /* Data rate of medium */
152
153 bool media_inserted; /* Is there a medium in the tray */
154 bool media_validated; /* Have we validated the media? */
155 } FDrive;
156
157
158 static FloppyDriveType get_fallback_drive_type(FDrive *drv);
159
160 static void fd_init(FDrive *drv)
161 {
162 /* Drive */
163 drv->perpendicular = 0;
164 /* Disk */
165 drv->disk = FLOPPY_DRIVE_TYPE_NONE;
166 drv->last_sect = 0;
167 drv->max_track = 0;
168 drv->ro = true;
169 drv->media_changed = 1;
170 }
171
172 #define NUM_SIDES(drv) ((drv)->flags & FDISK_DBL_SIDES ? 2 : 1)
173
174 static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect,
175 uint8_t last_sect, uint8_t num_sides)
176 {
177 return (((track * num_sides) + head) * last_sect) + sect - 1;
178 }
179
180 /* Returns current position, in sectors, for given drive */
181 static int fd_sector(FDrive *drv)
182 {
183 return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect,
184 NUM_SIDES(drv));
185 }
186
187 /* Seek to a new position:
188 * returns 0 if already on right track
189 * returns 1 if track changed
190 * returns 2 if track is invalid
191 * returns 3 if sector is invalid
192 * returns 4 if seek is disabled
193 */
194 static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect,
195 int enable_seek)
196 {
197 uint32_t sector;
198 int ret;
199
200 if (track > drv->max_track ||
201 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
202 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
203 head, track, sect, 1,
204 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
205 drv->max_track, drv->last_sect);
206 return 2;
207 }
208 if (sect > drv->last_sect) {
209 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
210 head, track, sect, 1,
211 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
212 drv->max_track, drv->last_sect);
213 return 3;
214 }
215 sector = fd_sector_calc(head, track, sect, drv->last_sect, NUM_SIDES(drv));
216 ret = 0;
217 if (sector != fd_sector(drv)) {
218 #if 0
219 if (!enable_seek) {
220 FLOPPY_DPRINTF("error: no implicit seek %d %02x %02x"
221 " (max=%d %02x %02x)\n",
222 head, track, sect, 1, drv->max_track,
223 drv->last_sect);
224 return 4;
225 }
226 #endif
227 drv->head = head;
228 if (drv->track != track) {
229 if (drv->media_inserted) {
230 drv->media_changed = 0;
231 }
232 ret = 1;
233 }
234 drv->track = track;
235 drv->sect = sect;
236 }
237
238 if (!drv->media_inserted) {
239 ret = 2;
240 }
241
242 return ret;
243 }
244
245 /* Set drive back to track 0 */
246 static void fd_recalibrate(FDrive *drv)
247 {
248 FLOPPY_DPRINTF("recalibrate\n");
249 fd_seek(drv, 0, 0, 1, 1);
250 }
251
252 /**
253 * Determine geometry based on inserted diskette.
254 * Will not operate on an empty drive.
255 *
256 * @return: 0 on success, -1 if the drive is empty.
257 */
258 static int pick_geometry(FDrive *drv)
259 {
260 BlockBackend *blk = drv->blk;
261 const FDFormat *parse;
262 uint64_t nb_sectors, size;
263 int i, first_match, match;
264
265 /* We can only pick a geometry if we have a diskette. */
266 if (!drv->media_inserted || drv->drive == FLOPPY_DRIVE_TYPE_NONE) {
267 return -1;
268 }
269
270 blk_get_geometry(blk, &nb_sectors);
271 match = -1;
272 first_match = -1;
273 for (i = 0; ; i++) {
274 parse = &fd_formats[i];
275 if (parse->drive == FLOPPY_DRIVE_TYPE_NONE) {
276 break;
277 }
278 if (drv->drive == parse->drive ||
279 drv->drive == FLOPPY_DRIVE_TYPE_AUTO) {
280 size = (parse->max_head + 1) * parse->max_track *
281 parse->last_sect;
282 if (nb_sectors == size) {
283 match = i;
284 break;
285 }
286 if (first_match == -1) {
287 first_match = i;
288 }
289 }
290 }
291 if (match == -1) {
292 if (first_match == -1) {
293 error_setg(&error_abort, "No candidate geometries present in table "
294 " for floppy drive type '%s'",
295 FloppyDriveType_lookup[drv->drive]);
296 } else {
297 match = first_match;
298 }
299 parse = &fd_formats[match];
300 }
301
302 if (parse->max_head == 0) {
303 drv->flags &= ~FDISK_DBL_SIDES;
304 } else {
305 drv->flags |= FDISK_DBL_SIDES;
306 }
307 drv->max_track = parse->max_track;
308 drv->last_sect = parse->last_sect;
309 drv->disk = parse->drive;
310 drv->media_rate = parse->rate;
311 return 0;
312 }
313
314 static void pick_drive_type(FDrive *drv)
315 {
316 if (drv->drive != FLOPPY_DRIVE_TYPE_AUTO) {
317 return;
318 }
319
320 if (pick_geometry(drv) == 0) {
321 drv->drive = drv->disk;
322 } else {
323 drv->drive = get_fallback_drive_type(drv);
324 }
325
326 g_assert(drv->drive != FLOPPY_DRIVE_TYPE_AUTO);
327 }
328
329 /* Revalidate a disk drive after a disk change */
330 static void fd_revalidate(FDrive *drv)
331 {
332 int rc;
333
334 FLOPPY_DPRINTF("revalidate\n");
335 if (drv->blk != NULL) {
336 drv->ro = blk_is_read_only(drv->blk);
337 if (!drv->media_inserted) {
338 FLOPPY_DPRINTF("No disk in drive\n");
339 drv->disk = FLOPPY_DRIVE_TYPE_NONE;
340 } else if (!drv->media_validated) {
341 rc = pick_geometry(drv);
342 if (rc) {
343 FLOPPY_DPRINTF("Could not validate floppy drive media");
344 } else {
345 drv->media_validated = true;
346 FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n",
347 (drv->flags & FDISK_DBL_SIDES) ? 2 : 1,
348 drv->max_track, drv->last_sect,
349 drv->ro ? "ro" : "rw");
350 }
351 }
352 } else {
353 FLOPPY_DPRINTF("No drive connected\n");
354 drv->last_sect = 0;
355 drv->max_track = 0;
356 drv->flags &= ~FDISK_DBL_SIDES;
357 drv->drive = FLOPPY_DRIVE_TYPE_NONE;
358 drv->disk = FLOPPY_DRIVE_TYPE_NONE;
359 }
360 }
361
362 /********************************************************/
363 /* Intel 82078 floppy disk controller emulation */
364
365 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq);
366 static void fdctrl_to_command_phase(FDCtrl *fdctrl);
367 static int fdctrl_transfer_handler (void *opaque, int nchan,
368 int dma_pos, int dma_len);
369 static void fdctrl_raise_irq(FDCtrl *fdctrl);
370 static FDrive *get_cur_drv(FDCtrl *fdctrl);
371
372 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl);
373 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl);
374 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl);
375 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value);
376 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl);
377 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value);
378 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl);
379 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value);
380 static uint32_t fdctrl_read_data(FDCtrl *fdctrl);
381 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value);
382 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl);
383 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value);
384
385 enum {
386 FD_DIR_WRITE = 0,
387 FD_DIR_READ = 1,
388 FD_DIR_SCANE = 2,
389 FD_DIR_SCANL = 3,
390 FD_DIR_SCANH = 4,
391 FD_DIR_VERIFY = 5,
392 };
393
394 enum {
395 FD_STATE_MULTI = 0x01, /* multi track flag */
396 FD_STATE_FORMAT = 0x02, /* format flag */
397 };
398
399 enum {
400 FD_REG_SRA = 0x00,
401 FD_REG_SRB = 0x01,
402 FD_REG_DOR = 0x02,
403 FD_REG_TDR = 0x03,
404 FD_REG_MSR = 0x04,
405 FD_REG_DSR = 0x04,
406 FD_REG_FIFO = 0x05,
407 FD_REG_DIR = 0x07,
408 FD_REG_CCR = 0x07,
409 };
410
411 enum {
412 FD_CMD_READ_TRACK = 0x02,
413 FD_CMD_SPECIFY = 0x03,
414 FD_CMD_SENSE_DRIVE_STATUS = 0x04,
415 FD_CMD_WRITE = 0x05,
416 FD_CMD_READ = 0x06,
417 FD_CMD_RECALIBRATE = 0x07,
418 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
419 FD_CMD_WRITE_DELETED = 0x09,
420 FD_CMD_READ_ID = 0x0a,
421 FD_CMD_READ_DELETED = 0x0c,
422 FD_CMD_FORMAT_TRACK = 0x0d,
423 FD_CMD_DUMPREG = 0x0e,
424 FD_CMD_SEEK = 0x0f,
425 FD_CMD_VERSION = 0x10,
426 FD_CMD_SCAN_EQUAL = 0x11,
427 FD_CMD_PERPENDICULAR_MODE = 0x12,
428 FD_CMD_CONFIGURE = 0x13,
429 FD_CMD_LOCK = 0x14,
430 FD_CMD_VERIFY = 0x16,
431 FD_CMD_POWERDOWN_MODE = 0x17,
432 FD_CMD_PART_ID = 0x18,
433 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
434 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
435 FD_CMD_SAVE = 0x2e,
436 FD_CMD_OPTION = 0x33,
437 FD_CMD_RESTORE = 0x4e,
438 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
439 FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
440 FD_CMD_FORMAT_AND_WRITE = 0xcd,
441 FD_CMD_RELATIVE_SEEK_IN = 0xcf,
442 };
443
444 enum {
445 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
446 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
447 FD_CONFIG_POLL = 0x10, /* Poll enabled */
448 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
449 FD_CONFIG_EIS = 0x40, /* No implied seeks */
450 };
451
452 enum {
453 FD_SR0_DS0 = 0x01,
454 FD_SR0_DS1 = 0x02,
455 FD_SR0_HEAD = 0x04,
456 FD_SR0_EQPMT = 0x10,
457 FD_SR0_SEEK = 0x20,
458 FD_SR0_ABNTERM = 0x40,
459 FD_SR0_INVCMD = 0x80,
460 FD_SR0_RDYCHG = 0xc0,
461 };
462
463 enum {
464 FD_SR1_MA = 0x01, /* Missing address mark */
465 FD_SR1_NW = 0x02, /* Not writable */
466 FD_SR1_EC = 0x80, /* End of cylinder */
467 };
468
469 enum {
470 FD_SR2_SNS = 0x04, /* Scan not satisfied */
471 FD_SR2_SEH = 0x08, /* Scan equal hit */
472 };
473
474 enum {
475 FD_SRA_DIR = 0x01,
476 FD_SRA_nWP = 0x02,
477 FD_SRA_nINDX = 0x04,
478 FD_SRA_HDSEL = 0x08,
479 FD_SRA_nTRK0 = 0x10,
480 FD_SRA_STEP = 0x20,
481 FD_SRA_nDRV2 = 0x40,
482 FD_SRA_INTPEND = 0x80,
483 };
484
485 enum {
486 FD_SRB_MTR0 = 0x01,
487 FD_SRB_MTR1 = 0x02,
488 FD_SRB_WGATE = 0x04,
489 FD_SRB_RDATA = 0x08,
490 FD_SRB_WDATA = 0x10,
491 FD_SRB_DR0 = 0x20,
492 };
493
494 enum {
495 #if MAX_FD == 4
496 FD_DOR_SELMASK = 0x03,
497 #else
498 FD_DOR_SELMASK = 0x01,
499 #endif
500 FD_DOR_nRESET = 0x04,
501 FD_DOR_DMAEN = 0x08,
502 FD_DOR_MOTEN0 = 0x10,
503 FD_DOR_MOTEN1 = 0x20,
504 FD_DOR_MOTEN2 = 0x40,
505 FD_DOR_MOTEN3 = 0x80,
506 };
507
508 enum {
509 #if MAX_FD == 4
510 FD_TDR_BOOTSEL = 0x0c,
511 #else
512 FD_TDR_BOOTSEL = 0x04,
513 #endif
514 };
515
516 enum {
517 FD_DSR_DRATEMASK= 0x03,
518 FD_DSR_PWRDOWN = 0x40,
519 FD_DSR_SWRESET = 0x80,
520 };
521
522 enum {
523 FD_MSR_DRV0BUSY = 0x01,
524 FD_MSR_DRV1BUSY = 0x02,
525 FD_MSR_DRV2BUSY = 0x04,
526 FD_MSR_DRV3BUSY = 0x08,
527 FD_MSR_CMDBUSY = 0x10,
528 FD_MSR_NONDMA = 0x20,
529 FD_MSR_DIO = 0x40,
530 FD_MSR_RQM = 0x80,
531 };
532
533 enum {
534 FD_DIR_DSKCHG = 0x80,
535 };
536
537 /*
538 * See chapter 5.0 "Controller phases" of the spec:
539 *
540 * Command phase:
541 * The host writes a command and its parameters into the FIFO. The command
542 * phase is completed when all parameters for the command have been supplied,
543 * and execution phase is entered.
544 *
545 * Execution phase:
546 * Data transfers, either DMA or non-DMA. For non-DMA transfers, the FIFO
547 * contains the payload now, otherwise it's unused. When all bytes of the
548 * required data have been transferred, the state is switched to either result
549 * phase (if the command produces status bytes) or directly back into the
550 * command phase for the next command.
551 *
552 * Result phase:
553 * The host reads out the FIFO, which contains one or more result bytes now.
554 */
555 enum {
556 /* Only for migration: reconstruct phase from registers like qemu 2.3 */
557 FD_PHASE_RECONSTRUCT = 0,
558
559 FD_PHASE_COMMAND = 1,
560 FD_PHASE_EXECUTION = 2,
561 FD_PHASE_RESULT = 3,
562 };
563
564 #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
565 #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
566
567 struct FDCtrl {
568 MemoryRegion iomem;
569 qemu_irq irq;
570 /* Controller state */
571 QEMUTimer *result_timer;
572 int dma_chann;
573 uint8_t phase;
574 /* Controller's identification */
575 uint8_t version;
576 /* HW */
577 uint8_t sra;
578 uint8_t srb;
579 uint8_t dor;
580 uint8_t dor_vmstate; /* only used as temp during vmstate */
581 uint8_t tdr;
582 uint8_t dsr;
583 uint8_t msr;
584 uint8_t cur_drv;
585 uint8_t status0;
586 uint8_t status1;
587 uint8_t status2;
588 /* Command FIFO */
589 uint8_t *fifo;
590 int32_t fifo_size;
591 uint32_t data_pos;
592 uint32_t data_len;
593 uint8_t data_state;
594 uint8_t data_dir;
595 uint8_t eot; /* last wanted sector */
596 /* States kept only to be returned back */
597 /* precompensation */
598 uint8_t precomp_trk;
599 uint8_t config;
600 uint8_t lock;
601 /* Power down config (also with status regB access mode */
602 uint8_t pwrd;
603 /* Floppy drives */
604 uint8_t num_floppies;
605 FDrive drives[MAX_FD];
606 int reset_sensei;
607 uint32_t check_media_rate;
608 FloppyDriveType fallback; /* type=auto failure fallback */
609 /* Timers state */
610 uint8_t timer0;
611 uint8_t timer1;
612 };
613
614 static FloppyDriveType get_fallback_drive_type(FDrive *drv)
615 {
616 return drv->fdctrl->fallback;
617 }
618
619 #define TYPE_SYSBUS_FDC "base-sysbus-fdc"
620 #define SYSBUS_FDC(obj) OBJECT_CHECK(FDCtrlSysBus, (obj), TYPE_SYSBUS_FDC)
621
622 typedef struct FDCtrlSysBus {
623 /*< private >*/
624 SysBusDevice parent_obj;
625 /*< public >*/
626
627 struct FDCtrl state;
628 } FDCtrlSysBus;
629
630 #define ISA_FDC(obj) OBJECT_CHECK(FDCtrlISABus, (obj), TYPE_ISA_FDC)
631
632 typedef struct FDCtrlISABus {
633 ISADevice parent_obj;
634
635 uint32_t iobase;
636 uint32_t irq;
637 uint32_t dma;
638 struct FDCtrl state;
639 int32_t bootindexA;
640 int32_t bootindexB;
641 } FDCtrlISABus;
642
643 static uint32_t fdctrl_read (void *opaque, uint32_t reg)
644 {
645 FDCtrl *fdctrl = opaque;
646 uint32_t retval;
647
648 reg &= 7;
649 switch (reg) {
650 case FD_REG_SRA:
651 retval = fdctrl_read_statusA(fdctrl);
652 break;
653 case FD_REG_SRB:
654 retval = fdctrl_read_statusB(fdctrl);
655 break;
656 case FD_REG_DOR:
657 retval = fdctrl_read_dor(fdctrl);
658 break;
659 case FD_REG_TDR:
660 retval = fdctrl_read_tape(fdctrl);
661 break;
662 case FD_REG_MSR:
663 retval = fdctrl_read_main_status(fdctrl);
664 break;
665 case FD_REG_FIFO:
666 retval = fdctrl_read_data(fdctrl);
667 break;
668 case FD_REG_DIR:
669 retval = fdctrl_read_dir(fdctrl);
670 break;
671 default:
672 retval = (uint32_t)(-1);
673 break;
674 }
675 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
676
677 return retval;
678 }
679
680 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
681 {
682 FDCtrl *fdctrl = opaque;
683
684 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
685
686 reg &= 7;
687 switch (reg) {
688 case FD_REG_DOR:
689 fdctrl_write_dor(fdctrl, value);
690 break;
691 case FD_REG_TDR:
692 fdctrl_write_tape(fdctrl, value);
693 break;
694 case FD_REG_DSR:
695 fdctrl_write_rate(fdctrl, value);
696 break;
697 case FD_REG_FIFO:
698 fdctrl_write_data(fdctrl, value);
699 break;
700 case FD_REG_CCR:
701 fdctrl_write_ccr(fdctrl, value);
702 break;
703 default:
704 break;
705 }
706 }
707
708 static uint64_t fdctrl_read_mem (void *opaque, hwaddr reg,
709 unsigned ize)
710 {
711 return fdctrl_read(opaque, (uint32_t)reg);
712 }
713
714 static void fdctrl_write_mem (void *opaque, hwaddr reg,
715 uint64_t value, unsigned size)
716 {
717 fdctrl_write(opaque, (uint32_t)reg, value);
718 }
719
720 static const MemoryRegionOps fdctrl_mem_ops = {
721 .read = fdctrl_read_mem,
722 .write = fdctrl_write_mem,
723 .endianness = DEVICE_NATIVE_ENDIAN,
724 };
725
726 static const MemoryRegionOps fdctrl_mem_strict_ops = {
727 .read = fdctrl_read_mem,
728 .write = fdctrl_write_mem,
729 .endianness = DEVICE_NATIVE_ENDIAN,
730 .valid = {
731 .min_access_size = 1,
732 .max_access_size = 1,
733 },
734 };
735
736 static bool fdrive_media_changed_needed(void *opaque)
737 {
738 FDrive *drive = opaque;
739
740 return (drive->media_inserted && drive->media_changed != 1);
741 }
742
743 static const VMStateDescription vmstate_fdrive_media_changed = {
744 .name = "fdrive/media_changed",
745 .version_id = 1,
746 .minimum_version_id = 1,
747 .needed = fdrive_media_changed_needed,
748 .fields = (VMStateField[]) {
749 VMSTATE_UINT8(media_changed, FDrive),
750 VMSTATE_END_OF_LIST()
751 }
752 };
753
754 static bool fdrive_media_rate_needed(void *opaque)
755 {
756 FDrive *drive = opaque;
757
758 return drive->fdctrl->check_media_rate;
759 }
760
761 static const VMStateDescription vmstate_fdrive_media_rate = {
762 .name = "fdrive/media_rate",
763 .version_id = 1,
764 .minimum_version_id = 1,
765 .needed = fdrive_media_rate_needed,
766 .fields = (VMStateField[]) {
767 VMSTATE_UINT8(media_rate, FDrive),
768 VMSTATE_END_OF_LIST()
769 }
770 };
771
772 static bool fdrive_perpendicular_needed(void *opaque)
773 {
774 FDrive *drive = opaque;
775
776 return drive->perpendicular != 0;
777 }
778
779 static const VMStateDescription vmstate_fdrive_perpendicular = {
780 .name = "fdrive/perpendicular",
781 .version_id = 1,
782 .minimum_version_id = 1,
783 .needed = fdrive_perpendicular_needed,
784 .fields = (VMStateField[]) {
785 VMSTATE_UINT8(perpendicular, FDrive),
786 VMSTATE_END_OF_LIST()
787 }
788 };
789
790 static int fdrive_post_load(void *opaque, int version_id)
791 {
792 fd_revalidate(opaque);
793 return 0;
794 }
795
796 static const VMStateDescription vmstate_fdrive = {
797 .name = "fdrive",
798 .version_id = 1,
799 .minimum_version_id = 1,
800 .post_load = fdrive_post_load,
801 .fields = (VMStateField[]) {
802 VMSTATE_UINT8(head, FDrive),
803 VMSTATE_UINT8(track, FDrive),
804 VMSTATE_UINT8(sect, FDrive),
805 VMSTATE_END_OF_LIST()
806 },
807 .subsections = (const VMStateDescription*[]) {
808 &vmstate_fdrive_media_changed,
809 &vmstate_fdrive_media_rate,
810 &vmstate_fdrive_perpendicular,
811 NULL
812 }
813 };
814
815 /*
816 * Reconstructs the phase from register values according to the logic that was
817 * implemented in qemu 2.3. This is the default value that is used if the phase
818 * subsection is not present on migration.
819 *
820 * Don't change this function to reflect newer qemu versions, it is part of
821 * the migration ABI.
822 */
823 static int reconstruct_phase(FDCtrl *fdctrl)
824 {
825 if (fdctrl->msr & FD_MSR_NONDMA) {
826 return FD_PHASE_EXECUTION;
827 } else if ((fdctrl->msr & FD_MSR_RQM) == 0) {
828 /* qemu 2.3 disabled RQM only during DMA transfers */
829 return FD_PHASE_EXECUTION;
830 } else if (fdctrl->msr & FD_MSR_DIO) {
831 return FD_PHASE_RESULT;
832 } else {
833 return FD_PHASE_COMMAND;
834 }
835 }
836
837 static void fdc_pre_save(void *opaque)
838 {
839 FDCtrl *s = opaque;
840
841 s->dor_vmstate = s->dor | GET_CUR_DRV(s);
842 }
843
844 static int fdc_pre_load(void *opaque)
845 {
846 FDCtrl *s = opaque;
847 s->phase = FD_PHASE_RECONSTRUCT;
848 return 0;
849 }
850
851 static int fdc_post_load(void *opaque, int version_id)
852 {
853 FDCtrl *s = opaque;
854
855 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
856 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
857
858 if (s->phase == FD_PHASE_RECONSTRUCT) {
859 s->phase = reconstruct_phase(s);
860 }
861
862 return 0;
863 }
864
865 static bool fdc_reset_sensei_needed(void *opaque)
866 {
867 FDCtrl *s = opaque;
868
869 return s->reset_sensei != 0;
870 }
871
872 static const VMStateDescription vmstate_fdc_reset_sensei = {
873 .name = "fdc/reset_sensei",
874 .version_id = 1,
875 .minimum_version_id = 1,
876 .needed = fdc_reset_sensei_needed,
877 .fields = (VMStateField[]) {
878 VMSTATE_INT32(reset_sensei, FDCtrl),
879 VMSTATE_END_OF_LIST()
880 }
881 };
882
883 static bool fdc_result_timer_needed(void *opaque)
884 {
885 FDCtrl *s = opaque;
886
887 return timer_pending(s->result_timer);
888 }
889
890 static const VMStateDescription vmstate_fdc_result_timer = {
891 .name = "fdc/result_timer",
892 .version_id = 1,
893 .minimum_version_id = 1,
894 .needed = fdc_result_timer_needed,
895 .fields = (VMStateField[]) {
896 VMSTATE_TIMER_PTR(result_timer, FDCtrl),
897 VMSTATE_END_OF_LIST()
898 }
899 };
900
901 static bool fdc_phase_needed(void *opaque)
902 {
903 FDCtrl *fdctrl = opaque;
904
905 return reconstruct_phase(fdctrl) != fdctrl->phase;
906 }
907
908 static const VMStateDescription vmstate_fdc_phase = {
909 .name = "fdc/phase",
910 .version_id = 1,
911 .minimum_version_id = 1,
912 .needed = fdc_phase_needed,
913 .fields = (VMStateField[]) {
914 VMSTATE_UINT8(phase, FDCtrl),
915 VMSTATE_END_OF_LIST()
916 }
917 };
918
919 static const VMStateDescription vmstate_fdc = {
920 .name = "fdc",
921 .version_id = 2,
922 .minimum_version_id = 2,
923 .pre_save = fdc_pre_save,
924 .pre_load = fdc_pre_load,
925 .post_load = fdc_post_load,
926 .fields = (VMStateField[]) {
927 /* Controller State */
928 VMSTATE_UINT8(sra, FDCtrl),
929 VMSTATE_UINT8(srb, FDCtrl),
930 VMSTATE_UINT8(dor_vmstate, FDCtrl),
931 VMSTATE_UINT8(tdr, FDCtrl),
932 VMSTATE_UINT8(dsr, FDCtrl),
933 VMSTATE_UINT8(msr, FDCtrl),
934 VMSTATE_UINT8(status0, FDCtrl),
935 VMSTATE_UINT8(status1, FDCtrl),
936 VMSTATE_UINT8(status2, FDCtrl),
937 /* Command FIFO */
938 VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8,
939 uint8_t),
940 VMSTATE_UINT32(data_pos, FDCtrl),
941 VMSTATE_UINT32(data_len, FDCtrl),
942 VMSTATE_UINT8(data_state, FDCtrl),
943 VMSTATE_UINT8(data_dir, FDCtrl),
944 VMSTATE_UINT8(eot, FDCtrl),
945 /* States kept only to be returned back */
946 VMSTATE_UINT8(timer0, FDCtrl),
947 VMSTATE_UINT8(timer1, FDCtrl),
948 VMSTATE_UINT8(precomp_trk, FDCtrl),
949 VMSTATE_UINT8(config, FDCtrl),
950 VMSTATE_UINT8(lock, FDCtrl),
951 VMSTATE_UINT8(pwrd, FDCtrl),
952 VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl),
953 VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1,
954 vmstate_fdrive, FDrive),
955 VMSTATE_END_OF_LIST()
956 },
957 .subsections = (const VMStateDescription*[]) {
958 &vmstate_fdc_reset_sensei,
959 &vmstate_fdc_result_timer,
960 &vmstate_fdc_phase,
961 NULL
962 }
963 };
964
965 static void fdctrl_external_reset_sysbus(DeviceState *d)
966 {
967 FDCtrlSysBus *sys = SYSBUS_FDC(d);
968 FDCtrl *s = &sys->state;
969
970 fdctrl_reset(s, 0);
971 }
972
973 static void fdctrl_external_reset_isa(DeviceState *d)
974 {
975 FDCtrlISABus *isa = ISA_FDC(d);
976 FDCtrl *s = &isa->state;
977
978 fdctrl_reset(s, 0);
979 }
980
981 static void fdctrl_handle_tc(void *opaque, int irq, int level)
982 {
983 //FDCtrl *s = opaque;
984
985 if (level) {
986 // XXX
987 FLOPPY_DPRINTF("TC pulsed\n");
988 }
989 }
990
991 /* Change IRQ state */
992 static void fdctrl_reset_irq(FDCtrl *fdctrl)
993 {
994 fdctrl->status0 = 0;
995 if (!(fdctrl->sra & FD_SRA_INTPEND))
996 return;
997 FLOPPY_DPRINTF("Reset interrupt\n");
998 qemu_set_irq(fdctrl->irq, 0);
999 fdctrl->sra &= ~FD_SRA_INTPEND;
1000 }
1001
1002 static void fdctrl_raise_irq(FDCtrl *fdctrl)
1003 {
1004 if (!(fdctrl->sra & FD_SRA_INTPEND)) {
1005 qemu_set_irq(fdctrl->irq, 1);
1006 fdctrl->sra |= FD_SRA_INTPEND;
1007 }
1008
1009 fdctrl->reset_sensei = 0;
1010 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
1011 }
1012
1013 /* Reset controller */
1014 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq)
1015 {
1016 int i;
1017
1018 FLOPPY_DPRINTF("reset controller\n");
1019 fdctrl_reset_irq(fdctrl);
1020 /* Initialise controller */
1021 fdctrl->sra = 0;
1022 fdctrl->srb = 0xc0;
1023 if (!fdctrl->drives[1].blk) {
1024 fdctrl->sra |= FD_SRA_nDRV2;
1025 }
1026 fdctrl->cur_drv = 0;
1027 fdctrl->dor = FD_DOR_nRESET;
1028 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
1029 fdctrl->msr = FD_MSR_RQM;
1030 fdctrl->reset_sensei = 0;
1031 timer_del(fdctrl->result_timer);
1032 /* FIFO state */
1033 fdctrl->data_pos = 0;
1034 fdctrl->data_len = 0;
1035 fdctrl->data_state = 0;
1036 fdctrl->data_dir = FD_DIR_WRITE;
1037 for (i = 0; i < MAX_FD; i++)
1038 fd_recalibrate(&fdctrl->drives[i]);
1039 fdctrl_to_command_phase(fdctrl);
1040 if (do_irq) {
1041 fdctrl->status0 |= FD_SR0_RDYCHG;
1042 fdctrl_raise_irq(fdctrl);
1043 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
1044 }
1045 }
1046
1047 static inline FDrive *drv0(FDCtrl *fdctrl)
1048 {
1049 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
1050 }
1051
1052 static inline FDrive *drv1(FDCtrl *fdctrl)
1053 {
1054 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
1055 return &fdctrl->drives[1];
1056 else
1057 return &fdctrl->drives[0];
1058 }
1059
1060 #if MAX_FD == 4
1061 static inline FDrive *drv2(FDCtrl *fdctrl)
1062 {
1063 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
1064 return &fdctrl->drives[2];
1065 else
1066 return &fdctrl->drives[1];
1067 }
1068
1069 static inline FDrive *drv3(FDCtrl *fdctrl)
1070 {
1071 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
1072 return &fdctrl->drives[3];
1073 else
1074 return &fdctrl->drives[2];
1075 }
1076 #endif
1077
1078 static FDrive *get_cur_drv(FDCtrl *fdctrl)
1079 {
1080 switch (fdctrl->cur_drv) {
1081 case 0: return drv0(fdctrl);
1082 case 1: return drv1(fdctrl);
1083 #if MAX_FD == 4
1084 case 2: return drv2(fdctrl);
1085 case 3: return drv3(fdctrl);
1086 #endif
1087 default: return NULL;
1088 }
1089 }
1090
1091 /* Status A register : 0x00 (read-only) */
1092 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl)
1093 {
1094 uint32_t retval = fdctrl->sra;
1095
1096 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
1097
1098 return retval;
1099 }
1100
1101 /* Status B register : 0x01 (read-only) */
1102 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl)
1103 {
1104 uint32_t retval = fdctrl->srb;
1105
1106 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
1107
1108 return retval;
1109 }
1110
1111 /* Digital output register : 0x02 */
1112 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl)
1113 {
1114 uint32_t retval = fdctrl->dor;
1115
1116 /* Selected drive */
1117 retval |= fdctrl->cur_drv;
1118 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
1119
1120 return retval;
1121 }
1122
1123 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value)
1124 {
1125 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
1126
1127 /* Motors */
1128 if (value & FD_DOR_MOTEN0)
1129 fdctrl->srb |= FD_SRB_MTR0;
1130 else
1131 fdctrl->srb &= ~FD_SRB_MTR0;
1132 if (value & FD_DOR_MOTEN1)
1133 fdctrl->srb |= FD_SRB_MTR1;
1134 else
1135 fdctrl->srb &= ~FD_SRB_MTR1;
1136
1137 /* Drive */
1138 if (value & 1)
1139 fdctrl->srb |= FD_SRB_DR0;
1140 else
1141 fdctrl->srb &= ~FD_SRB_DR0;
1142
1143 /* Reset */
1144 if (!(value & FD_DOR_nRESET)) {
1145 if (fdctrl->dor & FD_DOR_nRESET) {
1146 FLOPPY_DPRINTF("controller enter RESET state\n");
1147 }
1148 } else {
1149 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1150 FLOPPY_DPRINTF("controller out of RESET state\n");
1151 fdctrl_reset(fdctrl, 1);
1152 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1153 }
1154 }
1155 /* Selected drive */
1156 fdctrl->cur_drv = value & FD_DOR_SELMASK;
1157
1158 fdctrl->dor = value;
1159 }
1160
1161 /* Tape drive register : 0x03 */
1162 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl)
1163 {
1164 uint32_t retval = fdctrl->tdr;
1165
1166 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
1167
1168 return retval;
1169 }
1170
1171 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value)
1172 {
1173 /* Reset mode */
1174 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1175 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1176 return;
1177 }
1178 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
1179 /* Disk boot selection indicator */
1180 fdctrl->tdr = value & FD_TDR_BOOTSEL;
1181 /* Tape indicators: never allow */
1182 }
1183
1184 /* Main status register : 0x04 (read) */
1185 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl)
1186 {
1187 uint32_t retval = fdctrl->msr;
1188
1189 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1190 fdctrl->dor |= FD_DOR_nRESET;
1191
1192 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
1193
1194 return retval;
1195 }
1196
1197 /* Data select rate register : 0x04 (write) */
1198 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value)
1199 {
1200 /* Reset mode */
1201 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1202 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1203 return;
1204 }
1205 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
1206 /* Reset: autoclear */
1207 if (value & FD_DSR_SWRESET) {
1208 fdctrl->dor &= ~FD_DOR_nRESET;
1209 fdctrl_reset(fdctrl, 1);
1210 fdctrl->dor |= FD_DOR_nRESET;
1211 }
1212 if (value & FD_DSR_PWRDOWN) {
1213 fdctrl_reset(fdctrl, 1);
1214 }
1215 fdctrl->dsr = value;
1216 }
1217
1218 /* Configuration control register: 0x07 (write) */
1219 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value)
1220 {
1221 /* Reset mode */
1222 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1223 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1224 return;
1225 }
1226 FLOPPY_DPRINTF("configuration control register set to 0x%02x\n", value);
1227
1228 /* Only the rate selection bits used in AT mode, and we
1229 * store those in the DSR.
1230 */
1231 fdctrl->dsr = (fdctrl->dsr & ~FD_DSR_DRATEMASK) |
1232 (value & FD_DSR_DRATEMASK);
1233 }
1234
1235 static int fdctrl_media_changed(FDrive *drv)
1236 {
1237 return drv->media_changed;
1238 }
1239
1240 /* Digital input register : 0x07 (read-only) */
1241 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl)
1242 {
1243 uint32_t retval = 0;
1244
1245 if (fdctrl_media_changed(get_cur_drv(fdctrl))) {
1246 retval |= FD_DIR_DSKCHG;
1247 }
1248 if (retval != 0) {
1249 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
1250 }
1251
1252 return retval;
1253 }
1254
1255 /* Clear the FIFO and update the state for receiving the next command */
1256 static void fdctrl_to_command_phase(FDCtrl *fdctrl)
1257 {
1258 fdctrl->phase = FD_PHASE_COMMAND;
1259 fdctrl->data_dir = FD_DIR_WRITE;
1260 fdctrl->data_pos = 0;
1261 fdctrl->data_len = 1; /* Accept command byte, adjust for params later */
1262 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
1263 fdctrl->msr |= FD_MSR_RQM;
1264 }
1265
1266 /* Update the state to allow the guest to read out the command status.
1267 * @fifo_len is the number of result bytes to be read out. */
1268 static void fdctrl_to_result_phase(FDCtrl *fdctrl, int fifo_len)
1269 {
1270 fdctrl->phase = FD_PHASE_RESULT;
1271 fdctrl->data_dir = FD_DIR_READ;
1272 fdctrl->data_len = fifo_len;
1273 fdctrl->data_pos = 0;
1274 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
1275 }
1276
1277 /* Set an error: unimplemented/unknown command */
1278 static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction)
1279 {
1280 qemu_log_mask(LOG_UNIMP, "fdc: unimplemented command 0x%02x\n",
1281 fdctrl->fifo[0]);
1282 fdctrl->fifo[0] = FD_SR0_INVCMD;
1283 fdctrl_to_result_phase(fdctrl, 1);
1284 }
1285
1286 /* Seek to next sector
1287 * returns 0 when end of track reached (for DBL_SIDES on head 1)
1288 * otherwise returns 1
1289 */
1290 static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv)
1291 {
1292 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
1293 cur_drv->head, cur_drv->track, cur_drv->sect,
1294 fd_sector(cur_drv));
1295 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1296 error in fact */
1297 uint8_t new_head = cur_drv->head;
1298 uint8_t new_track = cur_drv->track;
1299 uint8_t new_sect = cur_drv->sect;
1300
1301 int ret = 1;
1302
1303 if (new_sect >= cur_drv->last_sect ||
1304 new_sect == fdctrl->eot) {
1305 new_sect = 1;
1306 if (FD_MULTI_TRACK(fdctrl->data_state)) {
1307 if (new_head == 0 &&
1308 (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
1309 new_head = 1;
1310 } else {
1311 new_head = 0;
1312 new_track++;
1313 fdctrl->status0 |= FD_SR0_SEEK;
1314 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0) {
1315 ret = 0;
1316 }
1317 }
1318 } else {
1319 fdctrl->status0 |= FD_SR0_SEEK;
1320 new_track++;
1321 ret = 0;
1322 }
1323 if (ret == 1) {
1324 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1325 new_head, new_track, new_sect, fd_sector(cur_drv));
1326 }
1327 } else {
1328 new_sect++;
1329 }
1330 fd_seek(cur_drv, new_head, new_track, new_sect, 1);
1331 return ret;
1332 }
1333
1334 /* Callback for transfer end (stop or abort) */
1335 static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0,
1336 uint8_t status1, uint8_t status2)
1337 {
1338 FDrive *cur_drv;
1339 cur_drv = get_cur_drv(fdctrl);
1340
1341 fdctrl->status0 &= ~(FD_SR0_DS0 | FD_SR0_DS1 | FD_SR0_HEAD);
1342 fdctrl->status0 |= GET_CUR_DRV(fdctrl);
1343 if (cur_drv->head) {
1344 fdctrl->status0 |= FD_SR0_HEAD;
1345 }
1346 fdctrl->status0 |= status0;
1347
1348 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
1349 status0, status1, status2, fdctrl->status0);
1350 fdctrl->fifo[0] = fdctrl->status0;
1351 fdctrl->fifo[1] = status1;
1352 fdctrl->fifo[2] = status2;
1353 fdctrl->fifo[3] = cur_drv->track;
1354 fdctrl->fifo[4] = cur_drv->head;
1355 fdctrl->fifo[5] = cur_drv->sect;
1356 fdctrl->fifo[6] = FD_SECTOR_SC;
1357 fdctrl->data_dir = FD_DIR_READ;
1358 if (!(fdctrl->msr & FD_MSR_NONDMA)) {
1359 DMA_release_DREQ(fdctrl->dma_chann);
1360 }
1361 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
1362 fdctrl->msr &= ~FD_MSR_NONDMA;
1363
1364 fdctrl_to_result_phase(fdctrl, 7);
1365 fdctrl_raise_irq(fdctrl);
1366 }
1367
1368 /* Prepare a data transfer (either DMA or FIFO) */
1369 static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction)
1370 {
1371 FDrive *cur_drv;
1372 uint8_t kh, kt, ks;
1373
1374 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1375 cur_drv = get_cur_drv(fdctrl);
1376 kt = fdctrl->fifo[2];
1377 kh = fdctrl->fifo[3];
1378 ks = fdctrl->fifo[4];
1379 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
1380 GET_CUR_DRV(fdctrl), kh, kt, ks,
1381 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1382 NUM_SIDES(cur_drv)));
1383 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1384 case 2:
1385 /* sect too big */
1386 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1387 fdctrl->fifo[3] = kt;
1388 fdctrl->fifo[4] = kh;
1389 fdctrl->fifo[5] = ks;
1390 return;
1391 case 3:
1392 /* track too big */
1393 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1394 fdctrl->fifo[3] = kt;
1395 fdctrl->fifo[4] = kh;
1396 fdctrl->fifo[5] = ks;
1397 return;
1398 case 4:
1399 /* No seek enabled */
1400 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1401 fdctrl->fifo[3] = kt;
1402 fdctrl->fifo[4] = kh;
1403 fdctrl->fifo[5] = ks;
1404 return;
1405 case 1:
1406 fdctrl->status0 |= FD_SR0_SEEK;
1407 break;
1408 default:
1409 break;
1410 }
1411
1412 /* Check the data rate. If the programmed data rate does not match
1413 * the currently inserted medium, the operation has to fail. */
1414 if (fdctrl->check_media_rate &&
1415 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
1416 FLOPPY_DPRINTF("data rate mismatch (fdc=%d, media=%d)\n",
1417 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
1418 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
1419 fdctrl->fifo[3] = kt;
1420 fdctrl->fifo[4] = kh;
1421 fdctrl->fifo[5] = ks;
1422 return;
1423 }
1424
1425 /* Set the FIFO state */
1426 fdctrl->data_dir = direction;
1427 fdctrl->data_pos = 0;
1428 assert(fdctrl->msr & FD_MSR_CMDBUSY);
1429 if (fdctrl->fifo[0] & 0x80)
1430 fdctrl->data_state |= FD_STATE_MULTI;
1431 else
1432 fdctrl->data_state &= ~FD_STATE_MULTI;
1433 if (fdctrl->fifo[5] == 0) {
1434 fdctrl->data_len = fdctrl->fifo[8];
1435 } else {
1436 int tmp;
1437 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
1438 tmp = (fdctrl->fifo[6] - ks + 1);
1439 if (fdctrl->fifo[0] & 0x80)
1440 tmp += fdctrl->fifo[6];
1441 fdctrl->data_len *= tmp;
1442 }
1443 fdctrl->eot = fdctrl->fifo[6];
1444 if (fdctrl->dor & FD_DOR_DMAEN) {
1445 int dma_mode;
1446 /* DMA transfer are enabled. Check if DMA channel is well programmed */
1447 dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
1448 dma_mode = (dma_mode >> 2) & 3;
1449 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
1450 dma_mode, direction,
1451 (128 << fdctrl->fifo[5]) *
1452 (cur_drv->last_sect - ks + 1), fdctrl->data_len);
1453 if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
1454 direction == FD_DIR_SCANH) && dma_mode == 0) ||
1455 (direction == FD_DIR_WRITE && dma_mode == 2) ||
1456 (direction == FD_DIR_READ && dma_mode == 1) ||
1457 (direction == FD_DIR_VERIFY)) {
1458 /* No access is allowed until DMA transfer has completed */
1459 fdctrl->msr &= ~FD_MSR_RQM;
1460 if (direction != FD_DIR_VERIFY) {
1461 /* Now, we just have to wait for the DMA controller to
1462 * recall us...
1463 */
1464 DMA_hold_DREQ(fdctrl->dma_chann);
1465 DMA_schedule();
1466 } else {
1467 /* Start transfer */
1468 fdctrl_transfer_handler(fdctrl, fdctrl->dma_chann, 0,
1469 fdctrl->data_len);
1470 }
1471 return;
1472 } else {
1473 FLOPPY_DPRINTF("bad dma_mode=%d direction=%d\n", dma_mode,
1474 direction);
1475 }
1476 }
1477 FLOPPY_DPRINTF("start non-DMA transfer\n");
1478 fdctrl->msr |= FD_MSR_NONDMA | FD_MSR_RQM;
1479 if (direction != FD_DIR_WRITE)
1480 fdctrl->msr |= FD_MSR_DIO;
1481 /* IO based transfer: calculate len */
1482 fdctrl_raise_irq(fdctrl);
1483 }
1484
1485 /* Prepare a transfer of deleted data */
1486 static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction)
1487 {
1488 qemu_log_mask(LOG_UNIMP, "fdctrl_start_transfer_del() unimplemented\n");
1489
1490 /* We don't handle deleted data,
1491 * so we don't return *ANYTHING*
1492 */
1493 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1494 }
1495
1496 /* handlers for DMA transfers */
1497 static int fdctrl_transfer_handler (void *opaque, int nchan,
1498 int dma_pos, int dma_len)
1499 {
1500 FDCtrl *fdctrl;
1501 FDrive *cur_drv;
1502 int len, start_pos, rel_pos;
1503 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1504
1505 fdctrl = opaque;
1506 if (fdctrl->msr & FD_MSR_RQM) {
1507 FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1508 return 0;
1509 }
1510 cur_drv = get_cur_drv(fdctrl);
1511 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1512 fdctrl->data_dir == FD_DIR_SCANH)
1513 status2 = FD_SR2_SNS;
1514 if (dma_len > fdctrl->data_len)
1515 dma_len = fdctrl->data_len;
1516 if (cur_drv->blk == NULL) {
1517 if (fdctrl->data_dir == FD_DIR_WRITE)
1518 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1519 else
1520 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1521 len = 0;
1522 goto transfer_error;
1523 }
1524 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1525 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1526 len = dma_len - fdctrl->data_pos;
1527 if (len + rel_pos > FD_SECTOR_LEN)
1528 len = FD_SECTOR_LEN - rel_pos;
1529 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1530 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
1531 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
1532 cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
1533 fd_sector(cur_drv) * FD_SECTOR_LEN);
1534 if (fdctrl->data_dir != FD_DIR_WRITE ||
1535 len < FD_SECTOR_LEN || rel_pos != 0) {
1536 /* READ & SCAN commands and realign to a sector for WRITE */
1537 if (blk_read(cur_drv->blk, fd_sector(cur_drv),
1538 fdctrl->fifo, 1) < 0) {
1539 FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1540 fd_sector(cur_drv));
1541 /* Sure, image size is too small... */
1542 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1543 }
1544 }
1545 switch (fdctrl->data_dir) {
1546 case FD_DIR_READ:
1547 /* READ commands */
1548 DMA_write_memory (nchan, fdctrl->fifo + rel_pos,
1549 fdctrl->data_pos, len);
1550 break;
1551 case FD_DIR_WRITE:
1552 /* WRITE commands */
1553 if (cur_drv->ro) {
1554 /* Handle readonly medium early, no need to do DMA, touch the
1555 * LED or attempt any writes. A real floppy doesn't attempt
1556 * to write to readonly media either. */
1557 fdctrl_stop_transfer(fdctrl,
1558 FD_SR0_ABNTERM | FD_SR0_SEEK, FD_SR1_NW,
1559 0x00);
1560 goto transfer_error;
1561 }
1562
1563 DMA_read_memory (nchan, fdctrl->fifo + rel_pos,
1564 fdctrl->data_pos, len);
1565 if (blk_write(cur_drv->blk, fd_sector(cur_drv),
1566 fdctrl->fifo, 1) < 0) {
1567 FLOPPY_DPRINTF("error writing sector %d\n",
1568 fd_sector(cur_drv));
1569 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1570 goto transfer_error;
1571 }
1572 break;
1573 case FD_DIR_VERIFY:
1574 /* VERIFY commands */
1575 break;
1576 default:
1577 /* SCAN commands */
1578 {
1579 uint8_t tmpbuf[FD_SECTOR_LEN];
1580 int ret;
1581 DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len);
1582 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
1583 if (ret == 0) {
1584 status2 = FD_SR2_SEH;
1585 goto end_transfer;
1586 }
1587 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1588 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
1589 status2 = 0x00;
1590 goto end_transfer;
1591 }
1592 }
1593 break;
1594 }
1595 fdctrl->data_pos += len;
1596 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1597 if (rel_pos == 0) {
1598 /* Seek to next sector */
1599 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1600 break;
1601 }
1602 }
1603 end_transfer:
1604 len = fdctrl->data_pos - start_pos;
1605 FLOPPY_DPRINTF("end transfer %d %d %d\n",
1606 fdctrl->data_pos, len, fdctrl->data_len);
1607 if (fdctrl->data_dir == FD_DIR_SCANE ||
1608 fdctrl->data_dir == FD_DIR_SCANL ||
1609 fdctrl->data_dir == FD_DIR_SCANH)
1610 status2 = FD_SR2_SEH;
1611 fdctrl->data_len -= len;
1612 fdctrl_stop_transfer(fdctrl, status0, status1, status2);
1613 transfer_error:
1614
1615 return len;
1616 }
1617
1618 /* Data register : 0x05 */
1619 static uint32_t fdctrl_read_data(FDCtrl *fdctrl)
1620 {
1621 FDrive *cur_drv;
1622 uint32_t retval = 0;
1623 uint32_t pos;
1624
1625 cur_drv = get_cur_drv(fdctrl);
1626 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1627 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
1628 FLOPPY_DPRINTF("error: controller not ready for reading\n");
1629 return 0;
1630 }
1631
1632 /* If data_len spans multiple sectors, the current position in the FIFO
1633 * wraps around while fdctrl->data_pos is the real position in the whole
1634 * request. */
1635 pos = fdctrl->data_pos;
1636 pos %= FD_SECTOR_LEN;
1637
1638 switch (fdctrl->phase) {
1639 case FD_PHASE_EXECUTION:
1640 assert(fdctrl->msr & FD_MSR_NONDMA);
1641 if (pos == 0) {
1642 if (fdctrl->data_pos != 0)
1643 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1644 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1645 fd_sector(cur_drv));
1646 return 0;
1647 }
1648 if (blk_read(cur_drv->blk, fd_sector(cur_drv), fdctrl->fifo, 1)
1649 < 0) {
1650 FLOPPY_DPRINTF("error getting sector %d\n",
1651 fd_sector(cur_drv));
1652 /* Sure, image size is too small... */
1653 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1654 }
1655 }
1656
1657 if (++fdctrl->data_pos == fdctrl->data_len) {
1658 fdctrl->msr &= ~FD_MSR_RQM;
1659 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1660 }
1661 break;
1662
1663 case FD_PHASE_RESULT:
1664 assert(!(fdctrl->msr & FD_MSR_NONDMA));
1665 if (++fdctrl->data_pos == fdctrl->data_len) {
1666 fdctrl->msr &= ~FD_MSR_RQM;
1667 fdctrl_to_command_phase(fdctrl);
1668 fdctrl_reset_irq(fdctrl);
1669 }
1670 break;
1671
1672 case FD_PHASE_COMMAND:
1673 default:
1674 abort();
1675 }
1676
1677 retval = fdctrl->fifo[pos];
1678 FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1679
1680 return retval;
1681 }
1682
1683 static void fdctrl_format_sector(FDCtrl *fdctrl)
1684 {
1685 FDrive *cur_drv;
1686 uint8_t kh, kt, ks;
1687
1688 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1689 cur_drv = get_cur_drv(fdctrl);
1690 kt = fdctrl->fifo[6];
1691 kh = fdctrl->fifo[7];
1692 ks = fdctrl->fifo[8];
1693 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
1694 GET_CUR_DRV(fdctrl), kh, kt, ks,
1695 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1696 NUM_SIDES(cur_drv)));
1697 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1698 case 2:
1699 /* sect too big */
1700 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1701 fdctrl->fifo[3] = kt;
1702 fdctrl->fifo[4] = kh;
1703 fdctrl->fifo[5] = ks;
1704 return;
1705 case 3:
1706 /* track too big */
1707 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1708 fdctrl->fifo[3] = kt;
1709 fdctrl->fifo[4] = kh;
1710 fdctrl->fifo[5] = ks;
1711 return;
1712 case 4:
1713 /* No seek enabled */
1714 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1715 fdctrl->fifo[3] = kt;
1716 fdctrl->fifo[4] = kh;
1717 fdctrl->fifo[5] = ks;
1718 return;
1719 case 1:
1720 fdctrl->status0 |= FD_SR0_SEEK;
1721 break;
1722 default:
1723 break;
1724 }
1725 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1726 if (cur_drv->blk == NULL ||
1727 blk_write(cur_drv->blk, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1728 FLOPPY_DPRINTF("error formatting sector %d\n", fd_sector(cur_drv));
1729 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1730 } else {
1731 if (cur_drv->sect == cur_drv->last_sect) {
1732 fdctrl->data_state &= ~FD_STATE_FORMAT;
1733 /* Last sector done */
1734 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1735 } else {
1736 /* More to do */
1737 fdctrl->data_pos = 0;
1738 fdctrl->data_len = 4;
1739 }
1740 }
1741 }
1742
1743 static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction)
1744 {
1745 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
1746 fdctrl->fifo[0] = fdctrl->lock << 4;
1747 fdctrl_to_result_phase(fdctrl, 1);
1748 }
1749
1750 static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction)
1751 {
1752 FDrive *cur_drv = get_cur_drv(fdctrl);
1753
1754 /* Drives position */
1755 fdctrl->fifo[0] = drv0(fdctrl)->track;
1756 fdctrl->fifo[1] = drv1(fdctrl)->track;
1757 #if MAX_FD == 4
1758 fdctrl->fifo[2] = drv2(fdctrl)->track;
1759 fdctrl->fifo[3] = drv3(fdctrl)->track;
1760 #else
1761 fdctrl->fifo[2] = 0;
1762 fdctrl->fifo[3] = 0;
1763 #endif
1764 /* timers */
1765 fdctrl->fifo[4] = fdctrl->timer0;
1766 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
1767 fdctrl->fifo[6] = cur_drv->last_sect;
1768 fdctrl->fifo[7] = (fdctrl->lock << 7) |
1769 (cur_drv->perpendicular << 2);
1770 fdctrl->fifo[8] = fdctrl->config;
1771 fdctrl->fifo[9] = fdctrl->precomp_trk;
1772 fdctrl_to_result_phase(fdctrl, 10);
1773 }
1774
1775 static void fdctrl_handle_version(FDCtrl *fdctrl, int direction)
1776 {
1777 /* Controller's version */
1778 fdctrl->fifo[0] = fdctrl->version;
1779 fdctrl_to_result_phase(fdctrl, 1);
1780 }
1781
1782 static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction)
1783 {
1784 fdctrl->fifo[0] = 0x41; /* Stepping 1 */
1785 fdctrl_to_result_phase(fdctrl, 1);
1786 }
1787
1788 static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction)
1789 {
1790 FDrive *cur_drv = get_cur_drv(fdctrl);
1791
1792 /* Drives position */
1793 drv0(fdctrl)->track = fdctrl->fifo[3];
1794 drv1(fdctrl)->track = fdctrl->fifo[4];
1795 #if MAX_FD == 4
1796 drv2(fdctrl)->track = fdctrl->fifo[5];
1797 drv3(fdctrl)->track = fdctrl->fifo[6];
1798 #endif
1799 /* timers */
1800 fdctrl->timer0 = fdctrl->fifo[7];
1801 fdctrl->timer1 = fdctrl->fifo[8];
1802 cur_drv->last_sect = fdctrl->fifo[9];
1803 fdctrl->lock = fdctrl->fifo[10] >> 7;
1804 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1805 fdctrl->config = fdctrl->fifo[11];
1806 fdctrl->precomp_trk = fdctrl->fifo[12];
1807 fdctrl->pwrd = fdctrl->fifo[13];
1808 fdctrl_to_command_phase(fdctrl);
1809 }
1810
1811 static void fdctrl_handle_save(FDCtrl *fdctrl, int direction)
1812 {
1813 FDrive *cur_drv = get_cur_drv(fdctrl);
1814
1815 fdctrl->fifo[0] = 0;
1816 fdctrl->fifo[1] = 0;
1817 /* Drives position */
1818 fdctrl->fifo[2] = drv0(fdctrl)->track;
1819 fdctrl->fifo[3] = drv1(fdctrl)->track;
1820 #if MAX_FD == 4
1821 fdctrl->fifo[4] = drv2(fdctrl)->track;
1822 fdctrl->fifo[5] = drv3(fdctrl)->track;
1823 #else
1824 fdctrl->fifo[4] = 0;
1825 fdctrl->fifo[5] = 0;
1826 #endif
1827 /* timers */
1828 fdctrl->fifo[6] = fdctrl->timer0;
1829 fdctrl->fifo[7] = fdctrl->timer1;
1830 fdctrl->fifo[8] = cur_drv->last_sect;
1831 fdctrl->fifo[9] = (fdctrl->lock << 7) |
1832 (cur_drv->perpendicular << 2);
1833 fdctrl->fifo[10] = fdctrl->config;
1834 fdctrl->fifo[11] = fdctrl->precomp_trk;
1835 fdctrl->fifo[12] = fdctrl->pwrd;
1836 fdctrl->fifo[13] = 0;
1837 fdctrl->fifo[14] = 0;
1838 fdctrl_to_result_phase(fdctrl, 15);
1839 }
1840
1841 static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction)
1842 {
1843 FDrive *cur_drv = get_cur_drv(fdctrl);
1844
1845 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1846 timer_mod(fdctrl->result_timer,
1847 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (get_ticks_per_sec() / 50));
1848 }
1849
1850 static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction)
1851 {
1852 FDrive *cur_drv;
1853
1854 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1855 cur_drv = get_cur_drv(fdctrl);
1856 fdctrl->data_state |= FD_STATE_FORMAT;
1857 if (fdctrl->fifo[0] & 0x80)
1858 fdctrl->data_state |= FD_STATE_MULTI;
1859 else
1860 fdctrl->data_state &= ~FD_STATE_MULTI;
1861 cur_drv->bps =
1862 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1863 #if 0
1864 cur_drv->last_sect =
1865 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1866 fdctrl->fifo[3] / 2;
1867 #else
1868 cur_drv->last_sect = fdctrl->fifo[3];
1869 #endif
1870 /* TODO: implement format using DMA expected by the Bochs BIOS
1871 * and Linux fdformat (read 3 bytes per sector via DMA and fill
1872 * the sector with the specified fill byte
1873 */
1874 fdctrl->data_state &= ~FD_STATE_FORMAT;
1875 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1876 }
1877
1878 static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction)
1879 {
1880 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
1881 fdctrl->timer1 = fdctrl->fifo[2] >> 1;
1882 if (fdctrl->fifo[2] & 1)
1883 fdctrl->dor &= ~FD_DOR_DMAEN;
1884 else
1885 fdctrl->dor |= FD_DOR_DMAEN;
1886 /* No result back */
1887 fdctrl_to_command_phase(fdctrl);
1888 }
1889
1890 static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction)
1891 {
1892 FDrive *cur_drv;
1893
1894 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1895 cur_drv = get_cur_drv(fdctrl);
1896 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1897 /* 1 Byte status back */
1898 fdctrl->fifo[0] = (cur_drv->ro << 6) |
1899 (cur_drv->track == 0 ? 0x10 : 0x00) |
1900 (cur_drv->head << 2) |
1901 GET_CUR_DRV(fdctrl) |
1902 0x28;
1903 fdctrl_to_result_phase(fdctrl, 1);
1904 }
1905
1906 static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction)
1907 {
1908 FDrive *cur_drv;
1909
1910 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1911 cur_drv = get_cur_drv(fdctrl);
1912 fd_recalibrate(cur_drv);
1913 fdctrl_to_command_phase(fdctrl);
1914 /* Raise Interrupt */
1915 fdctrl->status0 |= FD_SR0_SEEK;
1916 fdctrl_raise_irq(fdctrl);
1917 }
1918
1919 static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction)
1920 {
1921 FDrive *cur_drv = get_cur_drv(fdctrl);
1922
1923 if (fdctrl->reset_sensei > 0) {
1924 fdctrl->fifo[0] =
1925 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
1926 fdctrl->reset_sensei--;
1927 } else if (!(fdctrl->sra & FD_SRA_INTPEND)) {
1928 fdctrl->fifo[0] = FD_SR0_INVCMD;
1929 fdctrl_to_result_phase(fdctrl, 1);
1930 return;
1931 } else {
1932 fdctrl->fifo[0] =
1933 (fdctrl->status0 & ~(FD_SR0_HEAD | FD_SR0_DS1 | FD_SR0_DS0))
1934 | GET_CUR_DRV(fdctrl);
1935 }
1936
1937 fdctrl->fifo[1] = cur_drv->track;
1938 fdctrl_to_result_phase(fdctrl, 2);
1939 fdctrl_reset_irq(fdctrl);
1940 fdctrl->status0 = FD_SR0_RDYCHG;
1941 }
1942
1943 static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction)
1944 {
1945 FDrive *cur_drv;
1946
1947 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1948 cur_drv = get_cur_drv(fdctrl);
1949 fdctrl_to_command_phase(fdctrl);
1950 /* The seek command just sends step pulses to the drive and doesn't care if
1951 * there is a medium inserted of if it's banging the head against the drive.
1952 */
1953 fd_seek(cur_drv, cur_drv->head, fdctrl->fifo[2], cur_drv->sect, 1);
1954 /* Raise Interrupt */
1955 fdctrl->status0 |= FD_SR0_SEEK;
1956 fdctrl_raise_irq(fdctrl);
1957 }
1958
1959 static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction)
1960 {
1961 FDrive *cur_drv = get_cur_drv(fdctrl);
1962
1963 if (fdctrl->fifo[1] & 0x80)
1964 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
1965 /* No result back */
1966 fdctrl_to_command_phase(fdctrl);
1967 }
1968
1969 static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction)
1970 {
1971 fdctrl->config = fdctrl->fifo[2];
1972 fdctrl->precomp_trk = fdctrl->fifo[3];
1973 /* No result back */
1974 fdctrl_to_command_phase(fdctrl);
1975 }
1976
1977 static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction)
1978 {
1979 fdctrl->pwrd = fdctrl->fifo[1];
1980 fdctrl->fifo[0] = fdctrl->fifo[1];
1981 fdctrl_to_result_phase(fdctrl, 1);
1982 }
1983
1984 static void fdctrl_handle_option(FDCtrl *fdctrl, int direction)
1985 {
1986 /* No result back */
1987 fdctrl_to_command_phase(fdctrl);
1988 }
1989
1990 static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction)
1991 {
1992 FDrive *cur_drv = get_cur_drv(fdctrl);
1993 uint32_t pos;
1994
1995 pos = fdctrl->data_pos - 1;
1996 pos %= FD_SECTOR_LEN;
1997 if (fdctrl->fifo[pos] & 0x80) {
1998 /* Command parameters done */
1999 if (fdctrl->fifo[pos] & 0x40) {
2000 fdctrl->fifo[0] = fdctrl->fifo[1];
2001 fdctrl->fifo[2] = 0;
2002 fdctrl->fifo[3] = 0;
2003 fdctrl_to_result_phase(fdctrl, 4);
2004 } else {
2005 fdctrl_to_command_phase(fdctrl);
2006 }
2007 } else if (fdctrl->data_len > 7) {
2008 /* ERROR */
2009 fdctrl->fifo[0] = 0x80 |
2010 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
2011 fdctrl_to_result_phase(fdctrl, 1);
2012 }
2013 }
2014
2015 static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction)
2016 {
2017 FDrive *cur_drv;
2018
2019 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
2020 cur_drv = get_cur_drv(fdctrl);
2021 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
2022 fd_seek(cur_drv, cur_drv->head, cur_drv->max_track - 1,
2023 cur_drv->sect, 1);
2024 } else {
2025 fd_seek(cur_drv, cur_drv->head,
2026 cur_drv->track + fdctrl->fifo[2], cur_drv->sect, 1);
2027 }
2028 fdctrl_to_command_phase(fdctrl);
2029 /* Raise Interrupt */
2030 fdctrl->status0 |= FD_SR0_SEEK;
2031 fdctrl_raise_irq(fdctrl);
2032 }
2033
2034 static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction)
2035 {
2036 FDrive *cur_drv;
2037
2038 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
2039 cur_drv = get_cur_drv(fdctrl);
2040 if (fdctrl->fifo[2] > cur_drv->track) {
2041 fd_seek(cur_drv, cur_drv->head, 0, cur_drv->sect, 1);
2042 } else {
2043 fd_seek(cur_drv, cur_drv->head,
2044 cur_drv->track - fdctrl->fifo[2], cur_drv->sect, 1);
2045 }
2046 fdctrl_to_command_phase(fdctrl);
2047 /* Raise Interrupt */
2048 fdctrl->status0 |= FD_SR0_SEEK;
2049 fdctrl_raise_irq(fdctrl);
2050 }
2051
2052 /*
2053 * Handlers for the execution phase of each command
2054 */
2055 typedef struct FDCtrlCommand {
2056 uint8_t value;
2057 uint8_t mask;
2058 const char* name;
2059 int parameters;
2060 void (*handler)(FDCtrl *fdctrl, int direction);
2061 int direction;
2062 } FDCtrlCommand;
2063
2064 static const FDCtrlCommand handlers[] = {
2065 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
2066 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
2067 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
2068 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
2069 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
2070 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
2071 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
2072 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
2073 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
2074 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
2075 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
2076 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_start_transfer, FD_DIR_VERIFY },
2077 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
2078 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
2079 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
2080 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
2081 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
2082 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
2083 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
2084 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
2085 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
2086 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
2087 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
2088 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
2089 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
2090 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
2091 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
2092 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
2093 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
2094 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
2095 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
2096 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
2097 };
2098 /* Associate command to an index in the 'handlers' array */
2099 static uint8_t command_to_handler[256];
2100
2101 static const FDCtrlCommand *get_command(uint8_t cmd)
2102 {
2103 int idx;
2104
2105 idx = command_to_handler[cmd];
2106 FLOPPY_DPRINTF("%s command\n", handlers[idx].name);
2107 return &handlers[idx];
2108 }
2109
2110 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value)
2111 {
2112 FDrive *cur_drv;
2113 const FDCtrlCommand *cmd;
2114 uint32_t pos;
2115
2116 /* Reset mode */
2117 if (!(fdctrl->dor & FD_DOR_nRESET)) {
2118 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
2119 return;
2120 }
2121 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
2122 FLOPPY_DPRINTF("error: controller not ready for writing\n");
2123 return;
2124 }
2125 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
2126
2127 FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
2128
2129 /* If data_len spans multiple sectors, the current position in the FIFO
2130 * wraps around while fdctrl->data_pos is the real position in the whole
2131 * request. */
2132 pos = fdctrl->data_pos++;
2133 pos %= FD_SECTOR_LEN;
2134 fdctrl->fifo[pos] = value;
2135
2136 if (fdctrl->data_pos == fdctrl->data_len) {
2137 fdctrl->msr &= ~FD_MSR_RQM;
2138 }
2139
2140 switch (fdctrl->phase) {
2141 case FD_PHASE_EXECUTION:
2142 /* For DMA requests, RQM should be cleared during execution phase, so
2143 * we would have errored out above. */
2144 assert(fdctrl->msr & FD_MSR_NONDMA);
2145
2146 /* FIFO data write */
2147 if (pos == FD_SECTOR_LEN - 1 ||
2148 fdctrl->data_pos == fdctrl->data_len) {
2149 cur_drv = get_cur_drv(fdctrl);
2150 if (blk_write(cur_drv->blk, fd_sector(cur_drv), fdctrl->fifo, 1)
2151 < 0) {
2152 FLOPPY_DPRINTF("error writing sector %d\n",
2153 fd_sector(cur_drv));
2154 break;
2155 }
2156 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
2157 FLOPPY_DPRINTF("error seeking to next sector %d\n",
2158 fd_sector(cur_drv));
2159 break;
2160 }
2161 }
2162
2163 /* Switch to result phase when done with the transfer */
2164 if (fdctrl->data_pos == fdctrl->data_len) {
2165 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
2166 }
2167 break;
2168
2169 case FD_PHASE_COMMAND:
2170 assert(!(fdctrl->msr & FD_MSR_NONDMA));
2171 assert(fdctrl->data_pos < FD_SECTOR_LEN);
2172
2173 if (pos == 0) {
2174 /* The first byte specifies the command. Now we start reading
2175 * as many parameters as this command requires. */
2176 cmd = get_command(value);
2177 fdctrl->data_len = cmd->parameters + 1;
2178 if (cmd->parameters) {
2179 fdctrl->msr |= FD_MSR_RQM;
2180 }
2181 fdctrl->msr |= FD_MSR_CMDBUSY;
2182 }
2183
2184 if (fdctrl->data_pos == fdctrl->data_len) {
2185 /* We have all parameters now, execute the command */
2186 fdctrl->phase = FD_PHASE_EXECUTION;
2187
2188 if (fdctrl->data_state & FD_STATE_FORMAT) {
2189 fdctrl_format_sector(fdctrl);
2190 break;
2191 }
2192
2193 cmd = get_command(fdctrl->fifo[0]);
2194 FLOPPY_DPRINTF("Calling handler for '%s'\n", cmd->name);
2195 cmd->handler(fdctrl, cmd->direction);
2196 }
2197 break;
2198
2199 case FD_PHASE_RESULT:
2200 default:
2201 abort();
2202 }
2203 }
2204
2205 static void fdctrl_result_timer(void *opaque)
2206 {
2207 FDCtrl *fdctrl = opaque;
2208 FDrive *cur_drv = get_cur_drv(fdctrl);
2209
2210 /* Pretend we are spinning.
2211 * This is needed for Coherent, which uses READ ID to check for
2212 * sector interleaving.
2213 */
2214 if (cur_drv->last_sect != 0) {
2215 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
2216 }
2217 /* READ_ID can't automatically succeed! */
2218 if (fdctrl->check_media_rate &&
2219 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
2220 FLOPPY_DPRINTF("read id rate mismatch (fdc=%d, media=%d)\n",
2221 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
2222 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
2223 } else {
2224 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
2225 }
2226 }
2227
2228 static void fdctrl_change_cb(void *opaque, bool load)
2229 {
2230 FDrive *drive = opaque;
2231
2232 drive->media_inserted = load && drive->blk && blk_is_inserted(drive->blk);
2233
2234 drive->media_changed = 1;
2235 drive->media_validated = false;
2236 fd_revalidate(drive);
2237 }
2238
2239 static bool fdctrl_is_tray_open(void *opaque)
2240 {
2241 FDrive *drive = opaque;
2242 return !drive->media_inserted;
2243 }
2244
2245 static const BlockDevOps fdctrl_block_ops = {
2246 .change_media_cb = fdctrl_change_cb,
2247 .is_tray_open = fdctrl_is_tray_open,
2248 };
2249
2250 /* Init functions */
2251 static void fdctrl_connect_drives(FDCtrl *fdctrl, Error **errp)
2252 {
2253 unsigned int i;
2254 FDrive *drive;
2255
2256 for (i = 0; i < MAX_FD; i++) {
2257 drive = &fdctrl->drives[i];
2258 drive->fdctrl = fdctrl;
2259
2260 if (drive->blk) {
2261 if (blk_get_on_error(drive->blk, 0) != BLOCKDEV_ON_ERROR_ENOSPC) {
2262 error_setg(errp, "fdc doesn't support drive option werror");
2263 return;
2264 }
2265 if (blk_get_on_error(drive->blk, 1) != BLOCKDEV_ON_ERROR_REPORT) {
2266 error_setg(errp, "fdc doesn't support drive option rerror");
2267 return;
2268 }
2269 }
2270
2271 fd_init(drive);
2272 if (drive->blk) {
2273 blk_set_dev_ops(drive->blk, &fdctrl_block_ops, drive);
2274 drive->media_inserted = blk_is_inserted(drive->blk);
2275 pick_drive_type(drive);
2276 }
2277 fd_revalidate(drive);
2278 }
2279 }
2280
2281 ISADevice *fdctrl_init_isa(ISABus *bus, DriveInfo **fds)
2282 {
2283 DeviceState *dev;
2284 ISADevice *isadev;
2285
2286 isadev = isa_try_create(bus, TYPE_ISA_FDC);
2287 if (!isadev) {
2288 return NULL;
2289 }
2290 dev = DEVICE(isadev);
2291
2292 if (fds[0]) {
2293 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fds[0]),
2294 &error_fatal);
2295 }
2296 if (fds[1]) {
2297 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fds[1]),
2298 &error_fatal);
2299 }
2300 qdev_init_nofail(dev);
2301
2302 return isadev;
2303 }
2304
2305 void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
2306 hwaddr mmio_base, DriveInfo **fds)
2307 {
2308 FDCtrl *fdctrl;
2309 DeviceState *dev;
2310 SysBusDevice *sbd;
2311 FDCtrlSysBus *sys;
2312
2313 dev = qdev_create(NULL, "sysbus-fdc");
2314 sys = SYSBUS_FDC(dev);
2315 fdctrl = &sys->state;
2316 fdctrl->dma_chann = dma_chann; /* FIXME */
2317 if (fds[0]) {
2318 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fds[0]),
2319 &error_fatal);
2320 }
2321 if (fds[1]) {
2322 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fds[1]),
2323 &error_fatal);
2324 }
2325 qdev_init_nofail(dev);
2326 sbd = SYS_BUS_DEVICE(dev);
2327 sysbus_connect_irq(sbd, 0, irq);
2328 sysbus_mmio_map(sbd, 0, mmio_base);
2329 }
2330
2331 void sun4m_fdctrl_init(qemu_irq irq, hwaddr io_base,
2332 DriveInfo **fds, qemu_irq *fdc_tc)
2333 {
2334 DeviceState *dev;
2335 FDCtrlSysBus *sys;
2336
2337 dev = qdev_create(NULL, "SUNW,fdtwo");
2338 if (fds[0]) {
2339 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(fds[0]),
2340 &error_fatal);
2341 }
2342 qdev_init_nofail(dev);
2343 sys = SYSBUS_FDC(dev);
2344 sysbus_connect_irq(SYS_BUS_DEVICE(sys), 0, irq);
2345 sysbus_mmio_map(SYS_BUS_DEVICE(sys), 0, io_base);
2346 *fdc_tc = qdev_get_gpio_in(dev, 0);
2347 }
2348
2349 static void fdctrl_realize_common(FDCtrl *fdctrl, Error **errp)
2350 {
2351 int i, j;
2352 static int command_tables_inited = 0;
2353
2354 if (fdctrl->fallback == FLOPPY_DRIVE_TYPE_AUTO) {
2355 error_setg(errp, "Cannot choose a fallback FDrive type of 'auto'");
2356 }
2357
2358 /* Fill 'command_to_handler' lookup table */
2359 if (!command_tables_inited) {
2360 command_tables_inited = 1;
2361 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
2362 for (j = 0; j < sizeof(command_to_handler); j++) {
2363 if ((j & handlers[i].mask) == handlers[i].value) {
2364 command_to_handler[j] = i;
2365 }
2366 }
2367 }
2368 }
2369
2370 FLOPPY_DPRINTF("init controller\n");
2371 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
2372 fdctrl->fifo_size = 512;
2373 fdctrl->result_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
2374 fdctrl_result_timer, fdctrl);
2375
2376 fdctrl->version = 0x90; /* Intel 82078 controller */
2377 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
2378 fdctrl->num_floppies = MAX_FD;
2379
2380 if (fdctrl->dma_chann != -1) {
2381 DMA_register_channel(fdctrl->dma_chann, &fdctrl_transfer_handler, fdctrl);
2382 }
2383 fdctrl_connect_drives(fdctrl, errp);
2384 }
2385
2386 static const MemoryRegionPortio fdc_portio_list[] = {
2387 { 1, 5, 1, .read = fdctrl_read, .write = fdctrl_write },
2388 { 7, 1, 1, .read = fdctrl_read, .write = fdctrl_write },
2389 PORTIO_END_OF_LIST(),
2390 };
2391
2392 static void isabus_fdc_realize(DeviceState *dev, Error **errp)
2393 {
2394 ISADevice *isadev = ISA_DEVICE(dev);
2395 FDCtrlISABus *isa = ISA_FDC(dev);
2396 FDCtrl *fdctrl = &isa->state;
2397 Error *err = NULL;
2398
2399 isa_register_portio_list(isadev, isa->iobase, fdc_portio_list, fdctrl,
2400 "fdc");
2401
2402 isa_init_irq(isadev, &fdctrl->irq, isa->irq);
2403 fdctrl->dma_chann = isa->dma;
2404
2405 qdev_set_legacy_instance_id(dev, isa->iobase, 2);
2406 fdctrl_realize_common(fdctrl, &err);
2407 if (err != NULL) {
2408 error_propagate(errp, err);
2409 return;
2410 }
2411 }
2412
2413 static void sysbus_fdc_initfn(Object *obj)
2414 {
2415 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
2416 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
2417 FDCtrl *fdctrl = &sys->state;
2418
2419 fdctrl->dma_chann = -1;
2420
2421 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_ops, fdctrl,
2422 "fdc", 0x08);
2423 sysbus_init_mmio(sbd, &fdctrl->iomem);
2424 }
2425
2426 static void sun4m_fdc_initfn(Object *obj)
2427 {
2428 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
2429 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
2430 FDCtrl *fdctrl = &sys->state;
2431
2432 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_strict_ops,
2433 fdctrl, "fdctrl", 0x08);
2434 sysbus_init_mmio(sbd, &fdctrl->iomem);
2435 }
2436
2437 static void sysbus_fdc_common_initfn(Object *obj)
2438 {
2439 DeviceState *dev = DEVICE(obj);
2440 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
2441 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
2442 FDCtrl *fdctrl = &sys->state;
2443
2444 qdev_set_legacy_instance_id(dev, 0 /* io */, 2); /* FIXME */
2445
2446 sysbus_init_irq(sbd, &fdctrl->irq);
2447 qdev_init_gpio_in(dev, fdctrl_handle_tc, 1);
2448 }
2449
2450 static void sysbus_fdc_common_realize(DeviceState *dev, Error **errp)
2451 {
2452 FDCtrlSysBus *sys = SYSBUS_FDC(dev);
2453 FDCtrl *fdctrl = &sys->state;
2454
2455 fdctrl_realize_common(fdctrl, errp);
2456 }
2457
2458 FloppyDriveType isa_fdc_get_drive_type(ISADevice *fdc, int i)
2459 {
2460 FDCtrlISABus *isa = ISA_FDC(fdc);
2461
2462 return isa->state.drives[i].drive;
2463 }
2464
2465 static const VMStateDescription vmstate_isa_fdc ={
2466 .name = "fdc",
2467 .version_id = 2,
2468 .minimum_version_id = 2,
2469 .fields = (VMStateField[]) {
2470 VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl),
2471 VMSTATE_END_OF_LIST()
2472 }
2473 };
2474
2475 static Property isa_fdc_properties[] = {
2476 DEFINE_PROP_UINT32("iobase", FDCtrlISABus, iobase, 0x3f0),
2477 DEFINE_PROP_UINT32("irq", FDCtrlISABus, irq, 6),
2478 DEFINE_PROP_UINT32("dma", FDCtrlISABus, dma, 2),
2479 DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.drives[0].blk),
2480 DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.drives[1].blk),
2481 DEFINE_PROP_BIT("check_media_rate", FDCtrlISABus, state.check_media_rate,
2482 0, true),
2483 DEFINE_PROP_DEFAULT("fdtypeA", FDCtrlISABus, state.drives[0].drive,
2484 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2485 FloppyDriveType),
2486 DEFINE_PROP_DEFAULT("fdtypeB", FDCtrlISABus, state.drives[1].drive,
2487 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2488 FloppyDriveType),
2489 DEFINE_PROP_DEFAULT("fallback", FDCtrlISABus, state.fallback,
2490 FLOPPY_DRIVE_TYPE_144, qdev_prop_fdc_drive_type,
2491 FloppyDriveType),
2492 DEFINE_PROP_END_OF_LIST(),
2493 };
2494
2495 static void isabus_fdc_class_init(ObjectClass *klass, void *data)
2496 {
2497 DeviceClass *dc = DEVICE_CLASS(klass);
2498
2499 dc->realize = isabus_fdc_realize;
2500 dc->fw_name = "fdc";
2501 dc->reset = fdctrl_external_reset_isa;
2502 dc->vmsd = &vmstate_isa_fdc;
2503 dc->props = isa_fdc_properties;
2504 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
2505 }
2506
2507 static void isabus_fdc_instance_init(Object *obj)
2508 {
2509 FDCtrlISABus *isa = ISA_FDC(obj);
2510
2511 device_add_bootindex_property(obj, &isa->bootindexA,
2512 "bootindexA", "/floppy@0",
2513 DEVICE(obj), NULL);
2514 device_add_bootindex_property(obj, &isa->bootindexB,
2515 "bootindexB", "/floppy@1",
2516 DEVICE(obj), NULL);
2517 }
2518
2519 static const TypeInfo isa_fdc_info = {
2520 .name = TYPE_ISA_FDC,
2521 .parent = TYPE_ISA_DEVICE,
2522 .instance_size = sizeof(FDCtrlISABus),
2523 .class_init = isabus_fdc_class_init,
2524 .instance_init = isabus_fdc_instance_init,
2525 };
2526
2527 static const VMStateDescription vmstate_sysbus_fdc ={
2528 .name = "fdc",
2529 .version_id = 2,
2530 .minimum_version_id = 2,
2531 .fields = (VMStateField[]) {
2532 VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl),
2533 VMSTATE_END_OF_LIST()
2534 }
2535 };
2536
2537 static Property sysbus_fdc_properties[] = {
2538 DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.drives[0].blk),
2539 DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.drives[1].blk),
2540 DEFINE_PROP_DEFAULT("fdtypeA", FDCtrlSysBus, state.drives[0].drive,
2541 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2542 FloppyDriveType),
2543 DEFINE_PROP_DEFAULT("fdtypeB", FDCtrlSysBus, state.drives[1].drive,
2544 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2545 FloppyDriveType),
2546 DEFINE_PROP_DEFAULT("fallback", FDCtrlISABus, state.fallback,
2547 FLOPPY_DRIVE_TYPE_144, qdev_prop_fdc_drive_type,
2548 FloppyDriveType),
2549 DEFINE_PROP_END_OF_LIST(),
2550 };
2551
2552 static void sysbus_fdc_class_init(ObjectClass *klass, void *data)
2553 {
2554 DeviceClass *dc = DEVICE_CLASS(klass);
2555
2556 dc->props = sysbus_fdc_properties;
2557 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
2558 }
2559
2560 static const TypeInfo sysbus_fdc_info = {
2561 .name = "sysbus-fdc",
2562 .parent = TYPE_SYSBUS_FDC,
2563 .instance_init = sysbus_fdc_initfn,
2564 .class_init = sysbus_fdc_class_init,
2565 };
2566
2567 static Property sun4m_fdc_properties[] = {
2568 DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.drives[0].blk),
2569 DEFINE_PROP_DEFAULT("fdtype", FDCtrlSysBus, state.drives[0].drive,
2570 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2571 FloppyDriveType),
2572 DEFINE_PROP_DEFAULT("fallback", FDCtrlISABus, state.fallback,
2573 FLOPPY_DRIVE_TYPE_144, qdev_prop_fdc_drive_type,
2574 FloppyDriveType),
2575 DEFINE_PROP_END_OF_LIST(),
2576 };
2577
2578 static void sun4m_fdc_class_init(ObjectClass *klass, void *data)
2579 {
2580 DeviceClass *dc = DEVICE_CLASS(klass);
2581
2582 dc->props = sun4m_fdc_properties;
2583 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
2584 }
2585
2586 static const TypeInfo sun4m_fdc_info = {
2587 .name = "SUNW,fdtwo",
2588 .parent = TYPE_SYSBUS_FDC,
2589 .instance_init = sun4m_fdc_initfn,
2590 .class_init = sun4m_fdc_class_init,
2591 };
2592
2593 static void sysbus_fdc_common_class_init(ObjectClass *klass, void *data)
2594 {
2595 DeviceClass *dc = DEVICE_CLASS(klass);
2596
2597 dc->realize = sysbus_fdc_common_realize;
2598 dc->reset = fdctrl_external_reset_sysbus;
2599 dc->vmsd = &vmstate_sysbus_fdc;
2600 }
2601
2602 static const TypeInfo sysbus_fdc_type_info = {
2603 .name = TYPE_SYSBUS_FDC,
2604 .parent = TYPE_SYS_BUS_DEVICE,
2605 .instance_size = sizeof(FDCtrlSysBus),
2606 .instance_init = sysbus_fdc_common_initfn,
2607 .abstract = true,
2608 .class_init = sysbus_fdc_common_class_init,
2609 };
2610
2611 static void fdc_register_types(void)
2612 {
2613 type_register_static(&isa_fdc_info);
2614 type_register_static(&sysbus_fdc_type_info);
2615 type_register_static(&sysbus_fdc_info);
2616 type_register_static(&sun4m_fdc_info);
2617 }
2618
2619 type_init(fdc_register_types)
AR7 emulation for QEMU