4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
23 #include "tcg/tcg-op.h"
24 #include "tcg/tcg-op-gvec.h"
27 #include "translate.h"
28 #include "internals.h"
29 #include "qemu/host-utils.h"
31 #include "hw/semihosting/semihost.h"
32 #include "exec/gen-icount.h"
34 #include "exec/helper-proto.h"
35 #include "exec/helper-gen.h"
38 #include "trace-tcg.h"
39 #include "translate-a64.h"
40 #include "qemu/atomic128.h"
42 static TCGv_i64 cpu_X
[32];
43 static TCGv_i64 cpu_pc
;
45 /* Load/store exclusive handling */
46 static TCGv_i64 cpu_exclusive_high
;
48 static const char *regnames
[] = {
49 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
50 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
51 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
52 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
56 A64_SHIFT_TYPE_LSL
= 0,
57 A64_SHIFT_TYPE_LSR
= 1,
58 A64_SHIFT_TYPE_ASR
= 2,
59 A64_SHIFT_TYPE_ROR
= 3
62 /* Table based decoder typedefs - used when the relevant bits for decode
63 * are too awkwardly scattered across the instruction (eg SIMD).
65 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
67 typedef struct AArch64DecodeTable
{
70 AArch64DecodeFn
*disas_fn
;
73 /* initialize TCG globals. */
74 void a64_translate_init(void)
78 cpu_pc
= tcg_global_mem_new_i64(cpu_env
,
79 offsetof(CPUARMState
, pc
),
81 for (i
= 0; i
< 32; i
++) {
82 cpu_X
[i
] = tcg_global_mem_new_i64(cpu_env
,
83 offsetof(CPUARMState
, xregs
[i
]),
87 cpu_exclusive_high
= tcg_global_mem_new_i64(cpu_env
,
88 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
92 * Return the core mmu_idx to use for A64 "unprivileged load/store" insns
94 static int get_a64_user_mem_index(DisasContext
*s
)
97 * If AccType_UNPRIV is not used, the insn uses AccType_NORMAL,
98 * which is the usual mmu_idx for this cpu state.
100 ARMMMUIdx useridx
= s
->mmu_idx
;
104 * We have pre-computed the condition for AccType_UNPRIV.
105 * Therefore we should never get here with a mmu_idx for
106 * which we do not know the corresponding user mmu_idx.
109 case ARMMMUIdx_E10_1
:
110 case ARMMMUIdx_E10_1_PAN
:
111 useridx
= ARMMMUIdx_E10_0
;
113 case ARMMMUIdx_E20_2
:
114 case ARMMMUIdx_E20_2_PAN
:
115 useridx
= ARMMMUIdx_E20_0
;
117 case ARMMMUIdx_SE10_1
:
118 case ARMMMUIdx_SE10_1_PAN
:
119 useridx
= ARMMMUIdx_SE10_0
;
122 g_assert_not_reached();
125 return arm_to_core_mmu_idx(useridx
);
128 static void reset_btype(DisasContext
*s
)
131 TCGv_i32 zero
= tcg_const_i32(0);
132 tcg_gen_st_i32(zero
, cpu_env
, offsetof(CPUARMState
, btype
));
133 tcg_temp_free_i32(zero
);
138 static void set_btype(DisasContext
*s
, int val
)
142 /* BTYPE is a 2-bit field, and 0 should be done with reset_btype. */
143 tcg_debug_assert(val
>= 1 && val
<= 3);
145 tcg_val
= tcg_const_i32(val
);
146 tcg_gen_st_i32(tcg_val
, cpu_env
, offsetof(CPUARMState
, btype
));
147 tcg_temp_free_i32(tcg_val
);
151 void gen_a64_set_pc_im(uint64_t val
)
153 tcg_gen_movi_i64(cpu_pc
, val
);
157 * Handle Top Byte Ignore (TBI) bits.
159 * If address tagging is enabled via the TCR TBI bits:
160 * + for EL2 and EL3 there is only one TBI bit, and if it is set
161 * then the address is zero-extended, clearing bits [63:56]
162 * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
163 * and TBI1 controls addressses with bit 55 == 1.
164 * If the appropriate TBI bit is set for the address then
165 * the address is sign-extended from bit 55 into bits [63:56]
167 * Here We have concatenated TBI{1,0} into tbi.
169 static void gen_top_byte_ignore(DisasContext
*s
, TCGv_i64 dst
,
170 TCGv_i64 src
, int tbi
)
173 /* Load unmodified address */
174 tcg_gen_mov_i64(dst
, src
);
175 } else if (!regime_has_2_ranges(s
->mmu_idx
)) {
176 /* Force tag byte to all zero */
177 tcg_gen_extract_i64(dst
, src
, 0, 56);
179 /* Sign-extend from bit 55. */
180 tcg_gen_sextract_i64(dst
, src
, 0, 56);
183 TCGv_i64 tcg_zero
= tcg_const_i64(0);
186 * The two TBI bits differ.
187 * If tbi0, then !tbi1: only use the extension if positive.
188 * if !tbi0, then tbi1: only use the extension if negative.
190 tcg_gen_movcond_i64(tbi
== 1 ? TCG_COND_GE
: TCG_COND_LT
,
191 dst
, dst
, tcg_zero
, dst
, src
);
192 tcg_temp_free_i64(tcg_zero
);
197 static void gen_a64_set_pc(DisasContext
*s
, TCGv_i64 src
)
200 * If address tagging is enabled for instructions via the TCR TBI bits,
201 * then loading an address into the PC will clear out any tag.
203 gen_top_byte_ignore(s
, cpu_pc
, src
, s
->tbii
);
207 * Handle MTE and/or TBI.
209 * For TBI, ideally, we would do nothing. Proper behaviour on fault is
210 * for the tag to be present in the FAR_ELx register. But for user-only
211 * mode we do not have a TLB with which to implement this, so we must
212 * remove the top byte now.
214 * Always return a fresh temporary that we can increment independently
215 * of the write-back address.
218 TCGv_i64
clean_data_tbi(DisasContext
*s
, TCGv_i64 addr
)
220 TCGv_i64 clean
= new_tmp_a64(s
);
221 #ifdef CONFIG_USER_ONLY
222 gen_top_byte_ignore(s
, clean
, addr
, s
->tbid
);
224 tcg_gen_mov_i64(clean
, addr
);
229 /* Insert a zero tag into src, with the result at dst. */
230 static void gen_address_with_allocation_tag0(TCGv_i64 dst
, TCGv_i64 src
)
232 tcg_gen_andi_i64(dst
, src
, ~MAKE_64BIT_MASK(56, 4));
235 static void gen_probe_access(DisasContext
*s
, TCGv_i64 ptr
,
236 MMUAccessType acc
, int log2_size
)
238 TCGv_i32 t_acc
= tcg_const_i32(acc
);
239 TCGv_i32 t_idx
= tcg_const_i32(get_mem_index(s
));
240 TCGv_i32 t_size
= tcg_const_i32(1 << log2_size
);
242 gen_helper_probe_access(cpu_env
, ptr
, t_acc
, t_idx
, t_size
);
243 tcg_temp_free_i32(t_acc
);
244 tcg_temp_free_i32(t_idx
);
245 tcg_temp_free_i32(t_size
);
249 * For MTE, check a single logical or atomic access. This probes a single
250 * address, the exact one specified. The size and alignment of the access
251 * is not relevant to MTE, per se, but watchpoints do require the size,
252 * and we want to recognize those before making any other changes to state.
254 static TCGv_i64
gen_mte_check1_mmuidx(DisasContext
*s
, TCGv_i64 addr
,
255 bool is_write
, bool tag_checked
,
256 int log2_size
, bool is_unpriv
,
259 if (tag_checked
&& s
->mte_active
[is_unpriv
]) {
264 desc
= FIELD_DP32(desc
, MTEDESC
, MIDX
, core_idx
);
265 desc
= FIELD_DP32(desc
, MTEDESC
, TBI
, s
->tbid
);
266 desc
= FIELD_DP32(desc
, MTEDESC
, TCMA
, s
->tcma
);
267 desc
= FIELD_DP32(desc
, MTEDESC
, WRITE
, is_write
);
268 desc
= FIELD_DP32(desc
, MTEDESC
, ESIZE
, 1 << log2_size
);
269 tcg_desc
= tcg_const_i32(desc
);
271 ret
= new_tmp_a64(s
);
272 gen_helper_mte_check1(ret
, cpu_env
, tcg_desc
, addr
);
273 tcg_temp_free_i32(tcg_desc
);
277 return clean_data_tbi(s
, addr
);
280 TCGv_i64
gen_mte_check1(DisasContext
*s
, TCGv_i64 addr
, bool is_write
,
281 bool tag_checked
, int log2_size
)
283 return gen_mte_check1_mmuidx(s
, addr
, is_write
, tag_checked
, log2_size
,
284 false, get_mem_index(s
));
288 * For MTE, check multiple logical sequential accesses.
290 TCGv_i64
gen_mte_checkN(DisasContext
*s
, TCGv_i64 addr
, bool is_write
,
291 bool tag_checked
, int log2_esize
, int total_size
)
293 if (tag_checked
&& s
->mte_active
[0] && total_size
!= (1 << log2_esize
)) {
298 desc
= FIELD_DP32(desc
, MTEDESC
, MIDX
, get_mem_index(s
));
299 desc
= FIELD_DP32(desc
, MTEDESC
, TBI
, s
->tbid
);
300 desc
= FIELD_DP32(desc
, MTEDESC
, TCMA
, s
->tcma
);
301 desc
= FIELD_DP32(desc
, MTEDESC
, WRITE
, is_write
);
302 desc
= FIELD_DP32(desc
, MTEDESC
, ESIZE
, 1 << log2_esize
);
303 desc
= FIELD_DP32(desc
, MTEDESC
, TSIZE
, total_size
);
304 tcg_desc
= tcg_const_i32(desc
);
306 ret
= new_tmp_a64(s
);
307 gen_helper_mte_checkN(ret
, cpu_env
, tcg_desc
, addr
);
308 tcg_temp_free_i32(tcg_desc
);
312 return gen_mte_check1(s
, addr
, is_write
, tag_checked
, log2_esize
);
315 typedef struct DisasCompare64
{
320 static void a64_test_cc(DisasCompare64
*c64
, int cc
)
324 arm_test_cc(&c32
, cc
);
326 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
327 * properly. The NE/EQ comparisons are also fine with this choice. */
328 c64
->cond
= c32
.cond
;
329 c64
->value
= tcg_temp_new_i64();
330 tcg_gen_ext_i32_i64(c64
->value
, c32
.value
);
335 static void a64_free_cc(DisasCompare64
*c64
)
337 tcg_temp_free_i64(c64
->value
);
340 static void gen_exception_internal(int excp
)
342 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
344 assert(excp_is_internal(excp
));
345 gen_helper_exception_internal(cpu_env
, tcg_excp
);
346 tcg_temp_free_i32(tcg_excp
);
349 static void gen_exception_internal_insn(DisasContext
*s
, uint64_t pc
, int excp
)
351 gen_a64_set_pc_im(pc
);
352 gen_exception_internal(excp
);
353 s
->base
.is_jmp
= DISAS_NORETURN
;
356 static void gen_exception_insn(DisasContext
*s
, uint64_t pc
, int excp
,
357 uint32_t syndrome
, uint32_t target_el
)
359 gen_a64_set_pc_im(pc
);
360 gen_exception(excp
, syndrome
, target_el
);
361 s
->base
.is_jmp
= DISAS_NORETURN
;
364 static void gen_exception_bkpt_insn(DisasContext
*s
, uint32_t syndrome
)
368 gen_a64_set_pc_im(s
->pc_curr
);
369 tcg_syn
= tcg_const_i32(syndrome
);
370 gen_helper_exception_bkpt_insn(cpu_env
, tcg_syn
);
371 tcg_temp_free_i32(tcg_syn
);
372 s
->base
.is_jmp
= DISAS_NORETURN
;
375 static void gen_step_complete_exception(DisasContext
*s
)
377 /* We just completed step of an insn. Move from Active-not-pending
378 * to Active-pending, and then also take the swstep exception.
379 * This corresponds to making the (IMPDEF) choice to prioritize
380 * swstep exceptions over asynchronous exceptions taken to an exception
381 * level where debug is disabled. This choice has the advantage that
382 * we do not need to maintain internal state corresponding to the
383 * ISV/EX syndrome bits between completion of the step and generation
384 * of the exception, and our syndrome information is always correct.
387 gen_swstep_exception(s
, 1, s
->is_ldex
);
388 s
->base
.is_jmp
= DISAS_NORETURN
;
391 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
393 /* No direct tb linking with singlestep (either QEMU's or the ARM
394 * debug architecture kind) or deterministic io
396 if (s
->base
.singlestep_enabled
|| s
->ss_active
||
397 (tb_cflags(s
->base
.tb
) & CF_LAST_IO
)) {
401 #ifndef CONFIG_USER_ONLY
402 /* Only link tbs from inside the same guest page */
403 if ((s
->base
.tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
411 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
413 TranslationBlock
*tb
;
416 if (use_goto_tb(s
, n
, dest
)) {
418 gen_a64_set_pc_im(dest
);
419 tcg_gen_exit_tb(tb
, n
);
420 s
->base
.is_jmp
= DISAS_NORETURN
;
422 gen_a64_set_pc_im(dest
);
424 gen_step_complete_exception(s
);
425 } else if (s
->base
.singlestep_enabled
) {
426 gen_exception_internal(EXCP_DEBUG
);
428 tcg_gen_lookup_and_goto_ptr();
429 s
->base
.is_jmp
= DISAS_NORETURN
;
434 void unallocated_encoding(DisasContext
*s
)
436 /* Unallocated and reserved encodings are uncategorized */
437 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
, syn_uncategorized(),
438 default_exception_el(s
));
441 static void init_tmp_a64_array(DisasContext
*s
)
443 #ifdef CONFIG_DEBUG_TCG
444 memset(s
->tmp_a64
, 0, sizeof(s
->tmp_a64
));
446 s
->tmp_a64_count
= 0;
449 static void free_tmp_a64(DisasContext
*s
)
452 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
453 tcg_temp_free_i64(s
->tmp_a64
[i
]);
455 init_tmp_a64_array(s
);
458 TCGv_i64
new_tmp_a64(DisasContext
*s
)
460 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
461 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
464 TCGv_i64
new_tmp_a64_local(DisasContext
*s
)
466 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
467 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_local_new_i64();
470 TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
472 TCGv_i64 t
= new_tmp_a64(s
);
473 tcg_gen_movi_i64(t
, 0);
478 * Register access functions
480 * These functions are used for directly accessing a register in where
481 * changes to the final register value are likely to be made. If you
482 * need to use a register for temporary calculation (e.g. index type
483 * operations) use the read_* form.
485 * B1.2.1 Register mappings
487 * In instruction register encoding 31 can refer to ZR (zero register) or
488 * the SP (stack pointer) depending on context. In QEMU's case we map SP
489 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
490 * This is the point of the _sp forms.
492 TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
495 return new_tmp_a64_zero(s
);
501 /* register access for when 31 == SP */
502 TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
507 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
508 * representing the register contents. This TCGv is an auto-freed
509 * temporary so it need not be explicitly freed, and may be modified.
511 TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
513 TCGv_i64 v
= new_tmp_a64(s
);
516 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
518 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
521 tcg_gen_movi_i64(v
, 0);
526 TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
528 TCGv_i64 v
= new_tmp_a64(s
);
530 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
532 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
537 /* Return the offset into CPUARMState of a slice (from
538 * the least significant end) of FP register Qn (ie
540 * (Note that this is not the same mapping as for A32; see cpu.h)
542 static inline int fp_reg_offset(DisasContext
*s
, int regno
, MemOp size
)
544 return vec_reg_offset(s
, regno
, 0, size
);
547 /* Offset of the high half of the 128 bit vector Qn */
548 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
550 return vec_reg_offset(s
, regno
, 1, MO_64
);
553 /* Convenience accessors for reading and writing single and double
554 * FP registers. Writing clears the upper parts of the associated
555 * 128 bit vector register, as required by the architecture.
556 * Note that unlike the GP register accessors, the values returned
557 * by the read functions must be manually freed.
559 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
561 TCGv_i64 v
= tcg_temp_new_i64();
563 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
567 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
569 TCGv_i32 v
= tcg_temp_new_i32();
571 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
575 static TCGv_i32
read_fp_hreg(DisasContext
*s
, int reg
)
577 TCGv_i32 v
= tcg_temp_new_i32();
579 tcg_gen_ld16u_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_16
));
583 /* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
584 * If SVE is not enabled, then there are only 128 bits in the vector.
586 static void clear_vec_high(DisasContext
*s
, bool is_q
, int rd
)
588 unsigned ofs
= fp_reg_offset(s
, rd
, MO_64
);
589 unsigned vsz
= vec_full_reg_size(s
);
591 /* Nop move, with side effect of clearing the tail. */
592 tcg_gen_gvec_mov(MO_64
, ofs
, ofs
, is_q
? 16 : 8, vsz
);
595 void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
597 unsigned ofs
= fp_reg_offset(s
, reg
, MO_64
);
599 tcg_gen_st_i64(v
, cpu_env
, ofs
);
600 clear_vec_high(s
, false, reg
);
603 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
605 TCGv_i64 tmp
= tcg_temp_new_i64();
607 tcg_gen_extu_i32_i64(tmp
, v
);
608 write_fp_dreg(s
, reg
, tmp
);
609 tcg_temp_free_i64(tmp
);
612 TCGv_ptr
get_fpstatus_ptr(bool is_f16
)
614 TCGv_ptr statusptr
= tcg_temp_new_ptr();
617 /* In A64 all instructions (both FP and Neon) use the FPCR; there
618 * is no equivalent of the A32 Neon "standard FPSCR value".
619 * However half-precision operations operate under a different
620 * FZ16 flag and use vfp.fp_status_f16 instead of vfp.fp_status.
623 offset
= offsetof(CPUARMState
, vfp
.fp_status_f16
);
625 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
627 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
631 /* Expand a 2-operand AdvSIMD vector operation using an expander function. */
632 static void gen_gvec_fn2(DisasContext
*s
, bool is_q
, int rd
, int rn
,
633 GVecGen2Fn
*gvec_fn
, int vece
)
635 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
636 is_q
? 16 : 8, vec_full_reg_size(s
));
639 /* Expand a 2-operand + immediate AdvSIMD vector operation using
640 * an expander function.
642 static void gen_gvec_fn2i(DisasContext
*s
, bool is_q
, int rd
, int rn
,
643 int64_t imm
, GVecGen2iFn
*gvec_fn
, int vece
)
645 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
646 imm
, is_q
? 16 : 8, vec_full_reg_size(s
));
649 /* Expand a 3-operand AdvSIMD vector operation using an expander function. */
650 static void gen_gvec_fn3(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
651 GVecGen3Fn
*gvec_fn
, int vece
)
653 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
654 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8, vec_full_reg_size(s
));
657 /* Expand a 4-operand AdvSIMD vector operation using an expander function. */
658 static void gen_gvec_fn4(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
659 int rx
, GVecGen4Fn
*gvec_fn
, int vece
)
661 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
662 vec_full_reg_offset(s
, rm
), vec_full_reg_offset(s
, rx
),
663 is_q
? 16 : 8, vec_full_reg_size(s
));
666 /* Expand a 2-operand operation using an out-of-line helper. */
667 static void gen_gvec_op2_ool(DisasContext
*s
, bool is_q
, int rd
,
668 int rn
, int data
, gen_helper_gvec_2
*fn
)
670 tcg_gen_gvec_2_ool(vec_full_reg_offset(s
, rd
),
671 vec_full_reg_offset(s
, rn
),
672 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
675 /* Expand a 3-operand operation using an out-of-line helper. */
676 static void gen_gvec_op3_ool(DisasContext
*s
, bool is_q
, int rd
,
677 int rn
, int rm
, int data
, gen_helper_gvec_3
*fn
)
679 tcg_gen_gvec_3_ool(vec_full_reg_offset(s
, rd
),
680 vec_full_reg_offset(s
, rn
),
681 vec_full_reg_offset(s
, rm
),
682 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
685 /* Expand a 3-operand + fpstatus pointer + simd data value operation using
686 * an out-of-line helper.
688 static void gen_gvec_op3_fpst(DisasContext
*s
, bool is_q
, int rd
, int rn
,
689 int rm
, bool is_fp16
, int data
,
690 gen_helper_gvec_3_ptr
*fn
)
692 TCGv_ptr fpst
= get_fpstatus_ptr(is_fp16
);
693 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
694 vec_full_reg_offset(s
, rn
),
695 vec_full_reg_offset(s
, rm
), fpst
,
696 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
697 tcg_temp_free_ptr(fpst
);
700 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
701 * than the 32 bit equivalent.
703 static inline void gen_set_NZ64(TCGv_i64 result
)
705 tcg_gen_extr_i64_i32(cpu_ZF
, cpu_NF
, result
);
706 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, cpu_NF
);
709 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
710 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
713 gen_set_NZ64(result
);
715 tcg_gen_extrl_i64_i32(cpu_ZF
, result
);
716 tcg_gen_mov_i32(cpu_NF
, cpu_ZF
);
718 tcg_gen_movi_i32(cpu_CF
, 0);
719 tcg_gen_movi_i32(cpu_VF
, 0);
722 /* dest = T0 + T1; compute C, N, V and Z flags */
723 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
726 TCGv_i64 result
, flag
, tmp
;
727 result
= tcg_temp_new_i64();
728 flag
= tcg_temp_new_i64();
729 tmp
= tcg_temp_new_i64();
731 tcg_gen_movi_i64(tmp
, 0);
732 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
734 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
736 gen_set_NZ64(result
);
738 tcg_gen_xor_i64(flag
, result
, t0
);
739 tcg_gen_xor_i64(tmp
, t0
, t1
);
740 tcg_gen_andc_i64(flag
, flag
, tmp
);
741 tcg_temp_free_i64(tmp
);
742 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
744 tcg_gen_mov_i64(dest
, result
);
745 tcg_temp_free_i64(result
);
746 tcg_temp_free_i64(flag
);
748 /* 32 bit arithmetic */
749 TCGv_i32 t0_32
= tcg_temp_new_i32();
750 TCGv_i32 t1_32
= tcg_temp_new_i32();
751 TCGv_i32 tmp
= tcg_temp_new_i32();
753 tcg_gen_movi_i32(tmp
, 0);
754 tcg_gen_extrl_i64_i32(t0_32
, t0
);
755 tcg_gen_extrl_i64_i32(t1_32
, t1
);
756 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
757 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
758 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
759 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
760 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
761 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
763 tcg_temp_free_i32(tmp
);
764 tcg_temp_free_i32(t0_32
);
765 tcg_temp_free_i32(t1_32
);
769 /* dest = T0 - T1; compute C, N, V and Z flags */
770 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
773 /* 64 bit arithmetic */
774 TCGv_i64 result
, flag
, tmp
;
776 result
= tcg_temp_new_i64();
777 flag
= tcg_temp_new_i64();
778 tcg_gen_sub_i64(result
, t0
, t1
);
780 gen_set_NZ64(result
);
782 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
783 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
785 tcg_gen_xor_i64(flag
, result
, t0
);
786 tmp
= tcg_temp_new_i64();
787 tcg_gen_xor_i64(tmp
, t0
, t1
);
788 tcg_gen_and_i64(flag
, flag
, tmp
);
789 tcg_temp_free_i64(tmp
);
790 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
791 tcg_gen_mov_i64(dest
, result
);
792 tcg_temp_free_i64(flag
);
793 tcg_temp_free_i64(result
);
795 /* 32 bit arithmetic */
796 TCGv_i32 t0_32
= tcg_temp_new_i32();
797 TCGv_i32 t1_32
= tcg_temp_new_i32();
800 tcg_gen_extrl_i64_i32(t0_32
, t0
);
801 tcg_gen_extrl_i64_i32(t1_32
, t1
);
802 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
803 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
804 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
805 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
806 tmp
= tcg_temp_new_i32();
807 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
808 tcg_temp_free_i32(t0_32
);
809 tcg_temp_free_i32(t1_32
);
810 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
811 tcg_temp_free_i32(tmp
);
812 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
816 /* dest = T0 + T1 + CF; do not compute flags. */
817 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
819 TCGv_i64 flag
= tcg_temp_new_i64();
820 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
821 tcg_gen_add_i64(dest
, t0
, t1
);
822 tcg_gen_add_i64(dest
, dest
, flag
);
823 tcg_temp_free_i64(flag
);
826 tcg_gen_ext32u_i64(dest
, dest
);
830 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
831 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
834 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
835 result
= tcg_temp_new_i64();
836 cf_64
= tcg_temp_new_i64();
837 vf_64
= tcg_temp_new_i64();
838 tmp
= tcg_const_i64(0);
840 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
841 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
842 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
843 tcg_gen_extrl_i64_i32(cpu_CF
, cf_64
);
844 gen_set_NZ64(result
);
846 tcg_gen_xor_i64(vf_64
, result
, t0
);
847 tcg_gen_xor_i64(tmp
, t0
, t1
);
848 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
849 tcg_gen_extrh_i64_i32(cpu_VF
, vf_64
);
851 tcg_gen_mov_i64(dest
, result
);
853 tcg_temp_free_i64(tmp
);
854 tcg_temp_free_i64(vf_64
);
855 tcg_temp_free_i64(cf_64
);
856 tcg_temp_free_i64(result
);
858 TCGv_i32 t0_32
, t1_32
, tmp
;
859 t0_32
= tcg_temp_new_i32();
860 t1_32
= tcg_temp_new_i32();
861 tmp
= tcg_const_i32(0);
863 tcg_gen_extrl_i64_i32(t0_32
, t0
);
864 tcg_gen_extrl_i64_i32(t1_32
, t1
);
865 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
866 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
868 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
869 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
870 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
871 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
872 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
874 tcg_temp_free_i32(tmp
);
875 tcg_temp_free_i32(t1_32
);
876 tcg_temp_free_i32(t0_32
);
881 * Load/Store generators
885 * Store from GPR register to memory.
887 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
888 TCGv_i64 tcg_addr
, int size
, int memidx
,
890 unsigned int iss_srt
,
891 bool iss_sf
, bool iss_ar
)
894 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, s
->be_data
+ size
);
899 syn
= syn_data_abort_with_iss(0,
905 0, 0, 0, 0, 0, false);
906 disas_set_insn_syndrome(s
, syn
);
910 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
911 TCGv_i64 tcg_addr
, int size
,
913 unsigned int iss_srt
,
914 bool iss_sf
, bool iss_ar
)
916 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
),
917 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
921 * Load from memory to GPR register
923 static void do_gpr_ld_memidx(DisasContext
*s
,
924 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
925 int size
, bool is_signed
,
926 bool extend
, int memidx
,
927 bool iss_valid
, unsigned int iss_srt
,
928 bool iss_sf
, bool iss_ar
)
930 MemOp memop
= s
->be_data
+ size
;
938 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
940 if (extend
&& is_signed
) {
942 tcg_gen_ext32u_i64(dest
, dest
);
948 syn
= syn_data_abort_with_iss(0,
954 0, 0, 0, 0, 0, false);
955 disas_set_insn_syndrome(s
, syn
);
959 static void do_gpr_ld(DisasContext
*s
,
960 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
961 int size
, bool is_signed
, bool extend
,
962 bool iss_valid
, unsigned int iss_srt
,
963 bool iss_sf
, bool iss_ar
)
965 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
967 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
971 * Store from FP register to memory
973 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
975 /* This writes the bottom N bits of a 128 bit wide vector to memory */
976 TCGv_i64 tmp
= tcg_temp_new_i64();
977 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
979 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
),
982 bool be
= s
->be_data
== MO_BE
;
983 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
985 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
986 tcg_gen_qemu_st_i64(tmp
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
988 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
989 tcg_gen_qemu_st_i64(tmp
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
991 tcg_temp_free_i64(tcg_hiaddr
);
994 tcg_temp_free_i64(tmp
);
998 * Load from memory to FP register
1000 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
1002 /* This always zero-extends and writes to a full 128 bit wide vector */
1003 TCGv_i64 tmplo
= tcg_temp_new_i64();
1004 TCGv_i64 tmphi
= NULL
;
1007 MemOp memop
= s
->be_data
+ size
;
1008 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
1010 bool be
= s
->be_data
== MO_BE
;
1011 TCGv_i64 tcg_hiaddr
;
1013 tmphi
= tcg_temp_new_i64();
1014 tcg_hiaddr
= tcg_temp_new_i64();
1016 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
1017 tcg_gen_qemu_ld_i64(tmplo
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
1019 tcg_gen_qemu_ld_i64(tmphi
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
1021 tcg_temp_free_i64(tcg_hiaddr
);
1024 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
1025 tcg_temp_free_i64(tmplo
);
1028 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
1029 tcg_temp_free_i64(tmphi
);
1031 clear_vec_high(s
, tmphi
!= NULL
, destidx
);
1035 * Vector load/store helpers.
1037 * The principal difference between this and a FP load is that we don't
1038 * zero extend as we are filling a partial chunk of the vector register.
1039 * These functions don't support 128 bit loads/stores, which would be
1040 * normal load/store operations.
1042 * The _i32 versions are useful when operating on 32 bit quantities
1043 * (eg for floating point single or using Neon helper functions).
1046 /* Get value of an element within a vector register */
1047 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
1048 int element
, MemOp memop
)
1050 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1053 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
1056 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
1059 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
1062 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
1065 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
1068 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
1072 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
1075 g_assert_not_reached();
1079 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
1080 int element
, MemOp memop
)
1082 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1085 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
1088 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
1091 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
1094 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
1098 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
1101 g_assert_not_reached();
1105 /* Set value of an element within a vector register */
1106 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
1107 int element
, MemOp memop
)
1109 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1112 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
1115 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
1118 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
1121 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
1124 g_assert_not_reached();
1128 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
1129 int destidx
, int element
, MemOp memop
)
1131 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1134 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
1137 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
1140 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
1143 g_assert_not_reached();
1147 /* Store from vector register to memory */
1148 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
1149 TCGv_i64 tcg_addr
, int size
, MemOp endian
)
1151 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1153 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
1154 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), endian
| size
);
1156 tcg_temp_free_i64(tcg_tmp
);
1159 /* Load from memory to vector register */
1160 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
1161 TCGv_i64 tcg_addr
, int size
, MemOp endian
)
1163 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1165 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), endian
| size
);
1166 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
1168 tcg_temp_free_i64(tcg_tmp
);
1171 /* Check that FP/Neon access is enabled. If it is, return
1172 * true. If not, emit code to generate an appropriate exception,
1173 * and return false; the caller should not emit any code for
1174 * the instruction. Note that this check must happen after all
1175 * unallocated-encoding checks (otherwise the syndrome information
1176 * for the resulting exception will be incorrect).
1178 static inline bool fp_access_check(DisasContext
*s
)
1180 assert(!s
->fp_access_checked
);
1181 s
->fp_access_checked
= true;
1183 if (!s
->fp_excp_el
) {
1187 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
1188 syn_fp_access_trap(1, 0xe, false), s
->fp_excp_el
);
1192 /* Check that SVE access is enabled. If it is, return true.
1193 * If not, emit code to generate an appropriate exception and return false.
1195 bool sve_access_check(DisasContext
*s
)
1197 if (s
->sve_excp_el
) {
1198 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
, syn_sve_access_trap(),
1202 return fp_access_check(s
);
1206 * This utility function is for doing register extension with an
1207 * optional shift. You will likely want to pass a temporary for the
1208 * destination register. See DecodeRegExtend() in the ARM ARM.
1210 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
1211 int option
, unsigned int shift
)
1213 int extsize
= extract32(option
, 0, 2);
1214 bool is_signed
= extract32(option
, 2, 1);
1219 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
1222 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
1225 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1228 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1234 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1237 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1240 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1243 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1249 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1253 static inline void gen_check_sp_alignment(DisasContext
*s
)
1255 /* The AArch64 architecture mandates that (if enabled via PSTATE
1256 * or SCTLR bits) there is a check that SP is 16-aligned on every
1257 * SP-relative load or store (with an exception generated if it is not).
1258 * In line with general QEMU practice regarding misaligned accesses,
1259 * we omit these checks for the sake of guest program performance.
1260 * This function is provided as a hook so we can more easily add these
1261 * checks in future (possibly as a "favour catching guest program bugs
1262 * over speed" user selectable option).
1267 * This provides a simple table based table lookup decoder. It is
1268 * intended to be used when the relevant bits for decode are too
1269 * awkwardly placed and switch/if based logic would be confusing and
1270 * deeply nested. Since it's a linear search through the table, tables
1271 * should be kept small.
1273 * It returns the first handler where insn & mask == pattern, or
1274 * NULL if there is no match.
1275 * The table is terminated by an empty mask (i.e. 0)
1277 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1280 const AArch64DecodeTable
*tptr
= table
;
1282 while (tptr
->mask
) {
1283 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1284 return tptr
->disas_fn
;
1292 * The instruction disassembly implemented here matches
1293 * the instruction encoding classifications in chapter C4
1294 * of the ARM Architecture Reference Manual (DDI0487B_a);
1295 * classification names and decode diagrams here should generally
1296 * match up with those in the manual.
1299 /* Unconditional branch (immediate)
1301 * +----+-----------+-------------------------------------+
1302 * | op | 0 0 1 0 1 | imm26 |
1303 * +----+-----------+-------------------------------------+
1305 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1307 uint64_t addr
= s
->pc_curr
+ sextract32(insn
, 0, 26) * 4;
1309 if (insn
& (1U << 31)) {
1310 /* BL Branch with link */
1311 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
1314 /* B Branch / BL Branch with link */
1316 gen_goto_tb(s
, 0, addr
);
1319 /* Compare and branch (immediate)
1320 * 31 30 25 24 23 5 4 0
1321 * +----+-------------+----+---------------------+--------+
1322 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1323 * +----+-------------+----+---------------------+--------+
1325 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1327 unsigned int sf
, op
, rt
;
1329 TCGLabel
*label_match
;
1332 sf
= extract32(insn
, 31, 1);
1333 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1334 rt
= extract32(insn
, 0, 5);
1335 addr
= s
->pc_curr
+ sextract32(insn
, 5, 19) * 4;
1337 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1338 label_match
= gen_new_label();
1341 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1342 tcg_cmp
, 0, label_match
);
1344 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1345 gen_set_label(label_match
);
1346 gen_goto_tb(s
, 1, addr
);
1349 /* Test and branch (immediate)
1350 * 31 30 25 24 23 19 18 5 4 0
1351 * +----+-------------+----+-------+-------------+------+
1352 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1353 * +----+-------------+----+-------+-------------+------+
1355 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1357 unsigned int bit_pos
, op
, rt
;
1359 TCGLabel
*label_match
;
1362 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1363 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1364 addr
= s
->pc_curr
+ sextract32(insn
, 5, 14) * 4;
1365 rt
= extract32(insn
, 0, 5);
1367 tcg_cmp
= tcg_temp_new_i64();
1368 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1369 label_match
= gen_new_label();
1372 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1373 tcg_cmp
, 0, label_match
);
1374 tcg_temp_free_i64(tcg_cmp
);
1375 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1376 gen_set_label(label_match
);
1377 gen_goto_tb(s
, 1, addr
);
1380 /* Conditional branch (immediate)
1381 * 31 25 24 23 5 4 3 0
1382 * +---------------+----+---------------------+----+------+
1383 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1384 * +---------------+----+---------------------+----+------+
1386 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1391 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1392 unallocated_encoding(s
);
1395 addr
= s
->pc_curr
+ sextract32(insn
, 5, 19) * 4;
1396 cond
= extract32(insn
, 0, 4);
1400 /* genuinely conditional branches */
1401 TCGLabel
*label_match
= gen_new_label();
1402 arm_gen_test_cc(cond
, label_match
);
1403 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1404 gen_set_label(label_match
);
1405 gen_goto_tb(s
, 1, addr
);
1407 /* 0xe and 0xf are both "always" conditions */
1408 gen_goto_tb(s
, 0, addr
);
1412 /* HINT instruction group, including various allocated HINTs */
1413 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1414 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1416 unsigned int selector
= crm
<< 3 | op2
;
1419 unallocated_encoding(s
);
1424 case 0b00000: /* NOP */
1426 case 0b00011: /* WFI */
1427 s
->base
.is_jmp
= DISAS_WFI
;
1429 case 0b00001: /* YIELD */
1430 /* When running in MTTCG we don't generate jumps to the yield and
1431 * WFE helpers as it won't affect the scheduling of other vCPUs.
1432 * If we wanted to more completely model WFE/SEV so we don't busy
1433 * spin unnecessarily we would need to do something more involved.
1435 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1436 s
->base
.is_jmp
= DISAS_YIELD
;
1439 case 0b00010: /* WFE */
1440 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1441 s
->base
.is_jmp
= DISAS_WFE
;
1444 case 0b00100: /* SEV */
1445 case 0b00101: /* SEVL */
1446 /* we treat all as NOP at least for now */
1448 case 0b00111: /* XPACLRI */
1449 if (s
->pauth_active
) {
1450 gen_helper_xpaci(cpu_X
[30], cpu_env
, cpu_X
[30]);
1453 case 0b01000: /* PACIA1716 */
1454 if (s
->pauth_active
) {
1455 gen_helper_pacia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1458 case 0b01010: /* PACIB1716 */
1459 if (s
->pauth_active
) {
1460 gen_helper_pacib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1463 case 0b01100: /* AUTIA1716 */
1464 if (s
->pauth_active
) {
1465 gen_helper_autia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1468 case 0b01110: /* AUTIB1716 */
1469 if (s
->pauth_active
) {
1470 gen_helper_autib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1473 case 0b11000: /* PACIAZ */
1474 if (s
->pauth_active
) {
1475 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30],
1476 new_tmp_a64_zero(s
));
1479 case 0b11001: /* PACIASP */
1480 if (s
->pauth_active
) {
1481 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1484 case 0b11010: /* PACIBZ */
1485 if (s
->pauth_active
) {
1486 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30],
1487 new_tmp_a64_zero(s
));
1490 case 0b11011: /* PACIBSP */
1491 if (s
->pauth_active
) {
1492 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1495 case 0b11100: /* AUTIAZ */
1496 if (s
->pauth_active
) {
1497 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30],
1498 new_tmp_a64_zero(s
));
1501 case 0b11101: /* AUTIASP */
1502 if (s
->pauth_active
) {
1503 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1506 case 0b11110: /* AUTIBZ */
1507 if (s
->pauth_active
) {
1508 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30],
1509 new_tmp_a64_zero(s
));
1512 case 0b11111: /* AUTIBSP */
1513 if (s
->pauth_active
) {
1514 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1518 /* default specified as NOP equivalent */
1523 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1525 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1528 /* CLREX, DSB, DMB, ISB */
1529 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1530 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1535 unallocated_encoding(s
);
1546 case 1: /* MBReqTypes_Reads */
1547 bar
= TCG_BAR_SC
| TCG_MO_LD_LD
| TCG_MO_LD_ST
;
1549 case 2: /* MBReqTypes_Writes */
1550 bar
= TCG_BAR_SC
| TCG_MO_ST_ST
;
1552 default: /* MBReqTypes_All */
1553 bar
= TCG_BAR_SC
| TCG_MO_ALL
;
1559 /* We need to break the TB after this insn to execute
1560 * a self-modified code correctly and also to take
1561 * any pending interrupts immediately.
1564 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1568 if (crm
!= 0 || !dc_isar_feature(aa64_sb
, s
)) {
1569 goto do_unallocated
;
1572 * TODO: There is no speculation barrier opcode for TCG;
1573 * MB and end the TB instead.
1575 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
1576 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1581 unallocated_encoding(s
);
1586 static void gen_xaflag(void)
1588 TCGv_i32 z
= tcg_temp_new_i32();
1590 tcg_gen_setcondi_i32(TCG_COND_EQ
, z
, cpu_ZF
, 0);
1599 tcg_gen_or_i32(cpu_NF
, cpu_CF
, z
);
1600 tcg_gen_subi_i32(cpu_NF
, cpu_NF
, 1);
1603 tcg_gen_and_i32(cpu_ZF
, z
, cpu_CF
);
1604 tcg_gen_xori_i32(cpu_ZF
, cpu_ZF
, 1);
1606 /* (!C & Z) << 31 -> -(Z & ~C) */
1607 tcg_gen_andc_i32(cpu_VF
, z
, cpu_CF
);
1608 tcg_gen_neg_i32(cpu_VF
, cpu_VF
);
1611 tcg_gen_or_i32(cpu_CF
, cpu_CF
, z
);
1613 tcg_temp_free_i32(z
);
1616 static void gen_axflag(void)
1618 tcg_gen_sari_i32(cpu_VF
, cpu_VF
, 31); /* V ? -1 : 0 */
1619 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, cpu_VF
); /* C & !V */
1621 /* !(Z | V) -> !(!ZF | V) -> ZF & !V -> ZF & ~VF */
1622 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, cpu_VF
);
1624 tcg_gen_movi_i32(cpu_NF
, 0);
1625 tcg_gen_movi_i32(cpu_VF
, 0);
1628 /* MSR (immediate) - move immediate to processor state field */
1629 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1630 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1633 int op
= op1
<< 3 | op2
;
1635 /* End the TB by default, chaining is ok. */
1636 s
->base
.is_jmp
= DISAS_TOO_MANY
;
1639 case 0x00: /* CFINV */
1640 if (crm
!= 0 || !dc_isar_feature(aa64_condm_4
, s
)) {
1641 goto do_unallocated
;
1643 tcg_gen_xori_i32(cpu_CF
, cpu_CF
, 1);
1644 s
->base
.is_jmp
= DISAS_NEXT
;
1647 case 0x01: /* XAFlag */
1648 if (crm
!= 0 || !dc_isar_feature(aa64_condm_5
, s
)) {
1649 goto do_unallocated
;
1652 s
->base
.is_jmp
= DISAS_NEXT
;
1655 case 0x02: /* AXFlag */
1656 if (crm
!= 0 || !dc_isar_feature(aa64_condm_5
, s
)) {
1657 goto do_unallocated
;
1660 s
->base
.is_jmp
= DISAS_NEXT
;
1663 case 0x03: /* UAO */
1664 if (!dc_isar_feature(aa64_uao
, s
) || s
->current_el
== 0) {
1665 goto do_unallocated
;
1668 set_pstate_bits(PSTATE_UAO
);
1670 clear_pstate_bits(PSTATE_UAO
);
1672 t1
= tcg_const_i32(s
->current_el
);
1673 gen_helper_rebuild_hflags_a64(cpu_env
, t1
);
1674 tcg_temp_free_i32(t1
);
1677 case 0x04: /* PAN */
1678 if (!dc_isar_feature(aa64_pan
, s
) || s
->current_el
== 0) {
1679 goto do_unallocated
;
1682 set_pstate_bits(PSTATE_PAN
);
1684 clear_pstate_bits(PSTATE_PAN
);
1686 t1
= tcg_const_i32(s
->current_el
);
1687 gen_helper_rebuild_hflags_a64(cpu_env
, t1
);
1688 tcg_temp_free_i32(t1
);
1691 case 0x05: /* SPSel */
1692 if (s
->current_el
== 0) {
1693 goto do_unallocated
;
1695 t1
= tcg_const_i32(crm
& PSTATE_SP
);
1696 gen_helper_msr_i_spsel(cpu_env
, t1
);
1697 tcg_temp_free_i32(t1
);
1700 case 0x1e: /* DAIFSet */
1701 t1
= tcg_const_i32(crm
);
1702 gen_helper_msr_i_daifset(cpu_env
, t1
);
1703 tcg_temp_free_i32(t1
);
1706 case 0x1f: /* DAIFClear */
1707 t1
= tcg_const_i32(crm
);
1708 gen_helper_msr_i_daifclear(cpu_env
, t1
);
1709 tcg_temp_free_i32(t1
);
1710 /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
1711 s
->base
.is_jmp
= DISAS_UPDATE_EXIT
;
1714 case 0x1c: /* TCO */
1715 if (dc_isar_feature(aa64_mte
, s
)) {
1716 /* Full MTE is enabled -- set the TCO bit as directed. */
1718 set_pstate_bits(PSTATE_TCO
);
1720 clear_pstate_bits(PSTATE_TCO
);
1722 t1
= tcg_const_i32(s
->current_el
);
1723 gen_helper_rebuild_hflags_a64(cpu_env
, t1
);
1724 tcg_temp_free_i32(t1
);
1725 /* Many factors, including TCO, go into MTE_ACTIVE. */
1726 s
->base
.is_jmp
= DISAS_UPDATE_NOCHAIN
;
1727 } else if (dc_isar_feature(aa64_mte_insn_reg
, s
)) {
1728 /* Only "instructions accessible at EL0" -- PSTATE.TCO is WI. */
1729 s
->base
.is_jmp
= DISAS_NEXT
;
1731 goto do_unallocated
;
1737 unallocated_encoding(s
);
1742 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1744 TCGv_i32 tmp
= tcg_temp_new_i32();
1745 TCGv_i32 nzcv
= tcg_temp_new_i32();
1747 /* build bit 31, N */
1748 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1749 /* build bit 30, Z */
1750 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1751 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1752 /* build bit 29, C */
1753 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1754 /* build bit 28, V */
1755 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1756 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1757 /* generate result */
1758 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1760 tcg_temp_free_i32(nzcv
);
1761 tcg_temp_free_i32(tmp
);
1764 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1766 TCGv_i32 nzcv
= tcg_temp_new_i32();
1768 /* take NZCV from R[t] */
1769 tcg_gen_extrl_i64_i32(nzcv
, tcg_rt
);
1772 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1774 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1775 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1777 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1778 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1780 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1781 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1782 tcg_temp_free_i32(nzcv
);
1785 /* MRS - move from system register
1786 * MSR (register) - move to system register
1789 * These are all essentially the same insn in 'read' and 'write'
1790 * versions, with varying op0 fields.
1792 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1793 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1794 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1796 const ARMCPRegInfo
*ri
;
1799 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1800 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1801 crn
, crm
, op0
, op1
, op2
));
1804 /* Unknown register; this might be a guest error or a QEMU
1805 * unimplemented feature.
1807 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1808 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1809 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1810 unallocated_encoding(s
);
1814 /* Check access permissions */
1815 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1816 unallocated_encoding(s
);
1821 /* Emit code to perform further access permissions checks at
1822 * runtime; this may result in an exception.
1825 TCGv_i32 tcg_syn
, tcg_isread
;
1828 gen_a64_set_pc_im(s
->pc_curr
);
1829 tmpptr
= tcg_const_ptr(ri
);
1830 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1831 tcg_syn
= tcg_const_i32(syndrome
);
1832 tcg_isread
= tcg_const_i32(isread
);
1833 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
, tcg_isread
);
1834 tcg_temp_free_ptr(tmpptr
);
1835 tcg_temp_free_i32(tcg_syn
);
1836 tcg_temp_free_i32(tcg_isread
);
1837 } else if (ri
->type
& ARM_CP_RAISES_EXC
) {
1839 * The readfn or writefn might raise an exception;
1840 * synchronize the CPU state in case it does.
1842 gen_a64_set_pc_im(s
->pc_curr
);
1845 /* Handle special cases first */
1846 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1850 tcg_rt
= cpu_reg(s
, rt
);
1852 gen_get_nzcv(tcg_rt
);
1854 gen_set_nzcv(tcg_rt
);
1857 case ARM_CP_CURRENTEL
:
1858 /* Reads as current EL value from pstate, which is
1859 * guaranteed to be constant by the tb flags.
1861 tcg_rt
= cpu_reg(s
, rt
);
1862 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1865 /* Writes clear the aligned block of memory which rt points into. */
1866 if (s
->mte_active
[0]) {
1870 desc
= FIELD_DP32(desc
, MTEDESC
, MIDX
, get_mem_index(s
));
1871 desc
= FIELD_DP32(desc
, MTEDESC
, TBI
, s
->tbid
);
1872 desc
= FIELD_DP32(desc
, MTEDESC
, TCMA
, s
->tcma
);
1873 t_desc
= tcg_const_i32(desc
);
1875 tcg_rt
= new_tmp_a64(s
);
1876 gen_helper_mte_check_zva(tcg_rt
, cpu_env
, t_desc
, cpu_reg(s
, rt
));
1877 tcg_temp_free_i32(t_desc
);
1879 tcg_rt
= clean_data_tbi(s
, cpu_reg(s
, rt
));
1881 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1885 TCGv_i64 clean_addr
, tag
;
1888 * DC_GVA, like DC_ZVA, requires that we supply the original
1889 * pointer for an invalid page. Probe that address first.
1891 tcg_rt
= cpu_reg(s
, rt
);
1892 clean_addr
= clean_data_tbi(s
, tcg_rt
);
1893 gen_probe_access(s
, clean_addr
, MMU_DATA_STORE
, MO_8
);
1896 /* Extract the tag from the register to match STZGM. */
1897 tag
= tcg_temp_new_i64();
1898 tcg_gen_shri_i64(tag
, tcg_rt
, 56);
1899 gen_helper_stzgm_tags(cpu_env
, clean_addr
, tag
);
1900 tcg_temp_free_i64(tag
);
1904 case ARM_CP_DC_GZVA
:
1906 TCGv_i64 clean_addr
, tag
;
1908 /* For DC_GZVA, we can rely on DC_ZVA for the proper fault. */
1909 tcg_rt
= cpu_reg(s
, rt
);
1910 clean_addr
= clean_data_tbi(s
, tcg_rt
);
1911 gen_helper_dc_zva(cpu_env
, clean_addr
);
1914 /* Extract the tag from the register to match STZGM. */
1915 tag
= tcg_temp_new_i64();
1916 tcg_gen_shri_i64(tag
, tcg_rt
, 56);
1917 gen_helper_stzgm_tags(cpu_env
, clean_addr
, tag
);
1918 tcg_temp_free_i64(tag
);
1925 if ((ri
->type
& ARM_CP_FPU
) && !fp_access_check(s
)) {
1927 } else if ((ri
->type
& ARM_CP_SVE
) && !sve_access_check(s
)) {
1931 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1935 tcg_rt
= cpu_reg(s
, rt
);
1938 if (ri
->type
& ARM_CP_CONST
) {
1939 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1940 } else if (ri
->readfn
) {
1942 tmpptr
= tcg_const_ptr(ri
);
1943 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1944 tcg_temp_free_ptr(tmpptr
);
1946 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1949 if (ri
->type
& ARM_CP_CONST
) {
1950 /* If not forbidden by access permissions, treat as WI */
1952 } else if (ri
->writefn
) {
1954 tmpptr
= tcg_const_ptr(ri
);
1955 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1956 tcg_temp_free_ptr(tmpptr
);
1958 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1962 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1963 /* I/O operations must end the TB here (whether read or write) */
1964 s
->base
.is_jmp
= DISAS_UPDATE_EXIT
;
1966 if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1968 * A write to any coprocessor regiser that ends a TB
1969 * must rebuild the hflags for the next TB.
1971 TCGv_i32 tcg_el
= tcg_const_i32(s
->current_el
);
1972 gen_helper_rebuild_hflags_a64(cpu_env
, tcg_el
);
1973 tcg_temp_free_i32(tcg_el
);
1975 * We default to ending the TB on a coprocessor register write,
1976 * but allow this to be suppressed by the register definition
1977 * (usually only necessary to work around guest bugs).
1979 s
->base
.is_jmp
= DISAS_UPDATE_EXIT
;
1984 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1985 * +---------------------+---+-----+-----+-------+-------+-----+------+
1986 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1987 * +---------------------+---+-----+-----+-------+-------+-----+------+
1989 static void disas_system(DisasContext
*s
, uint32_t insn
)
1991 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1992 l
= extract32(insn
, 21, 1);
1993 op0
= extract32(insn
, 19, 2);
1994 op1
= extract32(insn
, 16, 3);
1995 crn
= extract32(insn
, 12, 4);
1996 crm
= extract32(insn
, 8, 4);
1997 op2
= extract32(insn
, 5, 3);
1998 rt
= extract32(insn
, 0, 5);
2001 if (l
|| rt
!= 31) {
2002 unallocated_encoding(s
);
2006 case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */
2007 handle_hint(s
, insn
, op1
, op2
, crm
);
2009 case 3: /* CLREX, DSB, DMB, ISB */
2010 handle_sync(s
, insn
, op1
, op2
, crm
);
2012 case 4: /* MSR (immediate) */
2013 handle_msr_i(s
, insn
, op1
, op2
, crm
);
2016 unallocated_encoding(s
);
2021 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
2024 /* Exception generation
2026 * 31 24 23 21 20 5 4 2 1 0
2027 * +-----------------+-----+------------------------+-----+----+
2028 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
2029 * +-----------------------+------------------------+----------+
2031 static void disas_exc(DisasContext
*s
, uint32_t insn
)
2033 int opc
= extract32(insn
, 21, 3);
2034 int op2_ll
= extract32(insn
, 0, 5);
2035 int imm16
= extract32(insn
, 5, 16);
2040 /* For SVC, HVC and SMC we advance the single-step state
2041 * machine before taking the exception. This is architecturally
2042 * mandated, to ensure that single-stepping a system call
2043 * instruction works properly.
2048 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_SWI
,
2049 syn_aa64_svc(imm16
), default_exception_el(s
));
2052 if (s
->current_el
== 0) {
2053 unallocated_encoding(s
);
2056 /* The pre HVC helper handles cases when HVC gets trapped
2057 * as an undefined insn by runtime configuration.
2059 gen_a64_set_pc_im(s
->pc_curr
);
2060 gen_helper_pre_hvc(cpu_env
);
2062 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_HVC
,
2063 syn_aa64_hvc(imm16
), 2);
2066 if (s
->current_el
== 0) {
2067 unallocated_encoding(s
);
2070 gen_a64_set_pc_im(s
->pc_curr
);
2071 tmp
= tcg_const_i32(syn_aa64_smc(imm16
));
2072 gen_helper_pre_smc(cpu_env
, tmp
);
2073 tcg_temp_free_i32(tmp
);
2075 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_SMC
,
2076 syn_aa64_smc(imm16
), 3);
2079 unallocated_encoding(s
);
2085 unallocated_encoding(s
);
2089 gen_exception_bkpt_insn(s
, syn_aa64_bkpt(imm16
));
2093 unallocated_encoding(s
);
2096 /* HLT. This has two purposes.
2097 * Architecturally, it is an external halting debug instruction.
2098 * Since QEMU doesn't implement external debug, we treat this as
2099 * it is required for halting debug disabled: it will UNDEF.
2100 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
2102 if (semihosting_enabled() && imm16
== 0xf000) {
2103 #ifndef CONFIG_USER_ONLY
2104 /* In system mode, don't allow userspace access to semihosting,
2105 * to provide some semblance of security (and for consistency
2106 * with our 32-bit semihosting).
2108 if (s
->current_el
== 0) {
2109 unsupported_encoding(s
, insn
);
2113 gen_exception_internal_insn(s
, s
->pc_curr
, EXCP_SEMIHOST
);
2115 unsupported_encoding(s
, insn
);
2119 if (op2_ll
< 1 || op2_ll
> 3) {
2120 unallocated_encoding(s
);
2123 /* DCPS1, DCPS2, DCPS3 */
2124 unsupported_encoding(s
, insn
);
2127 unallocated_encoding(s
);
2132 /* Unconditional branch (register)
2133 * 31 25 24 21 20 16 15 10 9 5 4 0
2134 * +---------------+-------+-------+-------+------+-------+
2135 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
2136 * +---------------+-------+-------+-------+------+-------+
2138 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
2140 unsigned int opc
, op2
, op3
, rn
, op4
;
2141 unsigned btype_mod
= 2; /* 0: BR, 1: BLR, 2: other */
2145 opc
= extract32(insn
, 21, 4);
2146 op2
= extract32(insn
, 16, 5);
2147 op3
= extract32(insn
, 10, 6);
2148 rn
= extract32(insn
, 5, 5);
2149 op4
= extract32(insn
, 0, 5);
2152 goto do_unallocated
;
2164 goto do_unallocated
;
2166 dst
= cpu_reg(s
, rn
);
2171 if (!dc_isar_feature(aa64_pauth
, s
)) {
2172 goto do_unallocated
;
2176 if (rn
!= 0x1f || op4
!= 0x1f) {
2177 goto do_unallocated
;
2180 modifier
= cpu_X
[31];
2182 /* BRAAZ, BRABZ, BLRAAZ, BLRABZ */
2184 goto do_unallocated
;
2186 modifier
= new_tmp_a64_zero(s
);
2188 if (s
->pauth_active
) {
2189 dst
= new_tmp_a64(s
);
2191 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2193 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2196 dst
= cpu_reg(s
, rn
);
2201 goto do_unallocated
;
2203 gen_a64_set_pc(s
, dst
);
2204 /* BLR also needs to load return address */
2206 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
2212 if (!dc_isar_feature(aa64_pauth
, s
)) {
2213 goto do_unallocated
;
2215 if ((op3
& ~1) != 2) {
2216 goto do_unallocated
;
2218 btype_mod
= opc
& 1;
2219 if (s
->pauth_active
) {
2220 dst
= new_tmp_a64(s
);
2221 modifier
= cpu_reg_sp(s
, op4
);
2223 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2225 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2228 dst
= cpu_reg(s
, rn
);
2230 gen_a64_set_pc(s
, dst
);
2231 /* BLRAA also needs to load return address */
2233 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
2238 if (s
->current_el
== 0) {
2239 goto do_unallocated
;
2244 goto do_unallocated
;
2246 dst
= tcg_temp_new_i64();
2247 tcg_gen_ld_i64(dst
, cpu_env
,
2248 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2251 case 2: /* ERETAA */
2252 case 3: /* ERETAB */
2253 if (!dc_isar_feature(aa64_pauth
, s
)) {
2254 goto do_unallocated
;
2256 if (rn
!= 0x1f || op4
!= 0x1f) {
2257 goto do_unallocated
;
2259 dst
= tcg_temp_new_i64();
2260 tcg_gen_ld_i64(dst
, cpu_env
,
2261 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2262 if (s
->pauth_active
) {
2263 modifier
= cpu_X
[31];
2265 gen_helper_autia(dst
, cpu_env
, dst
, modifier
);
2267 gen_helper_autib(dst
, cpu_env
, dst
, modifier
);
2273 goto do_unallocated
;
2275 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
2279 gen_helper_exception_return(cpu_env
, dst
);
2280 tcg_temp_free_i64(dst
);
2281 /* Must exit loop to check un-masked IRQs */
2282 s
->base
.is_jmp
= DISAS_EXIT
;
2286 if (op3
!= 0 || op4
!= 0 || rn
!= 0x1f) {
2287 goto do_unallocated
;
2289 unsupported_encoding(s
, insn
);
2295 unallocated_encoding(s
);
2299 switch (btype_mod
) {
2301 if (dc_isar_feature(aa64_bti
, s
)) {
2302 /* BR to {x16,x17} or !guard -> 1, else 3. */
2303 set_btype(s
, rn
== 16 || rn
== 17 || !s
->guarded_page
? 1 : 3);
2308 if (dc_isar_feature(aa64_bti
, s
)) {
2309 /* BLR sets BTYPE to 2, regardless of source guarded page. */
2314 default: /* RET or none of the above. */
2315 /* BTYPE will be set to 0 by normal end-of-insn processing. */
2319 s
->base
.is_jmp
= DISAS_JUMP
;
2322 /* Branches, exception generating and system instructions */
2323 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
2325 switch (extract32(insn
, 25, 7)) {
2326 case 0x0a: case 0x0b:
2327 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
2328 disas_uncond_b_imm(s
, insn
);
2330 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
2331 disas_comp_b_imm(s
, insn
);
2333 case 0x1b: case 0x5b: /* Test & branch (immediate) */
2334 disas_test_b_imm(s
, insn
);
2336 case 0x2a: /* Conditional branch (immediate) */
2337 disas_cond_b_imm(s
, insn
);
2339 case 0x6a: /* Exception generation / System */
2340 if (insn
& (1 << 24)) {
2341 if (extract32(insn
, 22, 2) == 0) {
2342 disas_system(s
, insn
);
2344 unallocated_encoding(s
);
2350 case 0x6b: /* Unconditional branch (register) */
2351 disas_uncond_b_reg(s
, insn
);
2354 unallocated_encoding(s
);
2360 * Load/Store exclusive instructions are implemented by remembering
2361 * the value/address loaded, and seeing if these are the same
2362 * when the store is performed. This is not actually the architecturally
2363 * mandated semantics, but it works for typical guest code sequences
2364 * and avoids having to monitor regular stores.
2366 * The store exclusive uses the atomic cmpxchg primitives to avoid
2367 * races in multi-threaded linux-user and when MTTCG softmmu is
2370 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
2371 TCGv_i64 addr
, int size
, bool is_pair
)
2373 int idx
= get_mem_index(s
);
2374 MemOp memop
= s
->be_data
;
2376 g_assert(size
<= 3);
2378 g_assert(size
>= 2);
2380 /* The pair must be single-copy atomic for the doubleword. */
2381 memop
|= MO_64
| MO_ALIGN
;
2382 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2383 if (s
->be_data
== MO_LE
) {
2384 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 0, 32);
2385 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 32, 32);
2387 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 32, 32);
2388 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 0, 32);
2391 /* The pair must be single-copy atomic for *each* doubleword, not
2392 the entire quadword, however it must be quadword aligned. */
2394 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
,
2395 memop
| MO_ALIGN_16
);
2397 TCGv_i64 addr2
= tcg_temp_new_i64();
2398 tcg_gen_addi_i64(addr2
, addr
, 8);
2399 tcg_gen_qemu_ld_i64(cpu_exclusive_high
, addr2
, idx
, memop
);
2400 tcg_temp_free_i64(addr2
);
2402 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2403 tcg_gen_mov_i64(cpu_reg(s
, rt2
), cpu_exclusive_high
);
2406 memop
|= size
| MO_ALIGN
;
2407 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2408 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2410 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
2413 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
2414 TCGv_i64 addr
, int size
, int is_pair
)
2416 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
2417 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
2420 * [addr + datasize] = {Rt2};
2426 * env->exclusive_addr = -1;
2428 TCGLabel
*fail_label
= gen_new_label();
2429 TCGLabel
*done_label
= gen_new_label();
2432 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
2434 tmp
= tcg_temp_new_i64();
2437 if (s
->be_data
== MO_LE
) {
2438 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2440 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt2
), cpu_reg(s
, rt
));
2442 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
,
2443 cpu_exclusive_val
, tmp
,
2445 MO_64
| MO_ALIGN
| s
->be_data
);
2446 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2447 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2448 if (!HAVE_CMPXCHG128
) {
2449 gen_helper_exit_atomic(cpu_env
);
2450 s
->base
.is_jmp
= DISAS_NORETURN
;
2451 } else if (s
->be_data
== MO_LE
) {
2452 gen_helper_paired_cmpxchg64_le_parallel(tmp
, cpu_env
,
2457 gen_helper_paired_cmpxchg64_be_parallel(tmp
, cpu_env
,
2462 } else if (s
->be_data
== MO_LE
) {
2463 gen_helper_paired_cmpxchg64_le(tmp
, cpu_env
, cpu_exclusive_addr
,
2464 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2466 gen_helper_paired_cmpxchg64_be(tmp
, cpu_env
, cpu_exclusive_addr
,
2467 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2470 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
, cpu_exclusive_val
,
2471 cpu_reg(s
, rt
), get_mem_index(s
),
2472 size
| MO_ALIGN
| s
->be_data
);
2473 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2475 tcg_gen_mov_i64(cpu_reg(s
, rd
), tmp
);
2476 tcg_temp_free_i64(tmp
);
2477 tcg_gen_br(done_label
);
2479 gen_set_label(fail_label
);
2480 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
2481 gen_set_label(done_label
);
2482 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
2485 static void gen_compare_and_swap(DisasContext
*s
, int rs
, int rt
,
2488 TCGv_i64 tcg_rs
= cpu_reg(s
, rs
);
2489 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2490 int memidx
= get_mem_index(s
);
2491 TCGv_i64 clean_addr
;
2494 gen_check_sp_alignment(s
);
2496 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
), true, rn
!= 31, size
);
2497 tcg_gen_atomic_cmpxchg_i64(tcg_rs
, clean_addr
, tcg_rs
, tcg_rt
, memidx
,
2498 size
| MO_ALIGN
| s
->be_data
);
2501 static void gen_compare_and_swap_pair(DisasContext
*s
, int rs
, int rt
,
2504 TCGv_i64 s1
= cpu_reg(s
, rs
);
2505 TCGv_i64 s2
= cpu_reg(s
, rs
+ 1);
2506 TCGv_i64 t1
= cpu_reg(s
, rt
);
2507 TCGv_i64 t2
= cpu_reg(s
, rt
+ 1);
2508 TCGv_i64 clean_addr
;
2509 int memidx
= get_mem_index(s
);
2512 gen_check_sp_alignment(s
);
2515 /* This is a single atomic access, despite the "pair". */
2516 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
), true, rn
!= 31, size
+ 1);
2519 TCGv_i64 cmp
= tcg_temp_new_i64();
2520 TCGv_i64 val
= tcg_temp_new_i64();
2522 if (s
->be_data
== MO_LE
) {
2523 tcg_gen_concat32_i64(val
, t1
, t2
);
2524 tcg_gen_concat32_i64(cmp
, s1
, s2
);
2526 tcg_gen_concat32_i64(val
, t2
, t1
);
2527 tcg_gen_concat32_i64(cmp
, s2
, s1
);
2530 tcg_gen_atomic_cmpxchg_i64(cmp
, clean_addr
, cmp
, val
, memidx
,
2531 MO_64
| MO_ALIGN
| s
->be_data
);
2532 tcg_temp_free_i64(val
);
2534 if (s
->be_data
== MO_LE
) {
2535 tcg_gen_extr32_i64(s1
, s2
, cmp
);
2537 tcg_gen_extr32_i64(s2
, s1
, cmp
);
2539 tcg_temp_free_i64(cmp
);
2540 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2541 if (HAVE_CMPXCHG128
) {
2542 TCGv_i32 tcg_rs
= tcg_const_i32(rs
);
2543 if (s
->be_data
== MO_LE
) {
2544 gen_helper_casp_le_parallel(cpu_env
, tcg_rs
,
2545 clean_addr
, t1
, t2
);
2547 gen_helper_casp_be_parallel(cpu_env
, tcg_rs
,
2548 clean_addr
, t1
, t2
);
2550 tcg_temp_free_i32(tcg_rs
);
2552 gen_helper_exit_atomic(cpu_env
);
2553 s
->base
.is_jmp
= DISAS_NORETURN
;
2556 TCGv_i64 d1
= tcg_temp_new_i64();
2557 TCGv_i64 d2
= tcg_temp_new_i64();
2558 TCGv_i64 a2
= tcg_temp_new_i64();
2559 TCGv_i64 c1
= tcg_temp_new_i64();
2560 TCGv_i64 c2
= tcg_temp_new_i64();
2561 TCGv_i64 zero
= tcg_const_i64(0);
2563 /* Load the two words, in memory order. */
2564 tcg_gen_qemu_ld_i64(d1
, clean_addr
, memidx
,
2565 MO_64
| MO_ALIGN_16
| s
->be_data
);
2566 tcg_gen_addi_i64(a2
, clean_addr
, 8);
2567 tcg_gen_qemu_ld_i64(d2
, a2
, memidx
, MO_64
| s
->be_data
);
2569 /* Compare the two words, also in memory order. */
2570 tcg_gen_setcond_i64(TCG_COND_EQ
, c1
, d1
, s1
);
2571 tcg_gen_setcond_i64(TCG_COND_EQ
, c2
, d2
, s2
);
2572 tcg_gen_and_i64(c2
, c2
, c1
);
2574 /* If compare equal, write back new data, else write back old data. */
2575 tcg_gen_movcond_i64(TCG_COND_NE
, c1
, c2
, zero
, t1
, d1
);
2576 tcg_gen_movcond_i64(TCG_COND_NE
, c2
, c2
, zero
, t2
, d2
);
2577 tcg_gen_qemu_st_i64(c1
, clean_addr
, memidx
, MO_64
| s
->be_data
);
2578 tcg_gen_qemu_st_i64(c2
, a2
, memidx
, MO_64
| s
->be_data
);
2579 tcg_temp_free_i64(a2
);
2580 tcg_temp_free_i64(c1
);
2581 tcg_temp_free_i64(c2
);
2582 tcg_temp_free_i64(zero
);
2584 /* Write back the data from memory to Rs. */
2585 tcg_gen_mov_i64(s1
, d1
);
2586 tcg_gen_mov_i64(s2
, d2
);
2587 tcg_temp_free_i64(d1
);
2588 tcg_temp_free_i64(d2
);
2592 /* Update the Sixty-Four bit (SF) registersize. This logic is derived
2593 * from the ARMv8 specs for LDR (Shared decode for all encodings).
2595 static bool disas_ldst_compute_iss_sf(int size
, bool is_signed
, int opc
)
2597 int opc0
= extract32(opc
, 0, 1);
2601 regsize
= opc0
? 32 : 64;
2603 regsize
= size
== 3 ? 64 : 32;
2605 return regsize
== 64;
2608 /* Load/store exclusive
2610 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
2611 * +-----+-------------+----+---+----+------+----+-------+------+------+
2612 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
2613 * +-----+-------------+----+---+----+------+----+-------+------+------+
2615 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
2616 * L: 0 -> store, 1 -> load
2617 * o2: 0 -> exclusive, 1 -> not
2618 * o1: 0 -> single register, 1 -> register pair
2619 * o0: 1 -> load-acquire/store-release, 0 -> not
2621 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
2623 int rt
= extract32(insn
, 0, 5);
2624 int rn
= extract32(insn
, 5, 5);
2625 int rt2
= extract32(insn
, 10, 5);
2626 int rs
= extract32(insn
, 16, 5);
2627 int is_lasr
= extract32(insn
, 15, 1);
2628 int o2_L_o1_o0
= extract32(insn
, 21, 3) * 2 | is_lasr
;
2629 int size
= extract32(insn
, 30, 2);
2630 TCGv_i64 clean_addr
;
2632 switch (o2_L_o1_o0
) {
2633 case 0x0: /* STXR */
2634 case 0x1: /* STLXR */
2636 gen_check_sp_alignment(s
);
2639 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2641 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2642 true, rn
!= 31, size
);
2643 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, false);
2646 case 0x4: /* LDXR */
2647 case 0x5: /* LDAXR */
2649 gen_check_sp_alignment(s
);
2651 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2652 false, rn
!= 31, size
);
2654 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, false);
2656 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2660 case 0x8: /* STLLR */
2661 if (!dc_isar_feature(aa64_lor
, s
)) {
2664 /* StoreLORelease is the same as Store-Release for QEMU. */
2666 case 0x9: /* STLR */
2667 /* Generate ISS for non-exclusive accesses including LASR. */
2669 gen_check_sp_alignment(s
);
2671 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2672 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2673 true, rn
!= 31, size
);
2674 do_gpr_st(s
, cpu_reg(s
, rt
), clean_addr
, size
, true, rt
,
2675 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2678 case 0xc: /* LDLAR */
2679 if (!dc_isar_feature(aa64_lor
, s
)) {
2682 /* LoadLOAcquire is the same as Load-Acquire for QEMU. */
2684 case 0xd: /* LDAR */
2685 /* Generate ISS for non-exclusive accesses including LASR. */
2687 gen_check_sp_alignment(s
);
2689 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2690 false, rn
!= 31, size
);
2691 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
, false, false, true, rt
,
2692 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2693 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2696 case 0x2: case 0x3: /* CASP / STXP */
2697 if (size
& 2) { /* STXP / STLXP */
2699 gen_check_sp_alignment(s
);
2702 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2704 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2705 true, rn
!= 31, size
);
2706 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, true);
2710 && ((rt
| rs
) & 1) == 0
2711 && dc_isar_feature(aa64_atomics
, s
)) {
2713 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2718 case 0x6: case 0x7: /* CASPA / LDXP */
2719 if (size
& 2) { /* LDXP / LDAXP */
2721 gen_check_sp_alignment(s
);
2723 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2724 false, rn
!= 31, size
);
2726 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, true);
2728 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2733 && ((rt
| rs
) & 1) == 0
2734 && dc_isar_feature(aa64_atomics
, s
)) {
2735 /* CASPA / CASPAL */
2736 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2742 case 0xb: /* CASL */
2743 case 0xe: /* CASA */
2744 case 0xf: /* CASAL */
2745 if (rt2
== 31 && dc_isar_feature(aa64_atomics
, s
)) {
2746 gen_compare_and_swap(s
, rs
, rt
, rn
, size
);
2751 unallocated_encoding(s
);
2755 * Load register (literal)
2757 * 31 30 29 27 26 25 24 23 5 4 0
2758 * +-----+-------+---+-----+-------------------+-------+
2759 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
2760 * +-----+-------+---+-----+-------------------+-------+
2762 * V: 1 -> vector (simd/fp)
2763 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
2764 * 10-> 32 bit signed, 11 -> prefetch
2765 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
2767 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
2769 int rt
= extract32(insn
, 0, 5);
2770 int64_t imm
= sextract32(insn
, 5, 19) << 2;
2771 bool is_vector
= extract32(insn
, 26, 1);
2772 int opc
= extract32(insn
, 30, 2);
2773 bool is_signed
= false;
2775 TCGv_i64 tcg_rt
, clean_addr
;
2779 unallocated_encoding(s
);
2783 if (!fp_access_check(s
)) {
2788 /* PRFM (literal) : prefetch */
2791 size
= 2 + extract32(opc
, 0, 1);
2792 is_signed
= extract32(opc
, 1, 1);
2795 tcg_rt
= cpu_reg(s
, rt
);
2797 clean_addr
= tcg_const_i64(s
->pc_curr
+ imm
);
2799 do_fp_ld(s
, rt
, clean_addr
, size
);
2801 /* Only unsigned 32bit loads target 32bit registers. */
2802 bool iss_sf
= opc
!= 0;
2804 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, is_signed
, false,
2805 true, rt
, iss_sf
, false);
2807 tcg_temp_free_i64(clean_addr
);
2811 * LDNP (Load Pair - non-temporal hint)
2812 * LDP (Load Pair - non vector)
2813 * LDPSW (Load Pair Signed Word - non vector)
2814 * STNP (Store Pair - non-temporal hint)
2815 * STP (Store Pair - non vector)
2816 * LDNP (Load Pair of SIMD&FP - non-temporal hint)
2817 * LDP (Load Pair of SIMD&FP)
2818 * STNP (Store Pair of SIMD&FP - non-temporal hint)
2819 * STP (Store Pair of SIMD&FP)
2821 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
2822 * +-----+-------+---+---+-------+---+-----------------------------+
2823 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
2824 * +-----+-------+---+---+-------+---+-------+-------+------+------+
2826 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
2828 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
2829 * V: 0 -> GPR, 1 -> Vector
2830 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
2831 * 10 -> signed offset, 11 -> pre-index
2832 * L: 0 -> Store 1 -> Load
2834 * Rt, Rt2 = GPR or SIMD registers to be stored
2835 * Rn = general purpose register containing address
2836 * imm7 = signed offset (multiple of 4 or 8 depending on size)
2838 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
2840 int rt
= extract32(insn
, 0, 5);
2841 int rn
= extract32(insn
, 5, 5);
2842 int rt2
= extract32(insn
, 10, 5);
2843 uint64_t offset
= sextract64(insn
, 15, 7);
2844 int index
= extract32(insn
, 23, 2);
2845 bool is_vector
= extract32(insn
, 26, 1);
2846 bool is_load
= extract32(insn
, 22, 1);
2847 int opc
= extract32(insn
, 30, 2);
2849 bool is_signed
= false;
2850 bool postindex
= false;
2852 bool set_tag
= false;
2854 TCGv_i64 clean_addr
, dirty_addr
;
2859 unallocated_encoding(s
);
2865 } else if (opc
== 1 && !is_load
) {
2867 if (!dc_isar_feature(aa64_mte_insn_reg
, s
) || index
== 0) {
2868 unallocated_encoding(s
);
2874 size
= 2 + extract32(opc
, 1, 1);
2875 is_signed
= extract32(opc
, 0, 1);
2876 if (!is_load
&& is_signed
) {
2877 unallocated_encoding(s
);
2883 case 1: /* post-index */
2888 /* signed offset with "non-temporal" hint. Since we don't emulate
2889 * caches we don't care about hints to the cache system about
2890 * data access patterns, and handle this identically to plain
2894 /* There is no non-temporal-hint version of LDPSW */
2895 unallocated_encoding(s
);
2900 case 2: /* signed offset, rn not updated */
2903 case 3: /* pre-index */
2909 if (is_vector
&& !fp_access_check(s
)) {
2913 offset
<<= (set_tag
? LOG2_TAG_GRANULE
: size
);
2916 gen_check_sp_alignment(s
);
2919 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
2921 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
2927 * TODO: We could rely on the stores below, at least for
2928 * system mode, if we arrange to add MO_ALIGN_16.
2930 gen_helper_stg_stub(cpu_env
, dirty_addr
);
2931 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2932 gen_helper_stg_parallel(cpu_env
, dirty_addr
, dirty_addr
);
2934 gen_helper_stg(cpu_env
, dirty_addr
, dirty_addr
);
2938 clean_addr
= gen_mte_checkN(s
, dirty_addr
, !is_load
,
2939 (wback
|| rn
!= 31) && !set_tag
,
2944 do_fp_ld(s
, rt
, clean_addr
, size
);
2946 do_fp_st(s
, rt
, clean_addr
, size
);
2948 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2950 do_fp_ld(s
, rt2
, clean_addr
, size
);
2952 do_fp_st(s
, rt2
, clean_addr
, size
);
2955 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2956 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
2959 TCGv_i64 tmp
= tcg_temp_new_i64();
2961 /* Do not modify tcg_rt before recognizing any exception
2962 * from the second load.
2964 do_gpr_ld(s
, tmp
, clean_addr
, size
, is_signed
, false,
2965 false, 0, false, false);
2966 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2967 do_gpr_ld(s
, tcg_rt2
, clean_addr
, size
, is_signed
, false,
2968 false, 0, false, false);
2970 tcg_gen_mov_i64(tcg_rt
, tmp
);
2971 tcg_temp_free_i64(tmp
);
2973 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
2974 false, 0, false, false);
2975 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2976 do_gpr_st(s
, tcg_rt2
, clean_addr
, size
,
2977 false, 0, false, false);
2983 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
2985 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
2990 * Load/store (immediate post-indexed)
2991 * Load/store (immediate pre-indexed)
2992 * Load/store (unscaled immediate)
2994 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
2995 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2996 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
2997 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2999 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
3001 * V = 0 -> non-vector
3002 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
3003 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3005 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
,
3011 int rn
= extract32(insn
, 5, 5);
3012 int imm9
= sextract32(insn
, 12, 9);
3013 int idx
= extract32(insn
, 10, 2);
3014 bool is_signed
= false;
3015 bool is_store
= false;
3016 bool is_extended
= false;
3017 bool is_unpriv
= (idx
== 2);
3018 bool iss_valid
= !is_vector
;
3023 TCGv_i64 clean_addr
, dirty_addr
;
3026 size
|= (opc
& 2) << 1;
3027 if (size
> 4 || is_unpriv
) {
3028 unallocated_encoding(s
);
3031 is_store
= ((opc
& 1) == 0);
3032 if (!fp_access_check(s
)) {
3036 if (size
== 3 && opc
== 2) {
3037 /* PRFM - prefetch */
3039 unallocated_encoding(s
);
3044 if (opc
== 3 && size
> 1) {
3045 unallocated_encoding(s
);
3048 is_store
= (opc
== 0);
3049 is_signed
= extract32(opc
, 1, 1);
3050 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3068 g_assert_not_reached();
3072 gen_check_sp_alignment(s
);
3075 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3077 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
3080 memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
3081 clean_addr
= gen_mte_check1_mmuidx(s
, dirty_addr
, is_store
,
3082 writeback
|| rn
!= 31,
3083 size
, is_unpriv
, memidx
);
3087 do_fp_st(s
, rt
, clean_addr
, size
);
3089 do_fp_ld(s
, rt
, clean_addr
, size
);
3092 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3093 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3096 do_gpr_st_memidx(s
, tcg_rt
, clean_addr
, size
, memidx
,
3097 iss_valid
, rt
, iss_sf
, false);
3099 do_gpr_ld_memidx(s
, tcg_rt
, clean_addr
, size
,
3100 is_signed
, is_extended
, memidx
,
3101 iss_valid
, rt
, iss_sf
, false);
3106 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
3108 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
3110 tcg_gen_mov_i64(tcg_rn
, dirty_addr
);
3115 * Load/store (register offset)
3117 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3118 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
3119 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
3120 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
3123 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
3124 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3126 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
3127 * opc<0>: 0 -> store, 1 -> load
3128 * V: 1 -> vector/simd
3129 * opt: extend encoding (see DecodeRegExtend)
3130 * S: if S=1 then scale (essentially index by sizeof(size))
3131 * Rt: register to transfer into/out of
3132 * Rn: address register or SP for base
3133 * Rm: offset register or ZR for offset
3135 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
,
3141 int rn
= extract32(insn
, 5, 5);
3142 int shift
= extract32(insn
, 12, 1);
3143 int rm
= extract32(insn
, 16, 5);
3144 int opt
= extract32(insn
, 13, 3);
3145 bool is_signed
= false;
3146 bool is_store
= false;
3147 bool is_extended
= false;
3149 TCGv_i64 tcg_rm
, clean_addr
, dirty_addr
;
3151 if (extract32(opt
, 1, 1) == 0) {
3152 unallocated_encoding(s
);
3157 size
|= (opc
& 2) << 1;
3159 unallocated_encoding(s
);
3162 is_store
= !extract32(opc
, 0, 1);
3163 if (!fp_access_check(s
)) {
3167 if (size
== 3 && opc
== 2) {
3168 /* PRFM - prefetch */
3171 if (opc
== 3 && size
> 1) {
3172 unallocated_encoding(s
);
3175 is_store
= (opc
== 0);
3176 is_signed
= extract32(opc
, 1, 1);
3177 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3181 gen_check_sp_alignment(s
);
3183 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3185 tcg_rm
= read_cpu_reg(s
, rm
, 1);
3186 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
3188 tcg_gen_add_i64(dirty_addr
, dirty_addr
, tcg_rm
);
3189 clean_addr
= gen_mte_check1(s
, dirty_addr
, is_store
, true, size
);
3193 do_fp_st(s
, rt
, clean_addr
, size
);
3195 do_fp_ld(s
, rt
, clean_addr
, size
);
3198 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3199 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3201 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3202 true, rt
, iss_sf
, false);
3204 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
,
3205 is_signed
, is_extended
,
3206 true, rt
, iss_sf
, false);
3212 * Load/store (unsigned immediate)
3214 * 31 30 29 27 26 25 24 23 22 21 10 9 5
3215 * +----+-------+---+-----+-----+------------+-------+------+
3216 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
3217 * +----+-------+---+-----+-----+------------+-------+------+
3220 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
3221 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3223 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
3224 * opc<0>: 0 -> store, 1 -> load
3225 * Rn: base address register (inc SP)
3226 * Rt: target register
3228 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
,
3234 int rn
= extract32(insn
, 5, 5);
3235 unsigned int imm12
= extract32(insn
, 10, 12);
3236 unsigned int offset
;
3238 TCGv_i64 clean_addr
, dirty_addr
;
3241 bool is_signed
= false;
3242 bool is_extended
= false;
3245 size
|= (opc
& 2) << 1;
3247 unallocated_encoding(s
);
3250 is_store
= !extract32(opc
, 0, 1);
3251 if (!fp_access_check(s
)) {
3255 if (size
== 3 && opc
== 2) {
3256 /* PRFM - prefetch */
3259 if (opc
== 3 && size
> 1) {
3260 unallocated_encoding(s
);
3263 is_store
= (opc
== 0);
3264 is_signed
= extract32(opc
, 1, 1);
3265 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3269 gen_check_sp_alignment(s
);
3271 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3272 offset
= imm12
<< size
;
3273 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3274 clean_addr
= gen_mte_check1(s
, dirty_addr
, is_store
, rn
!= 31, size
);
3278 do_fp_st(s
, rt
, clean_addr
, size
);
3280 do_fp_ld(s
, rt
, clean_addr
, size
);
3283 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3284 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3286 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3287 true, rt
, iss_sf
, false);
3289 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, is_signed
, is_extended
,
3290 true, rt
, iss_sf
, false);
3295 /* Atomic memory operations
3297 * 31 30 27 26 24 22 21 16 15 12 10 5 0
3298 * +------+-------+---+-----+-----+---+----+----+-----+-----+----+-----+
3299 * | size | 1 1 1 | V | 0 0 | A R | 1 | Rs | o3 | opc | 0 0 | Rn | Rt |
3300 * +------+-------+---+-----+-----+--------+----+-----+-----+----+-----+
3302 * Rt: the result register
3303 * Rn: base address or SP
3304 * Rs: the source register for the operation
3305 * V: vector flag (always 0 as of v8.3)
3309 static void disas_ldst_atomic(DisasContext
*s
, uint32_t insn
,
3310 int size
, int rt
, bool is_vector
)
3312 int rs
= extract32(insn
, 16, 5);
3313 int rn
= extract32(insn
, 5, 5);
3314 int o3_opc
= extract32(insn
, 12, 4);
3315 bool r
= extract32(insn
, 22, 1);
3316 bool a
= extract32(insn
, 23, 1);
3317 TCGv_i64 tcg_rs
, clean_addr
;
3318 AtomicThreeOpFn
*fn
= NULL
;
3320 if (is_vector
|| !dc_isar_feature(aa64_atomics
, s
)) {
3321 unallocated_encoding(s
);
3325 case 000: /* LDADD */
3326 fn
= tcg_gen_atomic_fetch_add_i64
;
3328 case 001: /* LDCLR */
3329 fn
= tcg_gen_atomic_fetch_and_i64
;
3331 case 002: /* LDEOR */
3332 fn
= tcg_gen_atomic_fetch_xor_i64
;
3334 case 003: /* LDSET */
3335 fn
= tcg_gen_atomic_fetch_or_i64
;
3337 case 004: /* LDSMAX */
3338 fn
= tcg_gen_atomic_fetch_smax_i64
;
3340 case 005: /* LDSMIN */
3341 fn
= tcg_gen_atomic_fetch_smin_i64
;
3343 case 006: /* LDUMAX */
3344 fn
= tcg_gen_atomic_fetch_umax_i64
;
3346 case 007: /* LDUMIN */
3347 fn
= tcg_gen_atomic_fetch_umin_i64
;
3350 fn
= tcg_gen_atomic_xchg_i64
;
3352 case 014: /* LDAPR, LDAPRH, LDAPRB */
3353 if (!dc_isar_feature(aa64_rcpc_8_3
, s
) ||
3354 rs
!= 31 || a
!= 1 || r
!= 0) {
3355 unallocated_encoding(s
);
3360 unallocated_encoding(s
);
3365 gen_check_sp_alignment(s
);
3367 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
), false, rn
!= 31, size
);
3369 if (o3_opc
== 014) {
3371 * LDAPR* are a special case because they are a simple load, not a
3372 * fetch-and-do-something op.
3373 * The architectural consistency requirements here are weaker than
3374 * full load-acquire (we only need "load-acquire processor consistent"),
3375 * but we choose to implement them as full LDAQ.
3377 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
, false, false,
3378 true, rt
, disas_ldst_compute_iss_sf(size
, false, 0), true);
3379 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
3383 tcg_rs
= read_cpu_reg(s
, rs
, true);
3385 if (o3_opc
== 1) { /* LDCLR */
3386 tcg_gen_not_i64(tcg_rs
, tcg_rs
);
3389 /* The tcg atomic primitives are all full barriers. Therefore we
3390 * can ignore the Acquire and Release bits of this instruction.
3392 fn(cpu_reg(s
, rt
), clean_addr
, tcg_rs
, get_mem_index(s
),
3393 s
->be_data
| size
| MO_ALIGN
);
3397 * PAC memory operations
3399 * 31 30 27 26 24 22 21 12 11 10 5 0
3400 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3401 * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt |
3402 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3404 * Rt: the result register
3405 * Rn: base address or SP
3406 * V: vector flag (always 0 as of v8.3)
3407 * M: clear for key DA, set for key DB
3408 * W: pre-indexing flag
3411 static void disas_ldst_pac(DisasContext
*s
, uint32_t insn
,
3412 int size
, int rt
, bool is_vector
)
3414 int rn
= extract32(insn
, 5, 5);
3415 bool is_wback
= extract32(insn
, 11, 1);
3416 bool use_key_a
= !extract32(insn
, 23, 1);
3418 TCGv_i64 clean_addr
, dirty_addr
, tcg_rt
;
3420 if (size
!= 3 || is_vector
|| !dc_isar_feature(aa64_pauth
, s
)) {
3421 unallocated_encoding(s
);
3426 gen_check_sp_alignment(s
);
3428 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3430 if (s
->pauth_active
) {
3432 gen_helper_autda(dirty_addr
, cpu_env
, dirty_addr
,
3433 new_tmp_a64_zero(s
));
3435 gen_helper_autdb(dirty_addr
, cpu_env
, dirty_addr
,
3436 new_tmp_a64_zero(s
));
3440 /* Form the 10-bit signed, scaled offset. */
3441 offset
= (extract32(insn
, 22, 1) << 9) | extract32(insn
, 12, 9);
3442 offset
= sextract32(offset
<< size
, 0, 10 + size
);
3443 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3445 /* Note that "clean" and "dirty" here refer to TBI not PAC. */
3446 clean_addr
= gen_mte_check1(s
, dirty_addr
, false,
3447 is_wback
|| rn
!= 31, size
);
3449 tcg_rt
= cpu_reg(s
, rt
);
3450 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, /* is_signed */ false,
3451 /* extend */ false, /* iss_valid */ !is_wback
,
3452 /* iss_srt */ rt
, /* iss_sf */ true, /* iss_ar */ false);
3455 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
3460 * LDAPR/STLR (unscaled immediate)
3462 * 31 30 24 22 21 12 10 5 0
3463 * +------+-------------+-----+---+--------+-----+----+-----+
3464 * | size | 0 1 1 0 0 1 | opc | 0 | imm9 | 0 0 | Rn | Rt |
3465 * +------+-------------+-----+---+--------+-----+----+-----+
3467 * Rt: source or destination register
3469 * imm9: unscaled immediate offset
3470 * opc: 00: STLUR*, 01/10/11: various LDAPUR*
3471 * size: size of load/store
3473 static void disas_ldst_ldapr_stlr(DisasContext
*s
, uint32_t insn
)
3475 int rt
= extract32(insn
, 0, 5);
3476 int rn
= extract32(insn
, 5, 5);
3477 int offset
= sextract32(insn
, 12, 9);
3478 int opc
= extract32(insn
, 22, 2);
3479 int size
= extract32(insn
, 30, 2);
3480 TCGv_i64 clean_addr
, dirty_addr
;
3481 bool is_store
= false;
3482 bool is_signed
= false;
3483 bool extend
= false;
3486 if (!dc_isar_feature(aa64_rcpc_8_4
, s
)) {
3487 unallocated_encoding(s
);
3492 case 0: /* STLURB */
3495 case 1: /* LDAPUR* */
3497 case 2: /* LDAPURS* 64-bit variant */
3499 unallocated_encoding(s
);
3504 case 3: /* LDAPURS* 32-bit variant */
3506 unallocated_encoding(s
);
3510 extend
= true; /* zero-extend 32->64 after signed load */
3513 g_assert_not_reached();
3516 iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3519 gen_check_sp_alignment(s
);
3522 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3523 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3524 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3527 /* Store-Release semantics */
3528 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
3529 do_gpr_st(s
, cpu_reg(s
, rt
), clean_addr
, size
, true, rt
, iss_sf
, true);
3532 * Load-AcquirePC semantics; we implement as the slightly more
3533 * restrictive Load-Acquire.
3535 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
, is_signed
, extend
,
3536 true, rt
, iss_sf
, true);
3537 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
3541 /* Load/store register (all forms) */
3542 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
3544 int rt
= extract32(insn
, 0, 5);
3545 int opc
= extract32(insn
, 22, 2);
3546 bool is_vector
= extract32(insn
, 26, 1);
3547 int size
= extract32(insn
, 30, 2);
3549 switch (extract32(insn
, 24, 2)) {
3551 if (extract32(insn
, 21, 1) == 0) {
3552 /* Load/store register (unscaled immediate)
3553 * Load/store immediate pre/post-indexed
3554 * Load/store register unprivileged
3556 disas_ldst_reg_imm9(s
, insn
, opc
, size
, rt
, is_vector
);
3559 switch (extract32(insn
, 10, 2)) {
3561 disas_ldst_atomic(s
, insn
, size
, rt
, is_vector
);
3564 disas_ldst_reg_roffset(s
, insn
, opc
, size
, rt
, is_vector
);
3567 disas_ldst_pac(s
, insn
, size
, rt
, is_vector
);
3572 disas_ldst_reg_unsigned_imm(s
, insn
, opc
, size
, rt
, is_vector
);
3575 unallocated_encoding(s
);
3578 /* AdvSIMD load/store multiple structures
3580 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
3581 * +---+---+---------------+---+-------------+--------+------+------+------+
3582 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
3583 * +---+---+---------------+---+-------------+--------+------+------+------+
3585 * AdvSIMD load/store multiple structures (post-indexed)
3587 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
3588 * +---+---+---------------+---+---+---------+--------+------+------+------+
3589 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
3590 * +---+---+---------------+---+---+---------+--------+------+------+------+
3592 * Rt: first (or only) SIMD&FP register to be transferred
3593 * Rn: base address or SP
3594 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3596 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
3598 int rt
= extract32(insn
, 0, 5);
3599 int rn
= extract32(insn
, 5, 5);
3600 int rm
= extract32(insn
, 16, 5);
3601 int size
= extract32(insn
, 10, 2);
3602 int opcode
= extract32(insn
, 12, 4);
3603 bool is_store
= !extract32(insn
, 22, 1);
3604 bool is_postidx
= extract32(insn
, 23, 1);
3605 bool is_q
= extract32(insn
, 30, 1);
3606 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3607 MemOp endian
= s
->be_data
;
3609 int total
; /* total bytes */
3610 int elements
; /* elements per vector */
3611 int rpt
; /* num iterations */
3612 int selem
; /* structure elements */
3615 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
3616 unallocated_encoding(s
);
3620 if (!is_postidx
&& rm
!= 0) {
3621 unallocated_encoding(s
);
3625 /* From the shared decode logic */
3656 unallocated_encoding(s
);
3660 if (size
== 3 && !is_q
&& selem
!= 1) {
3662 unallocated_encoding(s
);
3666 if (!fp_access_check(s
)) {
3671 gen_check_sp_alignment(s
);
3674 /* For our purposes, bytes are always little-endian. */
3679 total
= rpt
* selem
* (is_q
? 16 : 8);
3680 tcg_rn
= cpu_reg_sp(s
, rn
);
3683 * Issue the MTE check vs the logical repeat count, before we
3684 * promote consecutive little-endian elements below.
3686 clean_addr
= gen_mte_checkN(s
, tcg_rn
, is_store
, is_postidx
|| rn
!= 31,
3690 * Consecutive little-endian elements from a single register
3691 * can be promoted to a larger little-endian operation.
3693 if (selem
== 1 && endian
== MO_LE
) {
3696 elements
= (is_q
? 16 : 8) >> size
;
3698 tcg_ebytes
= tcg_const_i64(1 << size
);
3699 for (r
= 0; r
< rpt
; r
++) {
3701 for (e
= 0; e
< elements
; e
++) {
3703 for (xs
= 0; xs
< selem
; xs
++) {
3704 int tt
= (rt
+ r
+ xs
) % 32;
3706 do_vec_st(s
, tt
, e
, clean_addr
, size
, endian
);
3708 do_vec_ld(s
, tt
, e
, clean_addr
, size
, endian
);
3710 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3714 tcg_temp_free_i64(tcg_ebytes
);
3717 /* For non-quad operations, setting a slice of the low
3718 * 64 bits of the register clears the high 64 bits (in
3719 * the ARM ARM pseudocode this is implicit in the fact
3720 * that 'rval' is a 64 bit wide variable).
3721 * For quad operations, we might still need to zero the
3724 for (r
= 0; r
< rpt
* selem
; r
++) {
3725 int tt
= (rt
+ r
) % 32;
3726 clear_vec_high(s
, is_q
, tt
);
3732 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, total
);
3734 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3739 /* AdvSIMD load/store single structure
3741 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3742 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3743 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
3744 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3746 * AdvSIMD load/store single structure (post-indexed)
3748 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3749 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3750 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
3751 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3753 * Rt: first (or only) SIMD&FP register to be transferred
3754 * Rn: base address or SP
3755 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3756 * index = encoded in Q:S:size dependent on size
3758 * lane_size = encoded in R, opc
3759 * transfer width = encoded in opc, S, size
3761 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
3763 int rt
= extract32(insn
, 0, 5);
3764 int rn
= extract32(insn
, 5, 5);
3765 int rm
= extract32(insn
, 16, 5);
3766 int size
= extract32(insn
, 10, 2);
3767 int S
= extract32(insn
, 12, 1);
3768 int opc
= extract32(insn
, 13, 3);
3769 int R
= extract32(insn
, 21, 1);
3770 int is_load
= extract32(insn
, 22, 1);
3771 int is_postidx
= extract32(insn
, 23, 1);
3772 int is_q
= extract32(insn
, 30, 1);
3774 int scale
= extract32(opc
, 1, 2);
3775 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
3776 bool replicate
= false;
3777 int index
= is_q
<< 3 | S
<< 2 | size
;
3779 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3781 if (extract32(insn
, 31, 1)) {
3782 unallocated_encoding(s
);
3785 if (!is_postidx
&& rm
!= 0) {
3786 unallocated_encoding(s
);
3792 if (!is_load
|| S
) {
3793 unallocated_encoding(s
);
3802 if (extract32(size
, 0, 1)) {
3803 unallocated_encoding(s
);
3809 if (extract32(size
, 1, 1)) {
3810 unallocated_encoding(s
);
3813 if (!extract32(size
, 0, 1)) {
3817 unallocated_encoding(s
);
3825 g_assert_not_reached();
3828 if (!fp_access_check(s
)) {
3833 gen_check_sp_alignment(s
);
3836 total
= selem
<< scale
;
3837 tcg_rn
= cpu_reg_sp(s
, rn
);
3839 clean_addr
= gen_mte_checkN(s
, tcg_rn
, !is_load
, is_postidx
|| rn
!= 31,
3842 tcg_ebytes
= tcg_const_i64(1 << scale
);
3843 for (xs
= 0; xs
< selem
; xs
++) {
3845 /* Load and replicate to all elements */
3846 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3848 tcg_gen_qemu_ld_i64(tcg_tmp
, clean_addr
,
3849 get_mem_index(s
), s
->be_data
+ scale
);
3850 tcg_gen_gvec_dup_i64(scale
, vec_full_reg_offset(s
, rt
),
3851 (is_q
+ 1) * 8, vec_full_reg_size(s
),
3853 tcg_temp_free_i64(tcg_tmp
);
3855 /* Load/store one element per register */
3857 do_vec_ld(s
, rt
, index
, clean_addr
, scale
, s
->be_data
);
3859 do_vec_st(s
, rt
, index
, clean_addr
, scale
, s
->be_data
);
3862 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3865 tcg_temp_free_i64(tcg_ebytes
);
3869 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, total
);
3871 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3877 * Load/Store memory tags
3879 * 31 30 29 24 22 21 12 10 5 0
3880 * +-----+-------------+-----+---+------+-----+------+------+
3881 * | 1 1 | 0 1 1 0 0 1 | op1 | 1 | imm9 | op2 | Rn | Rt |
3882 * +-----+-------------+-----+---+------+-----+------+------+
3884 static void disas_ldst_tag(DisasContext
*s
, uint32_t insn
)
3886 int rt
= extract32(insn
, 0, 5);
3887 int rn
= extract32(insn
, 5, 5);
3888 uint64_t offset
= sextract64(insn
, 12, 9) << LOG2_TAG_GRANULE
;
3889 int op2
= extract32(insn
, 10, 2);
3890 int op1
= extract32(insn
, 22, 2);
3891 bool is_load
= false, is_pair
= false, is_zero
= false, is_mult
= false;
3893 TCGv_i64 addr
, clean_addr
, tcg_rt
;
3895 /* We checked insn bits [29:24,21] in the caller. */
3896 if (extract32(insn
, 30, 2) != 3) {
3897 goto do_unallocated
;
3901 * @index is a tri-state variable which has 3 states:
3902 * < 0 : post-index, writeback
3903 * = 0 : signed offset
3904 * > 0 : pre-index, writeback
3913 if (s
->current_el
== 0 || offset
!= 0) {
3914 goto do_unallocated
;
3916 is_mult
= is_zero
= true;
3936 if (s
->current_el
== 0 || offset
!= 0) {
3937 goto do_unallocated
;
3945 is_pair
= is_zero
= true;
3949 if (s
->current_el
== 0 || offset
!= 0) {
3950 goto do_unallocated
;
3952 is_mult
= is_load
= true;
3958 unallocated_encoding(s
);
3963 ? !dc_isar_feature(aa64_mte
, s
)
3964 : !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
3965 goto do_unallocated
;
3969 gen_check_sp_alignment(s
);
3972 addr
= read_cpu_reg_sp(s
, rn
, true);
3974 /* pre-index or signed offset */
3975 tcg_gen_addi_i64(addr
, addr
, offset
);
3979 tcg_rt
= cpu_reg(s
, rt
);
3982 int size
= 4 << s
->dcz_blocksize
;
3985 gen_helper_stzgm_tags(cpu_env
, addr
, tcg_rt
);
3988 * The non-tags portion of STZGM is mostly like DC_ZVA,
3989 * except the alignment happens before the access.
3991 clean_addr
= clean_data_tbi(s
, addr
);
3992 tcg_gen_andi_i64(clean_addr
, clean_addr
, -size
);
3993 gen_helper_dc_zva(cpu_env
, clean_addr
);
3994 } else if (s
->ata
) {
3996 gen_helper_ldgm(tcg_rt
, cpu_env
, addr
);
3998 gen_helper_stgm(cpu_env
, addr
, tcg_rt
);
4001 MMUAccessType acc
= is_load
? MMU_DATA_LOAD
: MMU_DATA_STORE
;
4002 int size
= 4 << GMID_EL1_BS
;
4004 clean_addr
= clean_data_tbi(s
, addr
);
4005 tcg_gen_andi_i64(clean_addr
, clean_addr
, -size
);
4006 gen_probe_access(s
, clean_addr
, acc
, size
);
4009 /* The result tags are zeros. */
4010 tcg_gen_movi_i64(tcg_rt
, 0);
4017 tcg_gen_andi_i64(addr
, addr
, -TAG_GRANULE
);
4018 tcg_rt
= cpu_reg(s
, rt
);
4020 gen_helper_ldg(tcg_rt
, cpu_env
, addr
, tcg_rt
);
4022 clean_addr
= clean_data_tbi(s
, addr
);
4023 gen_probe_access(s
, clean_addr
, MMU_DATA_LOAD
, MO_8
);
4024 gen_address_with_allocation_tag0(tcg_rt
, addr
);
4027 tcg_rt
= cpu_reg_sp(s
, rt
);
4030 * For STG and ST2G, we need to check alignment and probe memory.
4031 * TODO: For STZG and STZ2G, we could rely on the stores below,
4032 * at least for system mode; user-only won't enforce alignment.
4035 gen_helper_st2g_stub(cpu_env
, addr
);
4037 gen_helper_stg_stub(cpu_env
, addr
);
4039 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
4041 gen_helper_st2g_parallel(cpu_env
, addr
, tcg_rt
);
4043 gen_helper_stg_parallel(cpu_env
, addr
, tcg_rt
);
4047 gen_helper_st2g(cpu_env
, addr
, tcg_rt
);
4049 gen_helper_stg(cpu_env
, addr
, tcg_rt
);
4055 TCGv_i64 clean_addr
= clean_data_tbi(s
, addr
);
4056 TCGv_i64 tcg_zero
= tcg_const_i64(0);
4057 int mem_index
= get_mem_index(s
);
4058 int i
, n
= (1 + is_pair
) << LOG2_TAG_GRANULE
;
4060 tcg_gen_qemu_st_i64(tcg_zero
, clean_addr
, mem_index
,
4061 MO_Q
| MO_ALIGN_16
);
4062 for (i
= 8; i
< n
; i
+= 8) {
4063 tcg_gen_addi_i64(clean_addr
, clean_addr
, 8);
4064 tcg_gen_qemu_st_i64(tcg_zero
, clean_addr
, mem_index
, MO_Q
);
4066 tcg_temp_free_i64(tcg_zero
);
4070 /* pre-index or post-index */
4073 tcg_gen_addi_i64(addr
, addr
, offset
);
4075 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), addr
);
4079 /* Loads and stores */
4080 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
4082 switch (extract32(insn
, 24, 6)) {
4083 case 0x08: /* Load/store exclusive */
4084 disas_ldst_excl(s
, insn
);
4086 case 0x18: case 0x1c: /* Load register (literal) */
4087 disas_ld_lit(s
, insn
);
4089 case 0x28: case 0x29:
4090 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
4091 disas_ldst_pair(s
, insn
);
4093 case 0x38: case 0x39:
4094 case 0x3c: case 0x3d: /* Load/store register (all forms) */
4095 disas_ldst_reg(s
, insn
);
4097 case 0x0c: /* AdvSIMD load/store multiple structures */
4098 disas_ldst_multiple_struct(s
, insn
);
4100 case 0x0d: /* AdvSIMD load/store single structure */
4101 disas_ldst_single_struct(s
, insn
);
4104 if (extract32(insn
, 21, 1) != 0) {
4105 disas_ldst_tag(s
, insn
);
4106 } else if (extract32(insn
, 10, 2) == 0) {
4107 disas_ldst_ldapr_stlr(s
, insn
);
4109 unallocated_encoding(s
);
4113 unallocated_encoding(s
);
4118 /* PC-rel. addressing
4119 * 31 30 29 28 24 23 5 4 0
4120 * +----+-------+-----------+-------------------+------+
4121 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
4122 * +----+-------+-----------+-------------------+------+
4124 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
4126 unsigned int page
, rd
;
4130 page
= extract32(insn
, 31, 1);
4131 /* SignExtend(immhi:immlo) -> offset */
4132 offset
= sextract64(insn
, 5, 19);
4133 offset
= offset
<< 2 | extract32(insn
, 29, 2);
4134 rd
= extract32(insn
, 0, 5);
4138 /* ADRP (page based) */
4143 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
4147 * Add/subtract (immediate)
4149 * 31 30 29 28 23 22 21 10 9 5 4 0
4150 * +--+--+--+-------------+--+-------------+-----+-----+
4151 * |sf|op| S| 1 0 0 0 1 0 |sh| imm12 | Rn | Rd |
4152 * +--+--+--+-------------+--+-------------+-----+-----+
4154 * sf: 0 -> 32bit, 1 -> 64bit
4155 * op: 0 -> add , 1 -> sub
4157 * sh: 1 -> LSL imm by 12
4159 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
4161 int rd
= extract32(insn
, 0, 5);
4162 int rn
= extract32(insn
, 5, 5);
4163 uint64_t imm
= extract32(insn
, 10, 12);
4164 bool shift
= extract32(insn
, 22, 1);
4165 bool setflags
= extract32(insn
, 29, 1);
4166 bool sub_op
= extract32(insn
, 30, 1);
4167 bool is_64bit
= extract32(insn
, 31, 1);
4169 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
4170 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
4171 TCGv_i64 tcg_result
;
4177 tcg_result
= tcg_temp_new_i64();
4180 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
4182 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
4185 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
4187 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
4189 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
4191 tcg_temp_free_i64(tcg_imm
);
4195 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4197 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4200 tcg_temp_free_i64(tcg_result
);
4204 * Add/subtract (immediate, with tags)
4206 * 31 30 29 28 23 22 21 16 14 10 9 5 4 0
4207 * +--+--+--+-------------+--+---------+--+-------+-----+-----+
4208 * |sf|op| S| 1 0 0 0 1 1 |o2| uimm6 |o3| uimm4 | Rn | Rd |
4209 * +--+--+--+-------------+--+---------+--+-------+-----+-----+
4211 * op: 0 -> add, 1 -> sub
4213 static void disas_add_sub_imm_with_tags(DisasContext
*s
, uint32_t insn
)
4215 int rd
= extract32(insn
, 0, 5);
4216 int rn
= extract32(insn
, 5, 5);
4217 int uimm4
= extract32(insn
, 10, 4);
4218 int uimm6
= extract32(insn
, 16, 6);
4219 bool sub_op
= extract32(insn
, 30, 1);
4220 TCGv_i64 tcg_rn
, tcg_rd
;
4223 /* Test all of sf=1, S=0, o2=0, o3=0. */
4224 if ((insn
& 0xa040c000u
) != 0x80000000u
||
4225 !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
4226 unallocated_encoding(s
);
4230 imm
= uimm6
<< LOG2_TAG_GRANULE
;
4235 tcg_rn
= cpu_reg_sp(s
, rn
);
4236 tcg_rd
= cpu_reg_sp(s
, rd
);
4239 TCGv_i32 offset
= tcg_const_i32(imm
);
4240 TCGv_i32 tag_offset
= tcg_const_i32(uimm4
);
4242 gen_helper_addsubg(tcg_rd
, cpu_env
, tcg_rn
, offset
, tag_offset
);
4243 tcg_temp_free_i32(tag_offset
);
4244 tcg_temp_free_i32(offset
);
4246 tcg_gen_addi_i64(tcg_rd
, tcg_rn
, imm
);
4247 gen_address_with_allocation_tag0(tcg_rd
, tcg_rd
);
4251 /* The input should be a value in the bottom e bits (with higher
4252 * bits zero); returns that value replicated into every element
4253 * of size e in a 64 bit integer.
4255 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
4265 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
4266 static inline uint64_t bitmask64(unsigned int length
)
4268 assert(length
> 0 && length
<= 64);
4269 return ~0ULL >> (64 - length
);
4272 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
4273 * only require the wmask. Returns false if the imms/immr/immn are a reserved
4274 * value (ie should cause a guest UNDEF exception), and true if they are
4275 * valid, in which case the decoded bit pattern is written to result.
4277 bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
4278 unsigned int imms
, unsigned int immr
)
4281 unsigned e
, levels
, s
, r
;
4284 assert(immn
< 2 && imms
< 64 && immr
< 64);
4286 /* The bit patterns we create here are 64 bit patterns which
4287 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
4288 * 64 bits each. Each element contains the same value: a run
4289 * of between 1 and e-1 non-zero bits, rotated within the
4290 * element by between 0 and e-1 bits.
4292 * The element size and run length are encoded into immn (1 bit)
4293 * and imms (6 bits) as follows:
4294 * 64 bit elements: immn = 1, imms = <length of run - 1>
4295 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
4296 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
4297 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
4298 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
4299 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
4300 * Notice that immn = 0, imms = 11111x is the only combination
4301 * not covered by one of the above options; this is reserved.
4302 * Further, <length of run - 1> all-ones is a reserved pattern.
4304 * In all cases the rotation is by immr % e (and immr is 6 bits).
4307 /* First determine the element size */
4308 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
4310 /* This is the immn == 0, imms == 0x11111x case */
4320 /* <length of run - 1> mustn't be all-ones. */
4324 /* Create the value of one element: s+1 set bits rotated
4325 * by r within the element (which is e bits wide)...
4327 mask
= bitmask64(s
+ 1);
4329 mask
= (mask
>> r
) | (mask
<< (e
- r
));
4330 mask
&= bitmask64(e
);
4332 /* ...then replicate the element over the whole 64 bit value */
4333 mask
= bitfield_replicate(mask
, e
);
4338 /* Logical (immediate)
4339 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
4340 * +----+-----+-------------+---+------+------+------+------+
4341 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
4342 * +----+-----+-------------+---+------+------+------+------+
4344 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
4346 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
4347 TCGv_i64 tcg_rd
, tcg_rn
;
4349 bool is_and
= false;
4351 sf
= extract32(insn
, 31, 1);
4352 opc
= extract32(insn
, 29, 2);
4353 is_n
= extract32(insn
, 22, 1);
4354 immr
= extract32(insn
, 16, 6);
4355 imms
= extract32(insn
, 10, 6);
4356 rn
= extract32(insn
, 5, 5);
4357 rd
= extract32(insn
, 0, 5);
4360 unallocated_encoding(s
);
4364 if (opc
== 0x3) { /* ANDS */
4365 tcg_rd
= cpu_reg(s
, rd
);
4367 tcg_rd
= cpu_reg_sp(s
, rd
);
4369 tcg_rn
= cpu_reg(s
, rn
);
4371 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
4372 /* some immediate field values are reserved */
4373 unallocated_encoding(s
);
4378 wmask
&= 0xffffffff;
4382 case 0x3: /* ANDS */
4384 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
4388 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
4391 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
4394 assert(FALSE
); /* must handle all above */
4398 if (!sf
&& !is_and
) {
4399 /* zero extend final result; we know we can skip this for AND
4400 * since the immediate had the high 32 bits clear.
4402 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4405 if (opc
== 3) { /* ANDS */
4406 gen_logic_CC(sf
, tcg_rd
);
4411 * Move wide (immediate)
4413 * 31 30 29 28 23 22 21 20 5 4 0
4414 * +--+-----+-------------+-----+----------------+------+
4415 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
4416 * +--+-----+-------------+-----+----------------+------+
4418 * sf: 0 -> 32 bit, 1 -> 64 bit
4419 * opc: 00 -> N, 10 -> Z, 11 -> K
4420 * hw: shift/16 (0,16, and sf only 32, 48)
4422 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
4424 int rd
= extract32(insn
, 0, 5);
4425 uint64_t imm
= extract32(insn
, 5, 16);
4426 int sf
= extract32(insn
, 31, 1);
4427 int opc
= extract32(insn
, 29, 2);
4428 int pos
= extract32(insn
, 21, 2) << 4;
4429 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4432 if (!sf
&& (pos
>= 32)) {
4433 unallocated_encoding(s
);
4447 tcg_gen_movi_i64(tcg_rd
, imm
);
4450 tcg_imm
= tcg_const_i64(imm
);
4451 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
4452 tcg_temp_free_i64(tcg_imm
);
4454 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4458 unallocated_encoding(s
);
4464 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
4465 * +----+-----+-------------+---+------+------+------+------+
4466 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
4467 * +----+-----+-------------+---+------+------+------+------+
4469 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
4471 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
4472 TCGv_i64 tcg_rd
, tcg_tmp
;
4474 sf
= extract32(insn
, 31, 1);
4475 opc
= extract32(insn
, 29, 2);
4476 n
= extract32(insn
, 22, 1);
4477 ri
= extract32(insn
, 16, 6);
4478 si
= extract32(insn
, 10, 6);
4479 rn
= extract32(insn
, 5, 5);
4480 rd
= extract32(insn
, 0, 5);
4481 bitsize
= sf
? 64 : 32;
4483 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
4484 unallocated_encoding(s
);
4488 tcg_rd
= cpu_reg(s
, rd
);
4490 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
4491 to be smaller than bitsize, we'll never reference data outside the
4492 low 32-bits anyway. */
4493 tcg_tmp
= read_cpu_reg(s
, rn
, 1);
4495 /* Recognize simple(r) extractions. */
4497 /* Wd<s-r:0> = Wn<s:r> */
4498 len
= (si
- ri
) + 1;
4499 if (opc
== 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */
4500 tcg_gen_sextract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
4502 } else if (opc
== 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */
4503 tcg_gen_extract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
4506 /* opc == 1, BFXIL fall through to deposit */
4507 tcg_gen_shri_i64(tcg_tmp
, tcg_tmp
, ri
);
4510 /* Handle the ri > si case with a deposit
4511 * Wd<32+s-r,32-r> = Wn<s:0>
4514 pos
= (bitsize
- ri
) & (bitsize
- 1);
4517 if (opc
== 0 && len
< ri
) {
4518 /* SBFM: sign extend the destination field from len to fill
4519 the balance of the word. Let the deposit below insert all
4520 of those sign bits. */
4521 tcg_gen_sextract_i64(tcg_tmp
, tcg_tmp
, 0, len
);
4525 if (opc
== 1) { /* BFM, BFXIL */
4526 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
4528 /* SBFM or UBFM: We start with zero, and we haven't modified
4529 any bits outside bitsize, therefore the zero-extension
4530 below is unneeded. */
4531 tcg_gen_deposit_z_i64(tcg_rd
, tcg_tmp
, pos
, len
);
4536 if (!sf
) { /* zero extend final result */
4537 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4542 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
4543 * +----+------+-------------+---+----+------+--------+------+------+
4544 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
4545 * +----+------+-------------+---+----+------+--------+------+------+
4547 static void disas_extract(DisasContext
*s
, uint32_t insn
)
4549 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
4551 sf
= extract32(insn
, 31, 1);
4552 n
= extract32(insn
, 22, 1);
4553 rm
= extract32(insn
, 16, 5);
4554 imm
= extract32(insn
, 10, 6);
4555 rn
= extract32(insn
, 5, 5);
4556 rd
= extract32(insn
, 0, 5);
4557 op21
= extract32(insn
, 29, 2);
4558 op0
= extract32(insn
, 21, 1);
4559 bitsize
= sf
? 64 : 32;
4561 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
4562 unallocated_encoding(s
);
4564 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
4566 tcg_rd
= cpu_reg(s
, rd
);
4568 if (unlikely(imm
== 0)) {
4569 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
4570 * so an extract from bit 0 is a special case.
4573 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
4575 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
4578 tcg_rm
= cpu_reg(s
, rm
);
4579 tcg_rn
= cpu_reg(s
, rn
);
4582 /* Specialization to ROR happens in EXTRACT2. */
4583 tcg_gen_extract2_i64(tcg_rd
, tcg_rm
, tcg_rn
, imm
);
4585 TCGv_i32 t0
= tcg_temp_new_i32();
4587 tcg_gen_extrl_i64_i32(t0
, tcg_rm
);
4589 tcg_gen_rotri_i32(t0
, t0
, imm
);
4591 TCGv_i32 t1
= tcg_temp_new_i32();
4592 tcg_gen_extrl_i64_i32(t1
, tcg_rn
);
4593 tcg_gen_extract2_i32(t0
, t0
, t1
, imm
);
4594 tcg_temp_free_i32(t1
);
4596 tcg_gen_extu_i32_i64(tcg_rd
, t0
);
4597 tcg_temp_free_i32(t0
);
4603 /* Data processing - immediate */
4604 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
4606 switch (extract32(insn
, 23, 6)) {
4607 case 0x20: case 0x21: /* PC-rel. addressing */
4608 disas_pc_rel_adr(s
, insn
);
4610 case 0x22: /* Add/subtract (immediate) */
4611 disas_add_sub_imm(s
, insn
);
4613 case 0x23: /* Add/subtract (immediate, with tags) */
4614 disas_add_sub_imm_with_tags(s
, insn
);
4616 case 0x24: /* Logical (immediate) */
4617 disas_logic_imm(s
, insn
);
4619 case 0x25: /* Move wide (immediate) */
4620 disas_movw_imm(s
, insn
);
4622 case 0x26: /* Bitfield */
4623 disas_bitfield(s
, insn
);
4625 case 0x27: /* Extract */
4626 disas_extract(s
, insn
);
4629 unallocated_encoding(s
);
4634 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
4635 * Note that it is the caller's responsibility to ensure that the
4636 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
4637 * mandated semantics for out of range shifts.
4639 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4640 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
4642 switch (shift_type
) {
4643 case A64_SHIFT_TYPE_LSL
:
4644 tcg_gen_shl_i64(dst
, src
, shift_amount
);
4646 case A64_SHIFT_TYPE_LSR
:
4647 tcg_gen_shr_i64(dst
, src
, shift_amount
);
4649 case A64_SHIFT_TYPE_ASR
:
4651 tcg_gen_ext32s_i64(dst
, src
);
4653 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
4655 case A64_SHIFT_TYPE_ROR
:
4657 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
4660 t0
= tcg_temp_new_i32();
4661 t1
= tcg_temp_new_i32();
4662 tcg_gen_extrl_i64_i32(t0
, src
);
4663 tcg_gen_extrl_i64_i32(t1
, shift_amount
);
4664 tcg_gen_rotr_i32(t0
, t0
, t1
);
4665 tcg_gen_extu_i32_i64(dst
, t0
);
4666 tcg_temp_free_i32(t0
);
4667 tcg_temp_free_i32(t1
);
4671 assert(FALSE
); /* all shift types should be handled */
4675 if (!sf
) { /* zero extend final result */
4676 tcg_gen_ext32u_i64(dst
, dst
);
4680 /* Shift a TCGv src by immediate, put result in dst.
4681 * The shift amount must be in range (this should always be true as the
4682 * relevant instructions will UNDEF on bad shift immediates).
4684 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4685 enum a64_shift_type shift_type
, unsigned int shift_i
)
4687 assert(shift_i
< (sf
? 64 : 32));
4690 tcg_gen_mov_i64(dst
, src
);
4692 TCGv_i64 shift_const
;
4694 shift_const
= tcg_const_i64(shift_i
);
4695 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
4696 tcg_temp_free_i64(shift_const
);
4700 /* Logical (shifted register)
4701 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4702 * +----+-----+-----------+-------+---+------+--------+------+------+
4703 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
4704 * +----+-----+-----------+-------+---+------+--------+------+------+
4706 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
4708 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
4709 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
4711 sf
= extract32(insn
, 31, 1);
4712 opc
= extract32(insn
, 29, 2);
4713 shift_type
= extract32(insn
, 22, 2);
4714 invert
= extract32(insn
, 21, 1);
4715 rm
= extract32(insn
, 16, 5);
4716 shift_amount
= extract32(insn
, 10, 6);
4717 rn
= extract32(insn
, 5, 5);
4718 rd
= extract32(insn
, 0, 5);
4720 if (!sf
&& (shift_amount
& (1 << 5))) {
4721 unallocated_encoding(s
);
4725 tcg_rd
= cpu_reg(s
, rd
);
4727 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
4728 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
4729 * register-register MOV and MVN, so it is worth special casing.
4731 tcg_rm
= cpu_reg(s
, rm
);
4733 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
4735 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4739 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
4741 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
4747 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4750 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
4753 tcg_rn
= cpu_reg(s
, rn
);
4755 switch (opc
| (invert
<< 2)) {
4758 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4761 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4764 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4768 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4771 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4774 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4782 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4786 gen_logic_CC(sf
, tcg_rd
);
4791 * Add/subtract (extended register)
4793 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
4794 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4795 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
4796 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4798 * sf: 0 -> 32bit, 1 -> 64bit
4799 * op: 0 -> add , 1 -> sub
4802 * option: extension type (see DecodeRegExtend)
4803 * imm3: optional shift to Rm
4805 * Rd = Rn + LSL(extend(Rm), amount)
4807 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
4809 int rd
= extract32(insn
, 0, 5);
4810 int rn
= extract32(insn
, 5, 5);
4811 int imm3
= extract32(insn
, 10, 3);
4812 int option
= extract32(insn
, 13, 3);
4813 int rm
= extract32(insn
, 16, 5);
4814 int opt
= extract32(insn
, 22, 2);
4815 bool setflags
= extract32(insn
, 29, 1);
4816 bool sub_op
= extract32(insn
, 30, 1);
4817 bool sf
= extract32(insn
, 31, 1);
4819 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
4821 TCGv_i64 tcg_result
;
4823 if (imm3
> 4 || opt
!= 0) {
4824 unallocated_encoding(s
);
4828 /* non-flag setting ops may use SP */
4830 tcg_rd
= cpu_reg_sp(s
, rd
);
4832 tcg_rd
= cpu_reg(s
, rd
);
4834 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
4836 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4837 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
4839 tcg_result
= tcg_temp_new_i64();
4843 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4845 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4849 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4851 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4856 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4858 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4861 tcg_temp_free_i64(tcg_result
);
4865 * Add/subtract (shifted register)
4867 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4868 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4869 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
4870 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4872 * sf: 0 -> 32bit, 1 -> 64bit
4873 * op: 0 -> add , 1 -> sub
4875 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
4876 * imm6: Shift amount to apply to Rm before the add/sub
4878 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
4880 int rd
= extract32(insn
, 0, 5);
4881 int rn
= extract32(insn
, 5, 5);
4882 int imm6
= extract32(insn
, 10, 6);
4883 int rm
= extract32(insn
, 16, 5);
4884 int shift_type
= extract32(insn
, 22, 2);
4885 bool setflags
= extract32(insn
, 29, 1);
4886 bool sub_op
= extract32(insn
, 30, 1);
4887 bool sf
= extract32(insn
, 31, 1);
4889 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4890 TCGv_i64 tcg_rn
, tcg_rm
;
4891 TCGv_i64 tcg_result
;
4893 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
4894 unallocated_encoding(s
);
4898 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4899 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4901 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
4903 tcg_result
= tcg_temp_new_i64();
4907 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4909 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4913 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4915 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4920 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4922 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4925 tcg_temp_free_i64(tcg_result
);
4928 /* Data-processing (3 source)
4930 * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
4931 * +--+------+-----------+------+------+----+------+------+------+
4932 * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
4933 * +--+------+-----------+------+------+----+------+------+------+
4935 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
4937 int rd
= extract32(insn
, 0, 5);
4938 int rn
= extract32(insn
, 5, 5);
4939 int ra
= extract32(insn
, 10, 5);
4940 int rm
= extract32(insn
, 16, 5);
4941 int op_id
= (extract32(insn
, 29, 3) << 4) |
4942 (extract32(insn
, 21, 3) << 1) |
4943 extract32(insn
, 15, 1);
4944 bool sf
= extract32(insn
, 31, 1);
4945 bool is_sub
= extract32(op_id
, 0, 1);
4946 bool is_high
= extract32(op_id
, 2, 1);
4947 bool is_signed
= false;
4952 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
4954 case 0x42: /* SMADDL */
4955 case 0x43: /* SMSUBL */
4956 case 0x44: /* SMULH */
4959 case 0x0: /* MADD (32bit) */
4960 case 0x1: /* MSUB (32bit) */
4961 case 0x40: /* MADD (64bit) */
4962 case 0x41: /* MSUB (64bit) */
4963 case 0x4a: /* UMADDL */
4964 case 0x4b: /* UMSUBL */
4965 case 0x4c: /* UMULH */
4968 unallocated_encoding(s
);
4973 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
4974 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4975 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
4976 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
4979 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4981 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4984 tcg_temp_free_i64(low_bits
);
4988 tcg_op1
= tcg_temp_new_i64();
4989 tcg_op2
= tcg_temp_new_i64();
4990 tcg_tmp
= tcg_temp_new_i64();
4993 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
4994 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
4997 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
4998 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
5000 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
5001 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
5005 if (ra
== 31 && !is_sub
) {
5006 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
5007 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
5009 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
5011 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
5013 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
5018 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
5021 tcg_temp_free_i64(tcg_op1
);
5022 tcg_temp_free_i64(tcg_op2
);
5023 tcg_temp_free_i64(tcg_tmp
);
5026 /* Add/subtract (with carry)
5027 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
5028 * +--+--+--+------------------------+------+-------------+------+-----+
5029 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | 0 0 0 0 0 0 | Rn | Rd |
5030 * +--+--+--+------------------------+------+-------------+------+-----+
5033 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
5035 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
5036 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
5038 sf
= extract32(insn
, 31, 1);
5039 op
= extract32(insn
, 30, 1);
5040 setflags
= extract32(insn
, 29, 1);
5041 rm
= extract32(insn
, 16, 5);
5042 rn
= extract32(insn
, 5, 5);
5043 rd
= extract32(insn
, 0, 5);
5045 tcg_rd
= cpu_reg(s
, rd
);
5046 tcg_rn
= cpu_reg(s
, rn
);
5049 tcg_y
= new_tmp_a64(s
);
5050 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
5052 tcg_y
= cpu_reg(s
, rm
);
5056 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
5058 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
5063 * Rotate right into flags
5064 * 31 30 29 21 15 10 5 4 0
5065 * +--+--+--+-----------------+--------+-----------+------+--+------+
5066 * |sf|op| S| 1 1 0 1 0 0 0 0 | imm6 | 0 0 0 0 1 | Rn |o2| mask |
5067 * +--+--+--+-----------------+--------+-----------+------+--+------+
5069 static void disas_rotate_right_into_flags(DisasContext
*s
, uint32_t insn
)
5071 int mask
= extract32(insn
, 0, 4);
5072 int o2
= extract32(insn
, 4, 1);
5073 int rn
= extract32(insn
, 5, 5);
5074 int imm6
= extract32(insn
, 15, 6);
5075 int sf_op_s
= extract32(insn
, 29, 3);
5079 if (sf_op_s
!= 5 || o2
!= 0 || !dc_isar_feature(aa64_condm_4
, s
)) {
5080 unallocated_encoding(s
);
5084 tcg_rn
= read_cpu_reg(s
, rn
, 1);
5085 tcg_gen_rotri_i64(tcg_rn
, tcg_rn
, imm6
);
5087 nzcv
= tcg_temp_new_i32();
5088 tcg_gen_extrl_i64_i32(nzcv
, tcg_rn
);
5090 if (mask
& 8) { /* N */
5091 tcg_gen_shli_i32(cpu_NF
, nzcv
, 31 - 3);
5093 if (mask
& 4) { /* Z */
5094 tcg_gen_not_i32(cpu_ZF
, nzcv
);
5095 tcg_gen_andi_i32(cpu_ZF
, cpu_ZF
, 4);
5097 if (mask
& 2) { /* C */
5098 tcg_gen_extract_i32(cpu_CF
, nzcv
, 1, 1);
5100 if (mask
& 1) { /* V */
5101 tcg_gen_shli_i32(cpu_VF
, nzcv
, 31 - 0);
5104 tcg_temp_free_i32(nzcv
);
5108 * Evaluate into flags
5109 * 31 30 29 21 15 14 10 5 4 0
5110 * +--+--+--+-----------------+---------+----+---------+------+--+------+
5111 * |sf|op| S| 1 1 0 1 0 0 0 0 | opcode2 | sz | 0 0 1 0 | Rn |o3| mask |
5112 * +--+--+--+-----------------+---------+----+---------+------+--+------+
5114 static void disas_evaluate_into_flags(DisasContext
*s
, uint32_t insn
)
5116 int o3_mask
= extract32(insn
, 0, 5);
5117 int rn
= extract32(insn
, 5, 5);
5118 int o2
= extract32(insn
, 15, 6);
5119 int sz
= extract32(insn
, 14, 1);
5120 int sf_op_s
= extract32(insn
, 29, 3);
5124 if (sf_op_s
!= 1 || o2
!= 0 || o3_mask
!= 0xd ||
5125 !dc_isar_feature(aa64_condm_4
, s
)) {
5126 unallocated_encoding(s
);
5129 shift
= sz
? 16 : 24; /* SETF16 or SETF8 */
5131 tmp
= tcg_temp_new_i32();
5132 tcg_gen_extrl_i64_i32(tmp
, cpu_reg(s
, rn
));
5133 tcg_gen_shli_i32(cpu_NF
, tmp
, shift
);
5134 tcg_gen_shli_i32(cpu_VF
, tmp
, shift
- 1);
5135 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
5136 tcg_gen_xor_i32(cpu_VF
, cpu_VF
, cpu_NF
);
5137 tcg_temp_free_i32(tmp
);
5140 /* Conditional compare (immediate / register)
5141 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
5142 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
5143 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
5144 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
5147 static void disas_cc(DisasContext
*s
, uint32_t insn
)
5149 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
5150 TCGv_i32 tcg_t0
, tcg_t1
, tcg_t2
;
5151 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
5154 if (!extract32(insn
, 29, 1)) {
5155 unallocated_encoding(s
);
5158 if (insn
& (1 << 10 | 1 << 4)) {
5159 unallocated_encoding(s
);
5162 sf
= extract32(insn
, 31, 1);
5163 op
= extract32(insn
, 30, 1);
5164 is_imm
= extract32(insn
, 11, 1);
5165 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
5166 cond
= extract32(insn
, 12, 4);
5167 rn
= extract32(insn
, 5, 5);
5168 nzcv
= extract32(insn
, 0, 4);
5170 /* Set T0 = !COND. */
5171 tcg_t0
= tcg_temp_new_i32();
5172 arm_test_cc(&c
, cond
);
5173 tcg_gen_setcondi_i32(tcg_invert_cond(c
.cond
), tcg_t0
, c
.value
, 0);
5176 /* Load the arguments for the new comparison. */
5178 tcg_y
= new_tmp_a64(s
);
5179 tcg_gen_movi_i64(tcg_y
, y
);
5181 tcg_y
= cpu_reg(s
, y
);
5183 tcg_rn
= cpu_reg(s
, rn
);
5185 /* Set the flags for the new comparison. */
5186 tcg_tmp
= tcg_temp_new_i64();
5188 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
5190 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
5192 tcg_temp_free_i64(tcg_tmp
);
5194 /* If COND was false, force the flags to #nzcv. Compute two masks
5195 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
5196 * For tcg hosts that support ANDC, we can make do with just T1.
5197 * In either case, allow the tcg optimizer to delete any unused mask.
5199 tcg_t1
= tcg_temp_new_i32();
5200 tcg_t2
= tcg_temp_new_i32();
5201 tcg_gen_neg_i32(tcg_t1
, tcg_t0
);
5202 tcg_gen_subi_i32(tcg_t2
, tcg_t0
, 1);
5204 if (nzcv
& 8) { /* N */
5205 tcg_gen_or_i32(cpu_NF
, cpu_NF
, tcg_t1
);
5207 if (TCG_TARGET_HAS_andc_i32
) {
5208 tcg_gen_andc_i32(cpu_NF
, cpu_NF
, tcg_t1
);
5210 tcg_gen_and_i32(cpu_NF
, cpu_NF
, tcg_t2
);
5213 if (nzcv
& 4) { /* Z */
5214 if (TCG_TARGET_HAS_andc_i32
) {
5215 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, tcg_t1
);
5217 tcg_gen_and_i32(cpu_ZF
, cpu_ZF
, tcg_t2
);
5220 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, tcg_t0
);
5222 if (nzcv
& 2) { /* C */
5223 tcg_gen_or_i32(cpu_CF
, cpu_CF
, tcg_t0
);
5225 if (TCG_TARGET_HAS_andc_i32
) {
5226 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, tcg_t1
);
5228 tcg_gen_and_i32(cpu_CF
, cpu_CF
, tcg_t2
);
5231 if (nzcv
& 1) { /* V */
5232 tcg_gen_or_i32(cpu_VF
, cpu_VF
, tcg_t1
);
5234 if (TCG_TARGET_HAS_andc_i32
) {
5235 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tcg_t1
);
5237 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tcg_t2
);
5240 tcg_temp_free_i32(tcg_t0
);
5241 tcg_temp_free_i32(tcg_t1
);
5242 tcg_temp_free_i32(tcg_t2
);
5245 /* Conditional select
5246 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
5247 * +----+----+---+-----------------+------+------+-----+------+------+
5248 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
5249 * +----+----+---+-----------------+------+------+-----+------+------+
5251 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
5253 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
5254 TCGv_i64 tcg_rd
, zero
;
5257 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
5258 /* S == 1 or op2<1> == 1 */
5259 unallocated_encoding(s
);
5262 sf
= extract32(insn
, 31, 1);
5263 else_inv
= extract32(insn
, 30, 1);
5264 rm
= extract32(insn
, 16, 5);
5265 cond
= extract32(insn
, 12, 4);
5266 else_inc
= extract32(insn
, 10, 1);
5267 rn
= extract32(insn
, 5, 5);
5268 rd
= extract32(insn
, 0, 5);
5270 tcg_rd
= cpu_reg(s
, rd
);
5272 a64_test_cc(&c
, cond
);
5273 zero
= tcg_const_i64(0);
5275 if (rn
== 31 && rm
== 31 && (else_inc
^ else_inv
)) {
5277 tcg_gen_setcond_i64(tcg_invert_cond(c
.cond
), tcg_rd
, c
.value
, zero
);
5279 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
5282 TCGv_i64 t_true
= cpu_reg(s
, rn
);
5283 TCGv_i64 t_false
= read_cpu_reg(s
, rm
, 1);
5284 if (else_inv
&& else_inc
) {
5285 tcg_gen_neg_i64(t_false
, t_false
);
5286 } else if (else_inv
) {
5287 tcg_gen_not_i64(t_false
, t_false
);
5288 } else if (else_inc
) {
5289 tcg_gen_addi_i64(t_false
, t_false
, 1);
5291 tcg_gen_movcond_i64(c
.cond
, tcg_rd
, c
.value
, zero
, t_true
, t_false
);
5294 tcg_temp_free_i64(zero
);
5298 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5302 static void handle_clz(DisasContext
*s
, unsigned int sf
,
5303 unsigned int rn
, unsigned int rd
)
5305 TCGv_i64 tcg_rd
, tcg_rn
;
5306 tcg_rd
= cpu_reg(s
, rd
);
5307 tcg_rn
= cpu_reg(s
, rn
);
5310 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
5312 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
5313 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
5314 tcg_gen_clzi_i32(tcg_tmp32
, tcg_tmp32
, 32);
5315 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
5316 tcg_temp_free_i32(tcg_tmp32
);
5320 static void handle_cls(DisasContext
*s
, unsigned int sf
,
5321 unsigned int rn
, unsigned int rd
)
5323 TCGv_i64 tcg_rd
, tcg_rn
;
5324 tcg_rd
= cpu_reg(s
, rd
);
5325 tcg_rn
= cpu_reg(s
, rn
);
5328 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
5330 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
5331 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
5332 tcg_gen_clrsb_i32(tcg_tmp32
, tcg_tmp32
);
5333 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
5334 tcg_temp_free_i32(tcg_tmp32
);
5338 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
5339 unsigned int rn
, unsigned int rd
)
5341 TCGv_i64 tcg_rd
, tcg_rn
;
5342 tcg_rd
= cpu_reg(s
, rd
);
5343 tcg_rn
= cpu_reg(s
, rn
);
5346 gen_helper_rbit64(tcg_rd
, tcg_rn
);
5348 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
5349 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
5350 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
5351 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
5352 tcg_temp_free_i32(tcg_tmp32
);
5356 /* REV with sf==1, opcode==3 ("REV64") */
5357 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
5358 unsigned int rn
, unsigned int rd
)
5361 unallocated_encoding(s
);
5364 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
5367 /* REV with sf==0, opcode==2
5368 * REV32 (sf==1, opcode==2)
5370 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
5371 unsigned int rn
, unsigned int rd
)
5373 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5376 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
5377 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
5379 /* bswap32_i64 requires zero high word */
5380 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
5381 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
5382 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
5383 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
5384 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
5386 tcg_temp_free_i64(tcg_tmp
);
5388 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
5389 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
5393 /* REV16 (opcode==1) */
5394 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
5395 unsigned int rn
, unsigned int rd
)
5397 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5398 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
5399 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
5400 TCGv_i64 mask
= tcg_const_i64(sf
? 0x00ff00ff00ff00ffull
: 0x00ff00ff);
5402 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 8);
5403 tcg_gen_and_i64(tcg_rd
, tcg_rn
, mask
);
5404 tcg_gen_and_i64(tcg_tmp
, tcg_tmp
, mask
);
5405 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 8);
5406 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
5408 tcg_temp_free_i64(mask
);
5409 tcg_temp_free_i64(tcg_tmp
);
5412 /* Data-processing (1 source)
5413 * 31 30 29 28 21 20 16 15 10 9 5 4 0
5414 * +----+---+---+-----------------+---------+--------+------+------+
5415 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
5416 * +----+---+---+-----------------+---------+--------+------+------+
5418 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
5420 unsigned int sf
, opcode
, opcode2
, rn
, rd
;
5423 if (extract32(insn
, 29, 1)) {
5424 unallocated_encoding(s
);
5428 sf
= extract32(insn
, 31, 1);
5429 opcode
= extract32(insn
, 10, 6);
5430 opcode2
= extract32(insn
, 16, 5);
5431 rn
= extract32(insn
, 5, 5);
5432 rd
= extract32(insn
, 0, 5);
5434 #define MAP(SF, O2, O1) ((SF) | (O1 << 1) | (O2 << 7))
5436 switch (MAP(sf
, opcode2
, opcode
)) {
5437 case MAP(0, 0x00, 0x00): /* RBIT */
5438 case MAP(1, 0x00, 0x00):
5439 handle_rbit(s
, sf
, rn
, rd
);
5441 case MAP(0, 0x00, 0x01): /* REV16 */
5442 case MAP(1, 0x00, 0x01):
5443 handle_rev16(s
, sf
, rn
, rd
);
5445 case MAP(0, 0x00, 0x02): /* REV/REV32 */
5446 case MAP(1, 0x00, 0x02):
5447 handle_rev32(s
, sf
, rn
, rd
);
5449 case MAP(1, 0x00, 0x03): /* REV64 */
5450 handle_rev64(s
, sf
, rn
, rd
);
5452 case MAP(0, 0x00, 0x04): /* CLZ */
5453 case MAP(1, 0x00, 0x04):
5454 handle_clz(s
, sf
, rn
, rd
);
5456 case MAP(0, 0x00, 0x05): /* CLS */
5457 case MAP(1, 0x00, 0x05):
5458 handle_cls(s
, sf
, rn
, rd
);
5460 case MAP(1, 0x01, 0x00): /* PACIA */
5461 if (s
->pauth_active
) {
5462 tcg_rd
= cpu_reg(s
, rd
);
5463 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5464 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5465 goto do_unallocated
;
5468 case MAP(1, 0x01, 0x01): /* PACIB */
5469 if (s
->pauth_active
) {
5470 tcg_rd
= cpu_reg(s
, rd
);
5471 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5472 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5473 goto do_unallocated
;
5476 case MAP(1, 0x01, 0x02): /* PACDA */
5477 if (s
->pauth_active
) {
5478 tcg_rd
= cpu_reg(s
, rd
);
5479 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5480 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5481 goto do_unallocated
;
5484 case MAP(1, 0x01, 0x03): /* PACDB */
5485 if (s
->pauth_active
) {
5486 tcg_rd
= cpu_reg(s
, rd
);
5487 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5488 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5489 goto do_unallocated
;
5492 case MAP(1, 0x01, 0x04): /* AUTIA */
5493 if (s
->pauth_active
) {
5494 tcg_rd
= cpu_reg(s
, rd
);
5495 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5496 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5497 goto do_unallocated
;
5500 case MAP(1, 0x01, 0x05): /* AUTIB */
5501 if (s
->pauth_active
) {
5502 tcg_rd
= cpu_reg(s
, rd
);
5503 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5504 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5505 goto do_unallocated
;
5508 case MAP(1, 0x01, 0x06): /* AUTDA */
5509 if (s
->pauth_active
) {
5510 tcg_rd
= cpu_reg(s
, rd
);
5511 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5512 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5513 goto do_unallocated
;
5516 case MAP(1, 0x01, 0x07): /* AUTDB */
5517 if (s
->pauth_active
) {
5518 tcg_rd
= cpu_reg(s
, rd
);
5519 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5520 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5521 goto do_unallocated
;
5524 case MAP(1, 0x01, 0x08): /* PACIZA */
5525 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5526 goto do_unallocated
;
5527 } else if (s
->pauth_active
) {
5528 tcg_rd
= cpu_reg(s
, rd
);
5529 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5532 case MAP(1, 0x01, 0x09): /* PACIZB */
5533 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5534 goto do_unallocated
;
5535 } else if (s
->pauth_active
) {
5536 tcg_rd
= cpu_reg(s
, rd
);
5537 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5540 case MAP(1, 0x01, 0x0a): /* PACDZA */
5541 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5542 goto do_unallocated
;
5543 } else if (s
->pauth_active
) {
5544 tcg_rd
= cpu_reg(s
, rd
);
5545 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5548 case MAP(1, 0x01, 0x0b): /* PACDZB */
5549 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5550 goto do_unallocated
;
5551 } else if (s
->pauth_active
) {
5552 tcg_rd
= cpu_reg(s
, rd
);
5553 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5556 case MAP(1, 0x01, 0x0c): /* AUTIZA */
5557 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5558 goto do_unallocated
;
5559 } else if (s
->pauth_active
) {
5560 tcg_rd
= cpu_reg(s
, rd
);
5561 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5564 case MAP(1, 0x01, 0x0d): /* AUTIZB */
5565 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5566 goto do_unallocated
;
5567 } else if (s
->pauth_active
) {
5568 tcg_rd
= cpu_reg(s
, rd
);
5569 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5572 case MAP(1, 0x01, 0x0e): /* AUTDZA */
5573 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5574 goto do_unallocated
;
5575 } else if (s
->pauth_active
) {
5576 tcg_rd
= cpu_reg(s
, rd
);
5577 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5580 case MAP(1, 0x01, 0x0f): /* AUTDZB */
5581 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5582 goto do_unallocated
;
5583 } else if (s
->pauth_active
) {
5584 tcg_rd
= cpu_reg(s
, rd
);
5585 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5588 case MAP(1, 0x01, 0x10): /* XPACI */
5589 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5590 goto do_unallocated
;
5591 } else if (s
->pauth_active
) {
5592 tcg_rd
= cpu_reg(s
, rd
);
5593 gen_helper_xpaci(tcg_rd
, cpu_env
, tcg_rd
);
5596 case MAP(1, 0x01, 0x11): /* XPACD */
5597 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5598 goto do_unallocated
;
5599 } else if (s
->pauth_active
) {
5600 tcg_rd
= cpu_reg(s
, rd
);
5601 gen_helper_xpacd(tcg_rd
, cpu_env
, tcg_rd
);
5606 unallocated_encoding(s
);
5613 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
5614 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5616 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
5617 tcg_rd
= cpu_reg(s
, rd
);
5619 if (!sf
&& is_signed
) {
5620 tcg_n
= new_tmp_a64(s
);
5621 tcg_m
= new_tmp_a64(s
);
5622 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
5623 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
5625 tcg_n
= read_cpu_reg(s
, rn
, sf
);
5626 tcg_m
= read_cpu_reg(s
, rm
, sf
);
5630 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
5632 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
5635 if (!sf
) { /* zero extend final result */
5636 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5640 /* LSLV, LSRV, ASRV, RORV */
5641 static void handle_shift_reg(DisasContext
*s
,
5642 enum a64_shift_type shift_type
, unsigned int sf
,
5643 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5645 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
5646 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5647 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
5649 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
5650 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
5651 tcg_temp_free_i64(tcg_shift
);
5654 /* CRC32[BHWX], CRC32C[BHWX] */
5655 static void handle_crc32(DisasContext
*s
,
5656 unsigned int sf
, unsigned int sz
, bool crc32c
,
5657 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5659 TCGv_i64 tcg_acc
, tcg_val
;
5662 if (!dc_isar_feature(aa64_crc32
, s
)
5663 || (sf
== 1 && sz
!= 3)
5664 || (sf
== 0 && sz
== 3)) {
5665 unallocated_encoding(s
);
5670 tcg_val
= cpu_reg(s
, rm
);
5684 g_assert_not_reached();
5686 tcg_val
= new_tmp_a64(s
);
5687 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
5690 tcg_acc
= cpu_reg(s
, rn
);
5691 tcg_bytes
= tcg_const_i32(1 << sz
);
5694 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5696 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5699 tcg_temp_free_i32(tcg_bytes
);
5702 /* Data-processing (2 source)
5703 * 31 30 29 28 21 20 16 15 10 9 5 4 0
5704 * +----+---+---+-----------------+------+--------+------+------+
5705 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
5706 * +----+---+---+-----------------+------+--------+------+------+
5708 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
5710 unsigned int sf
, rm
, opcode
, rn
, rd
, setflag
;
5711 sf
= extract32(insn
, 31, 1);
5712 setflag
= extract32(insn
, 29, 1);
5713 rm
= extract32(insn
, 16, 5);
5714 opcode
= extract32(insn
, 10, 6);
5715 rn
= extract32(insn
, 5, 5);
5716 rd
= extract32(insn
, 0, 5);
5718 if (setflag
&& opcode
!= 0) {
5719 unallocated_encoding(s
);
5724 case 0: /* SUBP(S) */
5725 if (sf
== 0 || !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
5726 goto do_unallocated
;
5728 TCGv_i64 tcg_n
, tcg_m
, tcg_d
;
5730 tcg_n
= read_cpu_reg_sp(s
, rn
, true);
5731 tcg_m
= read_cpu_reg_sp(s
, rm
, true);
5732 tcg_gen_sextract_i64(tcg_n
, tcg_n
, 0, 56);
5733 tcg_gen_sextract_i64(tcg_m
, tcg_m
, 0, 56);
5734 tcg_d
= cpu_reg(s
, rd
);
5737 gen_sub_CC(true, tcg_d
, tcg_n
, tcg_m
);
5739 tcg_gen_sub_i64(tcg_d
, tcg_n
, tcg_m
);
5744 handle_div(s
, false, sf
, rm
, rn
, rd
);
5747 handle_div(s
, true, sf
, rm
, rn
, rd
);
5750 if (sf
== 0 || !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
5751 goto do_unallocated
;
5754 gen_helper_irg(cpu_reg_sp(s
, rd
), cpu_env
,
5755 cpu_reg_sp(s
, rn
), cpu_reg(s
, rm
));
5757 gen_address_with_allocation_tag0(cpu_reg_sp(s
, rd
),
5762 if (sf
== 0 || !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
5763 goto do_unallocated
;
5765 TCGv_i64 t1
= tcg_const_i64(1);
5766 TCGv_i64 t2
= tcg_temp_new_i64();
5768 tcg_gen_extract_i64(t2
, cpu_reg_sp(s
, rn
), 56, 4);
5769 tcg_gen_shl_i64(t1
, t1
, t2
);
5770 tcg_gen_or_i64(cpu_reg(s
, rd
), cpu_reg(s
, rm
), t1
);
5772 tcg_temp_free_i64(t1
);
5773 tcg_temp_free_i64(t2
);
5777 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
5780 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
5783 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
5786 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
5788 case 12: /* PACGA */
5789 if (sf
== 0 || !dc_isar_feature(aa64_pauth
, s
)) {
5790 goto do_unallocated
;
5792 gen_helper_pacga(cpu_reg(s
, rd
), cpu_env
,
5793 cpu_reg(s
, rn
), cpu_reg_sp(s
, rm
));
5802 case 23: /* CRC32 */
5804 int sz
= extract32(opcode
, 0, 2);
5805 bool crc32c
= extract32(opcode
, 2, 1);
5806 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
5811 unallocated_encoding(s
);
5817 * Data processing - register
5818 * 31 30 29 28 25 21 20 16 10 0
5819 * +--+---+--+---+-------+-----+-------+-------+---------+
5820 * | |op0| |op1| 1 0 1 | op2 | | op3 | |
5821 * +--+---+--+---+-------+-----+-------+-------+---------+
5823 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
5825 int op0
= extract32(insn
, 30, 1);
5826 int op1
= extract32(insn
, 28, 1);
5827 int op2
= extract32(insn
, 21, 4);
5828 int op3
= extract32(insn
, 10, 6);
5833 /* Add/sub (extended register) */
5834 disas_add_sub_ext_reg(s
, insn
);
5836 /* Add/sub (shifted register) */
5837 disas_add_sub_reg(s
, insn
);
5840 /* Logical (shifted register) */
5841 disas_logic_reg(s
, insn
);
5849 case 0x00: /* Add/subtract (with carry) */
5850 disas_adc_sbc(s
, insn
);
5853 case 0x01: /* Rotate right into flags */
5855 disas_rotate_right_into_flags(s
, insn
);
5858 case 0x02: /* Evaluate into flags */
5862 disas_evaluate_into_flags(s
, insn
);
5866 goto do_unallocated
;
5870 case 0x2: /* Conditional compare */
5871 disas_cc(s
, insn
); /* both imm and reg forms */
5874 case 0x4: /* Conditional select */
5875 disas_cond_select(s
, insn
);
5878 case 0x6: /* Data-processing */
5879 if (op0
) { /* (1 source) */
5880 disas_data_proc_1src(s
, insn
);
5881 } else { /* (2 source) */
5882 disas_data_proc_2src(s
, insn
);
5885 case 0x8 ... 0xf: /* (3 source) */
5886 disas_data_proc_3src(s
, insn
);
5891 unallocated_encoding(s
);
5896 static void handle_fp_compare(DisasContext
*s
, int size
,
5897 unsigned int rn
, unsigned int rm
,
5898 bool cmp_with_zero
, bool signal_all_nans
)
5900 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
5901 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
5903 if (size
== MO_64
) {
5904 TCGv_i64 tcg_vn
, tcg_vm
;
5906 tcg_vn
= read_fp_dreg(s
, rn
);
5907 if (cmp_with_zero
) {
5908 tcg_vm
= tcg_const_i64(0);
5910 tcg_vm
= read_fp_dreg(s
, rm
);
5912 if (signal_all_nans
) {
5913 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5915 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5917 tcg_temp_free_i64(tcg_vn
);
5918 tcg_temp_free_i64(tcg_vm
);
5920 TCGv_i32 tcg_vn
= tcg_temp_new_i32();
5921 TCGv_i32 tcg_vm
= tcg_temp_new_i32();
5923 read_vec_element_i32(s
, tcg_vn
, rn
, 0, size
);
5924 if (cmp_with_zero
) {
5925 tcg_gen_movi_i32(tcg_vm
, 0);
5927 read_vec_element_i32(s
, tcg_vm
, rm
, 0, size
);
5932 if (signal_all_nans
) {
5933 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5935 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5939 if (signal_all_nans
) {
5940 gen_helper_vfp_cmpeh_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5942 gen_helper_vfp_cmph_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5946 g_assert_not_reached();
5949 tcg_temp_free_i32(tcg_vn
);
5950 tcg_temp_free_i32(tcg_vm
);
5953 tcg_temp_free_ptr(fpst
);
5955 gen_set_nzcv(tcg_flags
);
5957 tcg_temp_free_i64(tcg_flags
);
5960 /* Floating point compare
5961 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
5962 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5963 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
5964 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5966 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
5968 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
5971 mos
= extract32(insn
, 29, 3);
5972 type
= extract32(insn
, 22, 2);
5973 rm
= extract32(insn
, 16, 5);
5974 op
= extract32(insn
, 14, 2);
5975 rn
= extract32(insn
, 5, 5);
5976 opc
= extract32(insn
, 3, 2);
5977 op2r
= extract32(insn
, 0, 3);
5979 if (mos
|| op
|| op2r
) {
5980 unallocated_encoding(s
);
5993 if (dc_isar_feature(aa64_fp16
, s
)) {
5998 unallocated_encoding(s
);
6002 if (!fp_access_check(s
)) {
6006 handle_fp_compare(s
, size
, rn
, rm
, opc
& 1, opc
& 2);
6009 /* Floating point conditional compare
6010 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
6011 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
6012 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
6013 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
6015 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
6017 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
6019 TCGLabel
*label_continue
= NULL
;
6022 mos
= extract32(insn
, 29, 3);
6023 type
= extract32(insn
, 22, 2);
6024 rm
= extract32(insn
, 16, 5);
6025 cond
= extract32(insn
, 12, 4);
6026 rn
= extract32(insn
, 5, 5);
6027 op
= extract32(insn
, 4, 1);
6028 nzcv
= extract32(insn
, 0, 4);
6031 unallocated_encoding(s
);
6044 if (dc_isar_feature(aa64_fp16
, s
)) {
6049 unallocated_encoding(s
);
6053 if (!fp_access_check(s
)) {
6057 if (cond
< 0x0e) { /* not always */
6058 TCGLabel
*label_match
= gen_new_label();
6059 label_continue
= gen_new_label();
6060 arm_gen_test_cc(cond
, label_match
);
6062 tcg_flags
= tcg_const_i64(nzcv
<< 28);
6063 gen_set_nzcv(tcg_flags
);
6064 tcg_temp_free_i64(tcg_flags
);
6065 tcg_gen_br(label_continue
);
6066 gen_set_label(label_match
);
6069 handle_fp_compare(s
, size
, rn
, rm
, false, op
);
6072 gen_set_label(label_continue
);
6076 /* Floating point conditional select
6077 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6078 * +---+---+---+-----------+------+---+------+------+-----+------+------+
6079 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
6080 * +---+---+---+-----------+------+---+------+------+-----+------+------+
6082 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
6084 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
6085 TCGv_i64 t_true
, t_false
, t_zero
;
6089 mos
= extract32(insn
, 29, 3);
6090 type
= extract32(insn
, 22, 2);
6091 rm
= extract32(insn
, 16, 5);
6092 cond
= extract32(insn
, 12, 4);
6093 rn
= extract32(insn
, 5, 5);
6094 rd
= extract32(insn
, 0, 5);
6097 unallocated_encoding(s
);
6110 if (dc_isar_feature(aa64_fp16
, s
)) {
6115 unallocated_encoding(s
);
6119 if (!fp_access_check(s
)) {
6123 /* Zero extend sreg & hreg inputs to 64 bits now. */
6124 t_true
= tcg_temp_new_i64();
6125 t_false
= tcg_temp_new_i64();
6126 read_vec_element(s
, t_true
, rn
, 0, sz
);
6127 read_vec_element(s
, t_false
, rm
, 0, sz
);
6129 a64_test_cc(&c
, cond
);
6130 t_zero
= tcg_const_i64(0);
6131 tcg_gen_movcond_i64(c
.cond
, t_true
, c
.value
, t_zero
, t_true
, t_false
);
6132 tcg_temp_free_i64(t_zero
);
6133 tcg_temp_free_i64(t_false
);
6136 /* Note that sregs & hregs write back zeros to the high bits,
6137 and we've already done the zero-extension. */
6138 write_fp_dreg(s
, rd
, t_true
);
6139 tcg_temp_free_i64(t_true
);
6142 /* Floating-point data-processing (1 source) - half precision */
6143 static void handle_fp_1src_half(DisasContext
*s
, int opcode
, int rd
, int rn
)
6145 TCGv_ptr fpst
= NULL
;
6146 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
6147 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6150 case 0x0: /* FMOV */
6151 tcg_gen_mov_i32(tcg_res
, tcg_op
);
6153 case 0x1: /* FABS */
6154 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
6156 case 0x2: /* FNEG */
6157 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
6159 case 0x3: /* FSQRT */
6160 fpst
= get_fpstatus_ptr(true);
6161 gen_helper_sqrt_f16(tcg_res
, tcg_op
, fpst
);
6163 case 0x8: /* FRINTN */
6164 case 0x9: /* FRINTP */
6165 case 0xa: /* FRINTM */
6166 case 0xb: /* FRINTZ */
6167 case 0xc: /* FRINTA */
6169 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
6170 fpst
= get_fpstatus_ptr(true);
6172 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6173 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
6175 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6176 tcg_temp_free_i32(tcg_rmode
);
6179 case 0xe: /* FRINTX */
6180 fpst
= get_fpstatus_ptr(true);
6181 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, fpst
);
6183 case 0xf: /* FRINTI */
6184 fpst
= get_fpstatus_ptr(true);
6185 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
6191 write_fp_sreg(s
, rd
, tcg_res
);
6194 tcg_temp_free_ptr(fpst
);
6196 tcg_temp_free_i32(tcg_op
);
6197 tcg_temp_free_i32(tcg_res
);
6200 /* Floating-point data-processing (1 source) - single precision */
6201 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
6203 void (*gen_fpst
)(TCGv_i32
, TCGv_i32
, TCGv_ptr
);
6204 TCGv_i32 tcg_op
, tcg_res
;
6208 tcg_op
= read_fp_sreg(s
, rn
);
6209 tcg_res
= tcg_temp_new_i32();
6212 case 0x0: /* FMOV */
6213 tcg_gen_mov_i32(tcg_res
, tcg_op
);
6215 case 0x1: /* FABS */
6216 gen_helper_vfp_abss(tcg_res
, tcg_op
);
6218 case 0x2: /* FNEG */
6219 gen_helper_vfp_negs(tcg_res
, tcg_op
);
6221 case 0x3: /* FSQRT */
6222 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
6224 case 0x8: /* FRINTN */
6225 case 0x9: /* FRINTP */
6226 case 0xa: /* FRINTM */
6227 case 0xb: /* FRINTZ */
6228 case 0xc: /* FRINTA */
6229 rmode
= arm_rmode_to_sf(opcode
& 7);
6230 gen_fpst
= gen_helper_rints
;
6232 case 0xe: /* FRINTX */
6233 gen_fpst
= gen_helper_rints_exact
;
6235 case 0xf: /* FRINTI */
6236 gen_fpst
= gen_helper_rints
;
6238 case 0x10: /* FRINT32Z */
6239 rmode
= float_round_to_zero
;
6240 gen_fpst
= gen_helper_frint32_s
;
6242 case 0x11: /* FRINT32X */
6243 gen_fpst
= gen_helper_frint32_s
;
6245 case 0x12: /* FRINT64Z */
6246 rmode
= float_round_to_zero
;
6247 gen_fpst
= gen_helper_frint64_s
;
6249 case 0x13: /* FRINT64X */
6250 gen_fpst
= gen_helper_frint64_s
;
6253 g_assert_not_reached();
6256 fpst
= get_fpstatus_ptr(false);
6258 TCGv_i32 tcg_rmode
= tcg_const_i32(rmode
);
6259 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6260 gen_fpst(tcg_res
, tcg_op
, fpst
);
6261 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6262 tcg_temp_free_i32(tcg_rmode
);
6264 gen_fpst(tcg_res
, tcg_op
, fpst
);
6266 tcg_temp_free_ptr(fpst
);
6269 write_fp_sreg(s
, rd
, tcg_res
);
6270 tcg_temp_free_i32(tcg_op
);
6271 tcg_temp_free_i32(tcg_res
);
6274 /* Floating-point data-processing (1 source) - double precision */
6275 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
6277 void (*gen_fpst
)(TCGv_i64
, TCGv_i64
, TCGv_ptr
);
6278 TCGv_i64 tcg_op
, tcg_res
;
6283 case 0x0: /* FMOV */
6284 gen_gvec_fn2(s
, false, rd
, rn
, tcg_gen_gvec_mov
, 0);
6288 tcg_op
= read_fp_dreg(s
, rn
);
6289 tcg_res
= tcg_temp_new_i64();
6292 case 0x1: /* FABS */
6293 gen_helper_vfp_absd(tcg_res
, tcg_op
);
6295 case 0x2: /* FNEG */
6296 gen_helper_vfp_negd(tcg_res
, tcg_op
);
6298 case 0x3: /* FSQRT */
6299 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
6301 case 0x8: /* FRINTN */
6302 case 0x9: /* FRINTP */
6303 case 0xa: /* FRINTM */
6304 case 0xb: /* FRINTZ */
6305 case 0xc: /* FRINTA */
6306 rmode
= arm_rmode_to_sf(opcode
& 7);
6307 gen_fpst
= gen_helper_rintd
;
6309 case 0xe: /* FRINTX */
6310 gen_fpst
= gen_helper_rintd_exact
;
6312 case 0xf: /* FRINTI */
6313 gen_fpst
= gen_helper_rintd
;
6315 case 0x10: /* FRINT32Z */
6316 rmode
= float_round_to_zero
;
6317 gen_fpst
= gen_helper_frint32_d
;
6319 case 0x11: /* FRINT32X */
6320 gen_fpst
= gen_helper_frint32_d
;
6322 case 0x12: /* FRINT64Z */
6323 rmode
= float_round_to_zero
;
6324 gen_fpst
= gen_helper_frint64_d
;
6326 case 0x13: /* FRINT64X */
6327 gen_fpst
= gen_helper_frint64_d
;
6330 g_assert_not_reached();
6333 fpst
= get_fpstatus_ptr(false);
6335 TCGv_i32 tcg_rmode
= tcg_const_i32(rmode
);
6336 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6337 gen_fpst(tcg_res
, tcg_op
, fpst
);
6338 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6339 tcg_temp_free_i32(tcg_rmode
);
6341 gen_fpst(tcg_res
, tcg_op
, fpst
);
6343 tcg_temp_free_ptr(fpst
);
6346 write_fp_dreg(s
, rd
, tcg_res
);
6347 tcg_temp_free_i64(tcg_op
);
6348 tcg_temp_free_i64(tcg_res
);
6351 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
6352 int rd
, int rn
, int dtype
, int ntype
)
6357 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
6359 /* Single to double */
6360 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
6361 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
6362 write_fp_dreg(s
, rd
, tcg_rd
);
6363 tcg_temp_free_i64(tcg_rd
);
6365 /* Single to half */
6366 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
6367 TCGv_i32 ahp
= get_ahp_flag();
6368 TCGv_ptr fpst
= get_fpstatus_ptr(false);
6370 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
6371 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
6372 write_fp_sreg(s
, rd
, tcg_rd
);
6373 tcg_temp_free_i32(tcg_rd
);
6374 tcg_temp_free_i32(ahp
);
6375 tcg_temp_free_ptr(fpst
);
6377 tcg_temp_free_i32(tcg_rn
);
6382 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
6383 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
6385 /* Double to single */
6386 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
6388 TCGv_ptr fpst
= get_fpstatus_ptr(false);
6389 TCGv_i32 ahp
= get_ahp_flag();
6390 /* Double to half */
6391 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
6392 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
6393 tcg_temp_free_ptr(fpst
);
6394 tcg_temp_free_i32(ahp
);
6396 write_fp_sreg(s
, rd
, tcg_rd
);
6397 tcg_temp_free_i32(tcg_rd
);
6398 tcg_temp_free_i64(tcg_rn
);
6403 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
6404 TCGv_ptr tcg_fpst
= get_fpstatus_ptr(false);
6405 TCGv_i32 tcg_ahp
= get_ahp_flag();
6406 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
6408 /* Half to single */
6409 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
6410 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
6411 write_fp_sreg(s
, rd
, tcg_rd
);
6412 tcg_temp_free_i32(tcg_rd
);
6414 /* Half to double */
6415 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
6416 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
6417 write_fp_dreg(s
, rd
, tcg_rd
);
6418 tcg_temp_free_i64(tcg_rd
);
6420 tcg_temp_free_i32(tcg_rn
);
6421 tcg_temp_free_ptr(tcg_fpst
);
6422 tcg_temp_free_i32(tcg_ahp
);
6430 /* Floating point data-processing (1 source)
6431 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
6432 * +---+---+---+-----------+------+---+--------+-----------+------+------+
6433 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
6434 * +---+---+---+-----------+------+---+--------+-----------+------+------+
6436 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
6438 int mos
= extract32(insn
, 29, 3);
6439 int type
= extract32(insn
, 22, 2);
6440 int opcode
= extract32(insn
, 15, 6);
6441 int rn
= extract32(insn
, 5, 5);
6442 int rd
= extract32(insn
, 0, 5);
6445 unallocated_encoding(s
);
6450 case 0x4: case 0x5: case 0x7:
6452 /* FCVT between half, single and double precision */
6453 int dtype
= extract32(opcode
, 0, 2);
6454 if (type
== 2 || dtype
== type
) {
6455 unallocated_encoding(s
);
6458 if (!fp_access_check(s
)) {
6462 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
6466 case 0x10 ... 0x13: /* FRINT{32,64}{X,Z} */
6467 if (type
> 1 || !dc_isar_feature(aa64_frint
, s
)) {
6468 unallocated_encoding(s
);
6475 /* 32-to-32 and 64-to-64 ops */
6478 if (!fp_access_check(s
)) {
6481 handle_fp_1src_single(s
, opcode
, rd
, rn
);
6484 if (!fp_access_check(s
)) {
6487 handle_fp_1src_double(s
, opcode
, rd
, rn
);
6490 if (!dc_isar_feature(aa64_fp16
, s
)) {
6491 unallocated_encoding(s
);
6495 if (!fp_access_check(s
)) {
6498 handle_fp_1src_half(s
, opcode
, rd
, rn
);
6501 unallocated_encoding(s
);
6506 unallocated_encoding(s
);
6511 /* Floating-point data-processing (2 source) - single precision */
6512 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
6513 int rd
, int rn
, int rm
)
6520 tcg_res
= tcg_temp_new_i32();
6521 fpst
= get_fpstatus_ptr(false);
6522 tcg_op1
= read_fp_sreg(s
, rn
);
6523 tcg_op2
= read_fp_sreg(s
, rm
);
6526 case 0x0: /* FMUL */
6527 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6529 case 0x1: /* FDIV */
6530 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6532 case 0x2: /* FADD */
6533 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6535 case 0x3: /* FSUB */
6536 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6538 case 0x4: /* FMAX */
6539 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6541 case 0x5: /* FMIN */
6542 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6544 case 0x6: /* FMAXNM */
6545 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6547 case 0x7: /* FMINNM */
6548 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6550 case 0x8: /* FNMUL */
6551 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6552 gen_helper_vfp_negs(tcg_res
, tcg_res
);
6556 write_fp_sreg(s
, rd
, tcg_res
);
6558 tcg_temp_free_ptr(fpst
);
6559 tcg_temp_free_i32(tcg_op1
);
6560 tcg_temp_free_i32(tcg_op2
);
6561 tcg_temp_free_i32(tcg_res
);
6564 /* Floating-point data-processing (2 source) - double precision */
6565 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
6566 int rd
, int rn
, int rm
)
6573 tcg_res
= tcg_temp_new_i64();
6574 fpst
= get_fpstatus_ptr(false);
6575 tcg_op1
= read_fp_dreg(s
, rn
);
6576 tcg_op2
= read_fp_dreg(s
, rm
);
6579 case 0x0: /* FMUL */
6580 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6582 case 0x1: /* FDIV */
6583 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6585 case 0x2: /* FADD */
6586 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6588 case 0x3: /* FSUB */
6589 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6591 case 0x4: /* FMAX */
6592 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6594 case 0x5: /* FMIN */
6595 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6597 case 0x6: /* FMAXNM */
6598 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6600 case 0x7: /* FMINNM */
6601 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6603 case 0x8: /* FNMUL */
6604 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6605 gen_helper_vfp_negd(tcg_res
, tcg_res
);
6609 write_fp_dreg(s
, rd
, tcg_res
);
6611 tcg_temp_free_ptr(fpst
);
6612 tcg_temp_free_i64(tcg_op1
);
6613 tcg_temp_free_i64(tcg_op2
);
6614 tcg_temp_free_i64(tcg_res
);
6617 /* Floating-point data-processing (2 source) - half precision */
6618 static void handle_fp_2src_half(DisasContext
*s
, int opcode
,
6619 int rd
, int rn
, int rm
)
6626 tcg_res
= tcg_temp_new_i32();
6627 fpst
= get_fpstatus_ptr(true);
6628 tcg_op1
= read_fp_hreg(s
, rn
);
6629 tcg_op2
= read_fp_hreg(s
, rm
);
6632 case 0x0: /* FMUL */
6633 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6635 case 0x1: /* FDIV */
6636 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6638 case 0x2: /* FADD */
6639 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6641 case 0x3: /* FSUB */
6642 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6644 case 0x4: /* FMAX */
6645 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6647 case 0x5: /* FMIN */
6648 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6650 case 0x6: /* FMAXNM */
6651 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6653 case 0x7: /* FMINNM */
6654 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6656 case 0x8: /* FNMUL */
6657 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6658 tcg_gen_xori_i32(tcg_res
, tcg_res
, 0x8000);
6661 g_assert_not_reached();
6664 write_fp_sreg(s
, rd
, tcg_res
);
6666 tcg_temp_free_ptr(fpst
);
6667 tcg_temp_free_i32(tcg_op1
);
6668 tcg_temp_free_i32(tcg_op2
);
6669 tcg_temp_free_i32(tcg_res
);
6672 /* Floating point data-processing (2 source)
6673 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6674 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6675 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
6676 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6678 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
6680 int mos
= extract32(insn
, 29, 3);
6681 int type
= extract32(insn
, 22, 2);
6682 int rd
= extract32(insn
, 0, 5);
6683 int rn
= extract32(insn
, 5, 5);
6684 int rm
= extract32(insn
, 16, 5);
6685 int opcode
= extract32(insn
, 12, 4);
6687 if (opcode
> 8 || mos
) {
6688 unallocated_encoding(s
);
6694 if (!fp_access_check(s
)) {
6697 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
6700 if (!fp_access_check(s
)) {
6703 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
6706 if (!dc_isar_feature(aa64_fp16
, s
)) {
6707 unallocated_encoding(s
);
6710 if (!fp_access_check(s
)) {
6713 handle_fp_2src_half(s
, opcode
, rd
, rn
, rm
);
6716 unallocated_encoding(s
);
6720 /* Floating-point data-processing (3 source) - single precision */
6721 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
6722 int rd
, int rn
, int rm
, int ra
)
6724 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6725 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6726 TCGv_ptr fpst
= get_fpstatus_ptr(false);
6728 tcg_op1
= read_fp_sreg(s
, rn
);
6729 tcg_op2
= read_fp_sreg(s
, rm
);
6730 tcg_op3
= read_fp_sreg(s
, ra
);
6732 /* These are fused multiply-add, and must be done as one
6733 * floating point operation with no rounding between the
6734 * multiplication and addition steps.
6735 * NB that doing the negations here as separate steps is
6736 * correct : an input NaN should come out with its sign bit
6737 * flipped if it is a negated-input.
6740 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
6744 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
6747 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6749 write_fp_sreg(s
, rd
, tcg_res
);
6751 tcg_temp_free_ptr(fpst
);
6752 tcg_temp_free_i32(tcg_op1
);
6753 tcg_temp_free_i32(tcg_op2
);
6754 tcg_temp_free_i32(tcg_op3
);
6755 tcg_temp_free_i32(tcg_res
);
6758 /* Floating-point data-processing (3 source) - double precision */
6759 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
6760 int rd
, int rn
, int rm
, int ra
)
6762 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
6763 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6764 TCGv_ptr fpst
= get_fpstatus_ptr(false);
6766 tcg_op1
= read_fp_dreg(s
, rn
);
6767 tcg_op2
= read_fp_dreg(s
, rm
);
6768 tcg_op3
= read_fp_dreg(s
, ra
);
6770 /* These are fused multiply-add, and must be done as one
6771 * floating point operation with no rounding between the
6772 * multiplication and addition steps.
6773 * NB that doing the negations here as separate steps is
6774 * correct : an input NaN should come out with its sign bit
6775 * flipped if it is a negated-input.
6778 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
6782 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
6785 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6787 write_fp_dreg(s
, rd
, tcg_res
);
6789 tcg_temp_free_ptr(fpst
);
6790 tcg_temp_free_i64(tcg_op1
);
6791 tcg_temp_free_i64(tcg_op2
);
6792 tcg_temp_free_i64(tcg_op3
);
6793 tcg_temp_free_i64(tcg_res
);
6796 /* Floating-point data-processing (3 source) - half precision */
6797 static void handle_fp_3src_half(DisasContext
*s
, bool o0
, bool o1
,
6798 int rd
, int rn
, int rm
, int ra
)
6800 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6801 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6802 TCGv_ptr fpst
= get_fpstatus_ptr(true);
6804 tcg_op1
= read_fp_hreg(s
, rn
);
6805 tcg_op2
= read_fp_hreg(s
, rm
);
6806 tcg_op3
= read_fp_hreg(s
, ra
);
6808 /* These are fused multiply-add, and must be done as one
6809 * floating point operation with no rounding between the
6810 * multiplication and addition steps.
6811 * NB that doing the negations here as separate steps is
6812 * correct : an input NaN should come out with its sign bit
6813 * flipped if it is a negated-input.
6816 tcg_gen_xori_i32(tcg_op3
, tcg_op3
, 0x8000);
6820 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
6823 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6825 write_fp_sreg(s
, rd
, tcg_res
);
6827 tcg_temp_free_ptr(fpst
);
6828 tcg_temp_free_i32(tcg_op1
);
6829 tcg_temp_free_i32(tcg_op2
);
6830 tcg_temp_free_i32(tcg_op3
);
6831 tcg_temp_free_i32(tcg_res
);
6834 /* Floating point data-processing (3 source)
6835 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
6836 * +---+---+---+-----------+------+----+------+----+------+------+------+
6837 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
6838 * +---+---+---+-----------+------+----+------+----+------+------+------+
6840 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
6842 int mos
= extract32(insn
, 29, 3);
6843 int type
= extract32(insn
, 22, 2);
6844 int rd
= extract32(insn
, 0, 5);
6845 int rn
= extract32(insn
, 5, 5);
6846 int ra
= extract32(insn
, 10, 5);
6847 int rm
= extract32(insn
, 16, 5);
6848 bool o0
= extract32(insn
, 15, 1);
6849 bool o1
= extract32(insn
, 21, 1);
6852 unallocated_encoding(s
);
6858 if (!fp_access_check(s
)) {
6861 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6864 if (!fp_access_check(s
)) {
6867 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6870 if (!dc_isar_feature(aa64_fp16
, s
)) {
6871 unallocated_encoding(s
);
6874 if (!fp_access_check(s
)) {
6877 handle_fp_3src_half(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6880 unallocated_encoding(s
);
6884 /* Floating point immediate
6885 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
6886 * +---+---+---+-----------+------+---+------------+-------+------+------+
6887 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
6888 * +---+---+---+-----------+------+---+------------+-------+------+------+
6890 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
6892 int rd
= extract32(insn
, 0, 5);
6893 int imm5
= extract32(insn
, 5, 5);
6894 int imm8
= extract32(insn
, 13, 8);
6895 int type
= extract32(insn
, 22, 2);
6896 int mos
= extract32(insn
, 29, 3);
6902 unallocated_encoding(s
);
6915 if (dc_isar_feature(aa64_fp16
, s
)) {
6920 unallocated_encoding(s
);
6924 if (!fp_access_check(s
)) {
6928 imm
= vfp_expand_imm(sz
, imm8
);
6930 tcg_res
= tcg_const_i64(imm
);
6931 write_fp_dreg(s
, rd
, tcg_res
);
6932 tcg_temp_free_i64(tcg_res
);
6935 /* Handle floating point <=> fixed point conversions. Note that we can
6936 * also deal with fp <=> integer conversions as a special case (scale == 64)
6937 * OPTME: consider handling that special case specially or at least skipping
6938 * the call to scalbn in the helpers for zero shifts.
6940 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
6941 bool itof
, int rmode
, int scale
, int sf
, int type
)
6943 bool is_signed
= !(opcode
& 1);
6944 TCGv_ptr tcg_fpstatus
;
6945 TCGv_i32 tcg_shift
, tcg_single
;
6946 TCGv_i64 tcg_double
;
6948 tcg_fpstatus
= get_fpstatus_ptr(type
== 3);
6950 tcg_shift
= tcg_const_i32(64 - scale
);
6953 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
6955 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
6958 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
6960 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
6963 tcg_int
= tcg_extend
;
6967 case 1: /* float64 */
6968 tcg_double
= tcg_temp_new_i64();
6970 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
6971 tcg_shift
, tcg_fpstatus
);
6973 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
6974 tcg_shift
, tcg_fpstatus
);
6976 write_fp_dreg(s
, rd
, tcg_double
);
6977 tcg_temp_free_i64(tcg_double
);
6980 case 0: /* float32 */
6981 tcg_single
= tcg_temp_new_i32();
6983 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
6984 tcg_shift
, tcg_fpstatus
);
6986 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
6987 tcg_shift
, tcg_fpstatus
);
6989 write_fp_sreg(s
, rd
, tcg_single
);
6990 tcg_temp_free_i32(tcg_single
);
6993 case 3: /* float16 */
6994 tcg_single
= tcg_temp_new_i32();
6996 gen_helper_vfp_sqtoh(tcg_single
, tcg_int
,
6997 tcg_shift
, tcg_fpstatus
);
6999 gen_helper_vfp_uqtoh(tcg_single
, tcg_int
,
7000 tcg_shift
, tcg_fpstatus
);
7002 write_fp_sreg(s
, rd
, tcg_single
);
7003 tcg_temp_free_i32(tcg_single
);
7007 g_assert_not_reached();
7010 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
7013 if (extract32(opcode
, 2, 1)) {
7014 /* There are too many rounding modes to all fit into rmode,
7015 * so FCVTA[US] is a special case.
7017 rmode
= FPROUNDING_TIEAWAY
;
7020 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
7022 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
7025 case 1: /* float64 */
7026 tcg_double
= read_fp_dreg(s
, rn
);
7029 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
7030 tcg_shift
, tcg_fpstatus
);
7032 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
7033 tcg_shift
, tcg_fpstatus
);
7037 gen_helper_vfp_tould(tcg_int
, tcg_double
,
7038 tcg_shift
, tcg_fpstatus
);
7040 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
7041 tcg_shift
, tcg_fpstatus
);
7045 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
7047 tcg_temp_free_i64(tcg_double
);
7050 case 0: /* float32 */
7051 tcg_single
= read_fp_sreg(s
, rn
);
7054 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
7055 tcg_shift
, tcg_fpstatus
);
7057 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
7058 tcg_shift
, tcg_fpstatus
);
7061 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
7063 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
7064 tcg_shift
, tcg_fpstatus
);
7066 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
7067 tcg_shift
, tcg_fpstatus
);
7069 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
7070 tcg_temp_free_i32(tcg_dest
);
7072 tcg_temp_free_i32(tcg_single
);
7075 case 3: /* float16 */
7076 tcg_single
= read_fp_sreg(s
, rn
);
7079 gen_helper_vfp_tosqh(tcg_int
, tcg_single
,
7080 tcg_shift
, tcg_fpstatus
);
7082 gen_helper_vfp_touqh(tcg_int
, tcg_single
,
7083 tcg_shift
, tcg_fpstatus
);
7086 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
7088 gen_helper_vfp_toslh(tcg_dest
, tcg_single
,
7089 tcg_shift
, tcg_fpstatus
);
7091 gen_helper_vfp_toulh(tcg_dest
, tcg_single
,
7092 tcg_shift
, tcg_fpstatus
);
7094 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
7095 tcg_temp_free_i32(tcg_dest
);
7097 tcg_temp_free_i32(tcg_single
);
7101 g_assert_not_reached();
7104 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
7105 tcg_temp_free_i32(tcg_rmode
);
7108 tcg_temp_free_ptr(tcg_fpstatus
);
7109 tcg_temp_free_i32(tcg_shift
);
7112 /* Floating point <-> fixed point conversions
7113 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
7114 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
7115 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
7116 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
7118 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
7120 int rd
= extract32(insn
, 0, 5);
7121 int rn
= extract32(insn
, 5, 5);
7122 int scale
= extract32(insn
, 10, 6);
7123 int opcode
= extract32(insn
, 16, 3);
7124 int rmode
= extract32(insn
, 19, 2);
7125 int type
= extract32(insn
, 22, 2);
7126 bool sbit
= extract32(insn
, 29, 1);
7127 bool sf
= extract32(insn
, 31, 1);
7130 if (sbit
|| (!sf
&& scale
< 32)) {
7131 unallocated_encoding(s
);
7136 case 0: /* float32 */
7137 case 1: /* float64 */
7139 case 3: /* float16 */
7140 if (dc_isar_feature(aa64_fp16
, s
)) {
7145 unallocated_encoding(s
);
7149 switch ((rmode
<< 3) | opcode
) {
7150 case 0x2: /* SCVTF */
7151 case 0x3: /* UCVTF */
7154 case 0x18: /* FCVTZS */
7155 case 0x19: /* FCVTZU */
7159 unallocated_encoding(s
);
7163 if (!fp_access_check(s
)) {
7167 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
7170 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
7172 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
7173 * without conversion.
7177 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
7183 tmp
= tcg_temp_new_i64();
7184 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
7185 write_fp_dreg(s
, rd
, tmp
);
7186 tcg_temp_free_i64(tmp
);
7190 write_fp_dreg(s
, rd
, tcg_rn
);
7193 /* 64 bit to top half. */
7194 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
7195 clear_vec_high(s
, true, rd
);
7199 tmp
= tcg_temp_new_i64();
7200 tcg_gen_ext16u_i64(tmp
, tcg_rn
);
7201 write_fp_dreg(s
, rd
, tmp
);
7202 tcg_temp_free_i64(tmp
);
7205 g_assert_not_reached();
7208 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
7213 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
7217 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
7220 /* 64 bits from top half */
7221 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
7225 tcg_gen_ld16u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_16
));
7228 g_assert_not_reached();
7233 static void handle_fjcvtzs(DisasContext
*s
, int rd
, int rn
)
7235 TCGv_i64 t
= read_fp_dreg(s
, rn
);
7236 TCGv_ptr fpstatus
= get_fpstatus_ptr(false);
7238 gen_helper_fjcvtzs(t
, t
, fpstatus
);
7240 tcg_temp_free_ptr(fpstatus
);
7242 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), t
);
7243 tcg_gen_extrh_i64_i32(cpu_ZF
, t
);
7244 tcg_gen_movi_i32(cpu_CF
, 0);
7245 tcg_gen_movi_i32(cpu_NF
, 0);
7246 tcg_gen_movi_i32(cpu_VF
, 0);
7248 tcg_temp_free_i64(t
);
7251 /* Floating point <-> integer conversions
7252 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
7253 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
7254 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
7255 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
7257 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
7259 int rd
= extract32(insn
, 0, 5);
7260 int rn
= extract32(insn
, 5, 5);
7261 int opcode
= extract32(insn
, 16, 3);
7262 int rmode
= extract32(insn
, 19, 2);
7263 int type
= extract32(insn
, 22, 2);
7264 bool sbit
= extract32(insn
, 29, 1);
7265 bool sf
= extract32(insn
, 31, 1);
7269 goto do_unallocated
;
7277 case 4: /* FCVTAS */
7278 case 5: /* FCVTAU */
7280 goto do_unallocated
;
7283 case 0: /* FCVT[NPMZ]S */
7284 case 1: /* FCVT[NPMZ]U */
7286 case 0: /* float32 */
7287 case 1: /* float64 */
7289 case 3: /* float16 */
7290 if (!dc_isar_feature(aa64_fp16
, s
)) {
7291 goto do_unallocated
;
7295 goto do_unallocated
;
7297 if (!fp_access_check(s
)) {
7300 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
7304 switch (sf
<< 7 | type
<< 5 | rmode
<< 3 | opcode
) {
7305 case 0b01100110: /* FMOV half <-> 32-bit int */
7307 case 0b11100110: /* FMOV half <-> 64-bit int */
7309 if (!dc_isar_feature(aa64_fp16
, s
)) {
7310 goto do_unallocated
;
7313 case 0b00000110: /* FMOV 32-bit */
7315 case 0b10100110: /* FMOV 64-bit */
7317 case 0b11001110: /* FMOV top half of 128-bit */
7319 if (!fp_access_check(s
)) {
7323 handle_fmov(s
, rd
, rn
, type
, itof
);
7326 case 0b00111110: /* FJCVTZS */
7327 if (!dc_isar_feature(aa64_jscvt
, s
)) {
7328 goto do_unallocated
;
7329 } else if (fp_access_check(s
)) {
7330 handle_fjcvtzs(s
, rd
, rn
);
7336 unallocated_encoding(s
);
7343 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
7344 * 31 30 29 28 25 24 0
7345 * +---+---+---+---------+-----------------------------+
7346 * | | 0 | | 1 1 1 1 | |
7347 * +---+---+---+---------+-----------------------------+
7349 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
7351 if (extract32(insn
, 24, 1)) {
7352 /* Floating point data-processing (3 source) */
7353 disas_fp_3src(s
, insn
);
7354 } else if (extract32(insn
, 21, 1) == 0) {
7355 /* Floating point to fixed point conversions */
7356 disas_fp_fixed_conv(s
, insn
);
7358 switch (extract32(insn
, 10, 2)) {
7360 /* Floating point conditional compare */
7361 disas_fp_ccomp(s
, insn
);
7364 /* Floating point data-processing (2 source) */
7365 disas_fp_2src(s
, insn
);
7368 /* Floating point conditional select */
7369 disas_fp_csel(s
, insn
);
7372 switch (ctz32(extract32(insn
, 12, 4))) {
7373 case 0: /* [15:12] == xxx1 */
7374 /* Floating point immediate */
7375 disas_fp_imm(s
, insn
);
7377 case 1: /* [15:12] == xx10 */
7378 /* Floating point compare */
7379 disas_fp_compare(s
, insn
);
7381 case 2: /* [15:12] == x100 */
7382 /* Floating point data-processing (1 source) */
7383 disas_fp_1src(s
, insn
);
7385 case 3: /* [15:12] == 1000 */
7386 unallocated_encoding(s
);
7388 default: /* [15:12] == 0000 */
7389 /* Floating point <-> integer conversions */
7390 disas_fp_int_conv(s
, insn
);
7398 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
7401 /* Extract 64 bits from the middle of two concatenated 64 bit
7402 * vector register slices left:right. The extracted bits start
7403 * at 'pos' bits into the right (least significant) side.
7404 * We return the result in tcg_right, and guarantee not to
7407 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
7408 assert(pos
> 0 && pos
< 64);
7410 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
7411 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
7412 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
7414 tcg_temp_free_i64(tcg_tmp
);
7418 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
7419 * +---+---+-------------+-----+---+------+---+------+---+------+------+
7420 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
7421 * +---+---+-------------+-----+---+------+---+------+---+------+------+
7423 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
7425 int is_q
= extract32(insn
, 30, 1);
7426 int op2
= extract32(insn
, 22, 2);
7427 int imm4
= extract32(insn
, 11, 4);
7428 int rm
= extract32(insn
, 16, 5);
7429 int rn
= extract32(insn
, 5, 5);
7430 int rd
= extract32(insn
, 0, 5);
7431 int pos
= imm4
<< 3;
7432 TCGv_i64 tcg_resl
, tcg_resh
;
7434 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
7435 unallocated_encoding(s
);
7439 if (!fp_access_check(s
)) {
7443 tcg_resh
= tcg_temp_new_i64();
7444 tcg_resl
= tcg_temp_new_i64();
7446 /* Vd gets bits starting at pos bits into Vm:Vn. This is
7447 * either extracting 128 bits from a 128:128 concatenation, or
7448 * extracting 64 bits from a 64:64 concatenation.
7451 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
7453 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
7454 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
7462 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
7463 EltPosns
*elt
= eltposns
;
7470 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
7472 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
7475 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
7476 tcg_hh
= tcg_temp_new_i64();
7477 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
7478 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
7479 tcg_temp_free_i64(tcg_hh
);
7483 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7484 tcg_temp_free_i64(tcg_resl
);
7486 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7488 tcg_temp_free_i64(tcg_resh
);
7489 clear_vec_high(s
, is_q
, rd
);
7493 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
7494 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
7495 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
7496 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
7498 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
7500 int op2
= extract32(insn
, 22, 2);
7501 int is_q
= extract32(insn
, 30, 1);
7502 int rm
= extract32(insn
, 16, 5);
7503 int rn
= extract32(insn
, 5, 5);
7504 int rd
= extract32(insn
, 0, 5);
7505 int is_tblx
= extract32(insn
, 12, 1);
7506 int len
= extract32(insn
, 13, 2);
7507 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
7508 TCGv_i32 tcg_regno
, tcg_numregs
;
7511 unallocated_encoding(s
);
7515 if (!fp_access_check(s
)) {
7519 /* This does a table lookup: for every byte element in the input
7520 * we index into a table formed from up to four vector registers,
7521 * and then the output is the result of the lookups. Our helper
7522 * function does the lookup operation for a single 64 bit part of
7525 tcg_resl
= tcg_temp_new_i64();
7529 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7531 tcg_gen_movi_i64(tcg_resl
, 0);
7535 tcg_resh
= tcg_temp_new_i64();
7537 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7539 tcg_gen_movi_i64(tcg_resh
, 0);
7543 tcg_idx
= tcg_temp_new_i64();
7544 tcg_regno
= tcg_const_i32(rn
);
7545 tcg_numregs
= tcg_const_i32(len
+ 1);
7546 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
7547 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
7548 tcg_regno
, tcg_numregs
);
7550 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
7551 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
7552 tcg_regno
, tcg_numregs
);
7554 tcg_temp_free_i64(tcg_idx
);
7555 tcg_temp_free_i32(tcg_regno
);
7556 tcg_temp_free_i32(tcg_numregs
);
7558 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7559 tcg_temp_free_i64(tcg_resl
);
7562 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7563 tcg_temp_free_i64(tcg_resh
);
7565 clear_vec_high(s
, is_q
, rd
);
7569 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
7570 * +---+---+-------------+------+---+------+---+------------------+------+
7571 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
7572 * +---+---+-------------+------+---+------+---+------------------+------+
7574 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
7576 int rd
= extract32(insn
, 0, 5);
7577 int rn
= extract32(insn
, 5, 5);
7578 int rm
= extract32(insn
, 16, 5);
7579 int size
= extract32(insn
, 22, 2);
7580 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
7581 * bit 2 indicates 1 vs 2 variant of the insn.
7583 int opcode
= extract32(insn
, 12, 2);
7584 bool part
= extract32(insn
, 14, 1);
7585 bool is_q
= extract32(insn
, 30, 1);
7586 int esize
= 8 << size
;
7588 int datasize
= is_q
? 128 : 64;
7589 int elements
= datasize
/ esize
;
7590 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
7592 if (opcode
== 0 || (size
== 3 && !is_q
)) {
7593 unallocated_encoding(s
);
7597 if (!fp_access_check(s
)) {
7601 tcg_resl
= tcg_const_i64(0);
7602 tcg_resh
= is_q
? tcg_const_i64(0) : NULL
;
7603 tcg_res
= tcg_temp_new_i64();
7605 for (i
= 0; i
< elements
; i
++) {
7607 case 1: /* UZP1/2 */
7609 int midpoint
= elements
/ 2;
7611 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
7613 read_vec_element(s
, tcg_res
, rm
,
7614 2 * (i
- midpoint
) + part
, size
);
7618 case 2: /* TRN1/2 */
7620 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
7622 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
7625 case 3: /* ZIP1/2 */
7627 int base
= part
* elements
/ 2;
7629 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
7631 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
7636 g_assert_not_reached();
7641 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
7642 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
7644 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
7645 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
7649 tcg_temp_free_i64(tcg_res
);
7651 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7652 tcg_temp_free_i64(tcg_resl
);
7655 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7656 tcg_temp_free_i64(tcg_resh
);
7658 clear_vec_high(s
, is_q
, rd
);
7662 * do_reduction_op helper
7664 * This mirrors the Reduce() pseudocode in the ARM ARM. It is
7665 * important for correct NaN propagation that we do these
7666 * operations in exactly the order specified by the pseudocode.
7668 * This is a recursive function, TCG temps should be freed by the
7669 * calling function once it is done with the values.
7671 static TCGv_i32
do_reduction_op(DisasContext
*s
, int fpopcode
, int rn
,
7672 int esize
, int size
, int vmap
, TCGv_ptr fpst
)
7674 if (esize
== size
) {
7676 MemOp msize
= esize
== 16 ? MO_16
: MO_32
;
7679 /* We should have one register left here */
7680 assert(ctpop8(vmap
) == 1);
7681 element
= ctz32(vmap
);
7682 assert(element
< 8);
7684 tcg_elem
= tcg_temp_new_i32();
7685 read_vec_element_i32(s
, tcg_elem
, rn
, element
, msize
);
7688 int bits
= size
/ 2;
7689 int shift
= ctpop8(vmap
) / 2;
7690 int vmap_lo
= (vmap
>> shift
) & vmap
;
7691 int vmap_hi
= (vmap
& ~vmap_lo
);
7692 TCGv_i32 tcg_hi
, tcg_lo
, tcg_res
;
7694 tcg_hi
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_hi
, fpst
);
7695 tcg_lo
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_lo
, fpst
);
7696 tcg_res
= tcg_temp_new_i32();
7699 case 0x0c: /* fmaxnmv half-precision */
7700 gen_helper_advsimd_maxnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7702 case 0x0f: /* fmaxv half-precision */
7703 gen_helper_advsimd_maxh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7705 case 0x1c: /* fminnmv half-precision */
7706 gen_helper_advsimd_minnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7708 case 0x1f: /* fminv half-precision */
7709 gen_helper_advsimd_minh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7711 case 0x2c: /* fmaxnmv */
7712 gen_helper_vfp_maxnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7714 case 0x2f: /* fmaxv */
7715 gen_helper_vfp_maxs(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7717 case 0x3c: /* fminnmv */
7718 gen_helper_vfp_minnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7720 case 0x3f: /* fminv */
7721 gen_helper_vfp_mins(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7724 g_assert_not_reached();
7727 tcg_temp_free_i32(tcg_hi
);
7728 tcg_temp_free_i32(tcg_lo
);
7733 /* AdvSIMD across lanes
7734 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7735 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7736 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7737 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7739 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
7741 int rd
= extract32(insn
, 0, 5);
7742 int rn
= extract32(insn
, 5, 5);
7743 int size
= extract32(insn
, 22, 2);
7744 int opcode
= extract32(insn
, 12, 5);
7745 bool is_q
= extract32(insn
, 30, 1);
7746 bool is_u
= extract32(insn
, 29, 1);
7748 bool is_min
= false;
7752 TCGv_i64 tcg_res
, tcg_elt
;
7755 case 0x1b: /* ADDV */
7757 unallocated_encoding(s
);
7761 case 0x3: /* SADDLV, UADDLV */
7762 case 0xa: /* SMAXV, UMAXV */
7763 case 0x1a: /* SMINV, UMINV */
7764 if (size
== 3 || (size
== 2 && !is_q
)) {
7765 unallocated_encoding(s
);
7769 case 0xc: /* FMAXNMV, FMINNMV */
7770 case 0xf: /* FMAXV, FMINV */
7771 /* Bit 1 of size field encodes min vs max and the actual size
7772 * depends on the encoding of the U bit. If not set (and FP16
7773 * enabled) then we do half-precision float instead of single
7776 is_min
= extract32(size
, 1, 1);
7778 if (!is_u
&& dc_isar_feature(aa64_fp16
, s
)) {
7780 } else if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
7781 unallocated_encoding(s
);
7788 unallocated_encoding(s
);
7792 if (!fp_access_check(s
)) {
7797 elements
= (is_q
? 128 : 64) / esize
;
7799 tcg_res
= tcg_temp_new_i64();
7800 tcg_elt
= tcg_temp_new_i64();
7802 /* These instructions operate across all lanes of a vector
7803 * to produce a single result. We can guarantee that a 64
7804 * bit intermediate is sufficient:
7805 * + for [US]ADDLV the maximum element size is 32 bits, and
7806 * the result type is 64 bits
7807 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
7808 * same as the element size, which is 32 bits at most
7809 * For the integer operations we can choose to work at 64
7810 * or 32 bits and truncate at the end; for simplicity
7811 * we use 64 bits always. The floating point
7812 * ops do require 32 bit intermediates, though.
7815 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
7817 for (i
= 1; i
< elements
; i
++) {
7818 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
7821 case 0x03: /* SADDLV / UADDLV */
7822 case 0x1b: /* ADDV */
7823 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
7825 case 0x0a: /* SMAXV / UMAXV */
7827 tcg_gen_umax_i64(tcg_res
, tcg_res
, tcg_elt
);
7829 tcg_gen_smax_i64(tcg_res
, tcg_res
, tcg_elt
);
7832 case 0x1a: /* SMINV / UMINV */
7834 tcg_gen_umin_i64(tcg_res
, tcg_res
, tcg_elt
);
7836 tcg_gen_smin_i64(tcg_res
, tcg_res
, tcg_elt
);
7840 g_assert_not_reached();
7845 /* Floating point vector reduction ops which work across 32
7846 * bit (single) or 16 bit (half-precision) intermediates.
7847 * Note that correct NaN propagation requires that we do these
7848 * operations in exactly the order specified by the pseudocode.
7850 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
7851 int fpopcode
= opcode
| is_min
<< 4 | is_u
<< 5;
7852 int vmap
= (1 << elements
) - 1;
7853 TCGv_i32 tcg_res32
= do_reduction_op(s
, fpopcode
, rn
, esize
,
7854 (is_q
? 128 : 64), vmap
, fpst
);
7855 tcg_gen_extu_i32_i64(tcg_res
, tcg_res32
);
7856 tcg_temp_free_i32(tcg_res32
);
7857 tcg_temp_free_ptr(fpst
);
7860 tcg_temp_free_i64(tcg_elt
);
7862 /* Now truncate the result to the width required for the final output */
7863 if (opcode
== 0x03) {
7864 /* SADDLV, UADDLV: result is 2*esize */
7870 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
7873 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
7876 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
7881 g_assert_not_reached();
7884 write_fp_dreg(s
, rd
, tcg_res
);
7885 tcg_temp_free_i64(tcg_res
);
7888 /* DUP (Element, Vector)
7890 * 31 30 29 21 20 16 15 10 9 5 4 0
7891 * +---+---+-------------------+--------+-------------+------+------+
7892 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7893 * +---+---+-------------------+--------+-------------+------+------+
7895 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7897 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
7900 int size
= ctz32(imm5
);
7903 if (size
> 3 || (size
== 3 && !is_q
)) {
7904 unallocated_encoding(s
);
7908 if (!fp_access_check(s
)) {
7912 index
= imm5
>> (size
+ 1);
7913 tcg_gen_gvec_dup_mem(size
, vec_full_reg_offset(s
, rd
),
7914 vec_reg_offset(s
, rn
, index
, size
),
7915 is_q
? 16 : 8, vec_full_reg_size(s
));
7918 /* DUP (element, scalar)
7919 * 31 21 20 16 15 10 9 5 4 0
7920 * +-----------------------+--------+-------------+------+------+
7921 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7922 * +-----------------------+--------+-------------+------+------+
7924 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
7927 int size
= ctz32(imm5
);
7932 unallocated_encoding(s
);
7936 if (!fp_access_check(s
)) {
7940 index
= imm5
>> (size
+ 1);
7942 /* This instruction just extracts the specified element and
7943 * zero-extends it into the bottom of the destination register.
7945 tmp
= tcg_temp_new_i64();
7946 read_vec_element(s
, tmp
, rn
, index
, size
);
7947 write_fp_dreg(s
, rd
, tmp
);
7948 tcg_temp_free_i64(tmp
);
7953 * 31 30 29 21 20 16 15 10 9 5 4 0
7954 * +---+---+-------------------+--------+-------------+------+------+
7955 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
7956 * +---+---+-------------------+--------+-------------+------+------+
7958 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7960 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
7963 int size
= ctz32(imm5
);
7964 uint32_t dofs
, oprsz
, maxsz
;
7966 if (size
> 3 || ((size
== 3) && !is_q
)) {
7967 unallocated_encoding(s
);
7971 if (!fp_access_check(s
)) {
7975 dofs
= vec_full_reg_offset(s
, rd
);
7976 oprsz
= is_q
? 16 : 8;
7977 maxsz
= vec_full_reg_size(s
);
7979 tcg_gen_gvec_dup_i64(size
, dofs
, oprsz
, maxsz
, cpu_reg(s
, rn
));
7984 * 31 21 20 16 15 14 11 10 9 5 4 0
7985 * +-----------------------+--------+------------+---+------+------+
7986 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7987 * +-----------------------+--------+------------+---+------+------+
7989 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7990 * index: encoded in imm5<4:size+1>
7992 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
7995 int size
= ctz32(imm5
);
7996 int src_index
, dst_index
;
8000 unallocated_encoding(s
);
8004 if (!fp_access_check(s
)) {
8008 dst_index
= extract32(imm5
, 1+size
, 5);
8009 src_index
= extract32(imm4
, size
, 4);
8011 tmp
= tcg_temp_new_i64();
8013 read_vec_element(s
, tmp
, rn
, src_index
, size
);
8014 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
8016 tcg_temp_free_i64(tmp
);
8018 /* INS is considered a 128-bit write for SVE. */
8019 clear_vec_high(s
, true, rd
);
8025 * 31 21 20 16 15 10 9 5 4 0
8026 * +-----------------------+--------+-------------+------+------+
8027 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
8028 * +-----------------------+--------+-------------+------+------+
8030 * size: encoded in imm5 (see ARM ARM LowestSetBit())
8031 * index: encoded in imm5<4:size+1>
8033 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
8035 int size
= ctz32(imm5
);
8039 unallocated_encoding(s
);
8043 if (!fp_access_check(s
)) {
8047 idx
= extract32(imm5
, 1 + size
, 4 - size
);
8048 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
8050 /* INS is considered a 128-bit write for SVE. */
8051 clear_vec_high(s
, true, rd
);
8058 * 31 30 29 21 20 16 15 12 10 9 5 4 0
8059 * +---+---+-------------------+--------+-------------+------+------+
8060 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
8061 * +---+---+-------------------+--------+-------------+------+------+
8063 * U: unsigned when set
8064 * size: encoded in imm5 (see ARM ARM LowestSetBit())
8066 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
8067 int rn
, int rd
, int imm5
)
8069 int size
= ctz32(imm5
);
8073 /* Check for UnallocatedEncodings */
8075 if (size
> 2 || (size
== 2 && !is_q
)) {
8076 unallocated_encoding(s
);
8081 || (size
< 3 && is_q
)
8082 || (size
== 3 && !is_q
)) {
8083 unallocated_encoding(s
);
8088 if (!fp_access_check(s
)) {
8092 element
= extract32(imm5
, 1+size
, 4);
8094 tcg_rd
= cpu_reg(s
, rd
);
8095 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
8096 if (is_signed
&& !is_q
) {
8097 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
8102 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
8103 * +---+---+----+-----------------+------+---+------+---+------+------+
8104 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
8105 * +---+---+----+-----------------+------+---+------+---+------+------+
8107 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
8109 int rd
= extract32(insn
, 0, 5);
8110 int rn
= extract32(insn
, 5, 5);
8111 int imm4
= extract32(insn
, 11, 4);
8112 int op
= extract32(insn
, 29, 1);
8113 int is_q
= extract32(insn
, 30, 1);
8114 int imm5
= extract32(insn
, 16, 5);
8119 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
8121 unallocated_encoding(s
);
8126 /* DUP (element - vector) */
8127 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
8131 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
8136 handle_simd_insg(s
, rd
, rn
, imm5
);
8138 unallocated_encoding(s
);
8143 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
8144 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
8147 unallocated_encoding(s
);
8153 /* AdvSIMD modified immediate
8154 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
8155 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
8156 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
8157 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
8159 * There are a number of operations that can be carried out here:
8160 * MOVI - move (shifted) imm into register
8161 * MVNI - move inverted (shifted) imm into register
8162 * ORR - bitwise OR of (shifted) imm with register
8163 * BIC - bitwise clear of (shifted) imm with register
8164 * With ARMv8.2 we also have:
8165 * FMOV half-precision
8167 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
8169 int rd
= extract32(insn
, 0, 5);
8170 int cmode
= extract32(insn
, 12, 4);
8171 int cmode_3_1
= extract32(cmode
, 1, 3);
8172 int cmode_0
= extract32(cmode
, 0, 1);
8173 int o2
= extract32(insn
, 11, 1);
8174 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
8175 bool is_neg
= extract32(insn
, 29, 1);
8176 bool is_q
= extract32(insn
, 30, 1);
8179 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
8180 /* Check for FMOV (vector, immediate) - half-precision */
8181 if (!(dc_isar_feature(aa64_fp16
, s
) && o2
&& cmode
== 0xf)) {
8182 unallocated_encoding(s
);
8187 if (!fp_access_check(s
)) {
8191 /* See AdvSIMDExpandImm() in ARM ARM */
8192 switch (cmode_3_1
) {
8193 case 0: /* Replicate(Zeros(24):imm8, 2) */
8194 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
8195 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
8196 case 3: /* Replicate(imm8:Zeros(24), 2) */
8198 int shift
= cmode_3_1
* 8;
8199 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
8202 case 4: /* Replicate(Zeros(8):imm8, 4) */
8203 case 5: /* Replicate(imm8:Zeros(8), 4) */
8205 int shift
= (cmode_3_1
& 0x1) * 8;
8206 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
8211 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
8212 imm
= (abcdefgh
<< 16) | 0xffff;
8214 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
8215 imm
= (abcdefgh
<< 8) | 0xff;
8217 imm
= bitfield_replicate(imm
, 32);
8220 if (!cmode_0
&& !is_neg
) {
8221 imm
= bitfield_replicate(abcdefgh
, 8);
8222 } else if (!cmode_0
&& is_neg
) {
8225 for (i
= 0; i
< 8; i
++) {
8226 if ((abcdefgh
) & (1 << i
)) {
8227 imm
|= 0xffULL
<< (i
* 8);
8230 } else if (cmode_0
) {
8232 imm
= (abcdefgh
& 0x3f) << 48;
8233 if (abcdefgh
& 0x80) {
8234 imm
|= 0x8000000000000000ULL
;
8236 if (abcdefgh
& 0x40) {
8237 imm
|= 0x3fc0000000000000ULL
;
8239 imm
|= 0x4000000000000000ULL
;
8243 /* FMOV (vector, immediate) - half-precision */
8244 imm
= vfp_expand_imm(MO_16
, abcdefgh
);
8245 /* now duplicate across the lanes */
8246 imm
= bitfield_replicate(imm
, 16);
8248 imm
= (abcdefgh
& 0x3f) << 19;
8249 if (abcdefgh
& 0x80) {
8252 if (abcdefgh
& 0x40) {
8263 fprintf(stderr
, "%s: cmode_3_1: %x\n", __func__
, cmode_3_1
);
8264 g_assert_not_reached();
8267 if (cmode_3_1
!= 7 && is_neg
) {
8271 if (!((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9)) {
8272 /* MOVI or MVNI, with MVNI negation handled above. */
8273 tcg_gen_gvec_dup_imm(MO_64
, vec_full_reg_offset(s
, rd
), is_q
? 16 : 8,
8274 vec_full_reg_size(s
), imm
);
8276 /* ORR or BIC, with BIC negation to AND handled above. */
8278 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_andi
, MO_64
);
8280 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_ori
, MO_64
);
8285 /* AdvSIMD scalar copy
8286 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
8287 * +-----+----+-----------------+------+---+------+---+------+------+
8288 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
8289 * +-----+----+-----------------+------+---+------+---+------+------+
8291 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
8293 int rd
= extract32(insn
, 0, 5);
8294 int rn
= extract32(insn
, 5, 5);
8295 int imm4
= extract32(insn
, 11, 4);
8296 int imm5
= extract32(insn
, 16, 5);
8297 int op
= extract32(insn
, 29, 1);
8299 if (op
!= 0 || imm4
!= 0) {
8300 unallocated_encoding(s
);
8304 /* DUP (element, scalar) */
8305 handle_simd_dupes(s
, rd
, rn
, imm5
);
8308 /* AdvSIMD scalar pairwise
8309 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
8310 * +-----+---+-----------+------+-----------+--------+-----+------+------+
8311 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
8312 * +-----+---+-----------+------+-----------+--------+-----+------+------+
8314 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
8316 int u
= extract32(insn
, 29, 1);
8317 int size
= extract32(insn
, 22, 2);
8318 int opcode
= extract32(insn
, 12, 5);
8319 int rn
= extract32(insn
, 5, 5);
8320 int rd
= extract32(insn
, 0, 5);
8323 /* For some ops (the FP ones), size[1] is part of the encoding.
8324 * For ADDP strictly it is not but size[1] is always 1 for valid
8327 opcode
|= (extract32(size
, 1, 1) << 5);
8330 case 0x3b: /* ADDP */
8331 if (u
|| size
!= 3) {
8332 unallocated_encoding(s
);
8335 if (!fp_access_check(s
)) {
8341 case 0xc: /* FMAXNMP */
8342 case 0xd: /* FADDP */
8343 case 0xf: /* FMAXP */
8344 case 0x2c: /* FMINNMP */
8345 case 0x2f: /* FMINP */
8346 /* FP op, size[0] is 32 or 64 bit*/
8348 if (!dc_isar_feature(aa64_fp16
, s
)) {
8349 unallocated_encoding(s
);
8355 size
= extract32(size
, 0, 1) ? MO_64
: MO_32
;
8358 if (!fp_access_check(s
)) {
8362 fpst
= get_fpstatus_ptr(size
== MO_16
);
8365 unallocated_encoding(s
);
8369 if (size
== MO_64
) {
8370 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8371 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8372 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8374 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
8375 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
8378 case 0x3b: /* ADDP */
8379 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
8381 case 0xc: /* FMAXNMP */
8382 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8384 case 0xd: /* FADDP */
8385 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8387 case 0xf: /* FMAXP */
8388 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8390 case 0x2c: /* FMINNMP */
8391 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8393 case 0x2f: /* FMINP */
8394 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8397 g_assert_not_reached();
8400 write_fp_dreg(s
, rd
, tcg_res
);
8402 tcg_temp_free_i64(tcg_op1
);
8403 tcg_temp_free_i64(tcg_op2
);
8404 tcg_temp_free_i64(tcg_res
);
8406 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8407 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8408 TCGv_i32 tcg_res
= tcg_temp_new_i32();
8410 read_vec_element_i32(s
, tcg_op1
, rn
, 0, size
);
8411 read_vec_element_i32(s
, tcg_op2
, rn
, 1, size
);
8413 if (size
== MO_16
) {
8415 case 0xc: /* FMAXNMP */
8416 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8418 case 0xd: /* FADDP */
8419 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8421 case 0xf: /* FMAXP */
8422 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8424 case 0x2c: /* FMINNMP */
8425 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8427 case 0x2f: /* FMINP */
8428 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8431 g_assert_not_reached();
8435 case 0xc: /* FMAXNMP */
8436 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8438 case 0xd: /* FADDP */
8439 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8441 case 0xf: /* FMAXP */
8442 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8444 case 0x2c: /* FMINNMP */
8445 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8447 case 0x2f: /* FMINP */
8448 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8451 g_assert_not_reached();
8455 write_fp_sreg(s
, rd
, tcg_res
);
8457 tcg_temp_free_i32(tcg_op1
);
8458 tcg_temp_free_i32(tcg_op2
);
8459 tcg_temp_free_i32(tcg_res
);
8463 tcg_temp_free_ptr(fpst
);
8468 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
8470 * This code is handles the common shifting code and is used by both
8471 * the vector and scalar code.
8473 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
8474 TCGv_i64 tcg_rnd
, bool accumulate
,
8475 bool is_u
, int size
, int shift
)
8477 bool extended_result
= false;
8478 bool round
= tcg_rnd
!= NULL
;
8480 TCGv_i64 tcg_src_hi
;
8482 if (round
&& size
== 3) {
8483 extended_result
= true;
8484 ext_lshift
= 64 - shift
;
8485 tcg_src_hi
= tcg_temp_new_i64();
8486 } else if (shift
== 64) {
8487 if (!accumulate
&& is_u
) {
8488 /* result is zero */
8489 tcg_gen_movi_i64(tcg_res
, 0);
8494 /* Deal with the rounding step */
8496 if (extended_result
) {
8497 TCGv_i64 tcg_zero
= tcg_const_i64(0);
8499 /* take care of sign extending tcg_res */
8500 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
8501 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
8502 tcg_src
, tcg_src_hi
,
8505 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
8509 tcg_temp_free_i64(tcg_zero
);
8511 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
8515 /* Now do the shift right */
8516 if (round
&& extended_result
) {
8517 /* extended case, >64 bit precision required */
8518 if (ext_lshift
== 0) {
8519 /* special case, only high bits matter */
8520 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
8522 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
8523 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
8524 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
8529 /* essentially shifting in 64 zeros */
8530 tcg_gen_movi_i64(tcg_src
, 0);
8532 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
8536 /* effectively extending the sign-bit */
8537 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
8539 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
8545 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
8547 tcg_gen_mov_i64(tcg_res
, tcg_src
);
8550 if (extended_result
) {
8551 tcg_temp_free_i64(tcg_src_hi
);
8555 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
8556 static void handle_scalar_simd_shri(DisasContext
*s
,
8557 bool is_u
, int immh
, int immb
,
8558 int opcode
, int rn
, int rd
)
8561 int immhb
= immh
<< 3 | immb
;
8562 int shift
= 2 * (8 << size
) - immhb
;
8563 bool accumulate
= false;
8565 bool insert
= false;
8570 if (!extract32(immh
, 3, 1)) {
8571 unallocated_encoding(s
);
8575 if (!fp_access_check(s
)) {
8580 case 0x02: /* SSRA / USRA (accumulate) */
8583 case 0x04: /* SRSHR / URSHR (rounding) */
8586 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8587 accumulate
= round
= true;
8589 case 0x08: /* SRI */
8595 uint64_t round_const
= 1ULL << (shift
- 1);
8596 tcg_round
= tcg_const_i64(round_const
);
8601 tcg_rn
= read_fp_dreg(s
, rn
);
8602 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
8605 /* shift count same as element size is valid but does nothing;
8606 * special case to avoid potential shift by 64.
8608 int esize
= 8 << size
;
8609 if (shift
!= esize
) {
8610 tcg_gen_shri_i64(tcg_rn
, tcg_rn
, shift
);
8611 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, 0, esize
- shift
);
8614 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8615 accumulate
, is_u
, size
, shift
);
8618 write_fp_dreg(s
, rd
, tcg_rd
);
8620 tcg_temp_free_i64(tcg_rn
);
8621 tcg_temp_free_i64(tcg_rd
);
8623 tcg_temp_free_i64(tcg_round
);
8627 /* SHL/SLI - Scalar shift left */
8628 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
8629 int immh
, int immb
, int opcode
,
8632 int size
= 32 - clz32(immh
) - 1;
8633 int immhb
= immh
<< 3 | immb
;
8634 int shift
= immhb
- (8 << size
);
8635 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8636 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8638 if (!extract32(immh
, 3, 1)) {
8639 unallocated_encoding(s
);
8643 if (!fp_access_check(s
)) {
8647 tcg_rn
= read_fp_dreg(s
, rn
);
8648 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
8651 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, shift
, 64 - shift
);
8653 tcg_gen_shli_i64(tcg_rd
, tcg_rn
, shift
);
8656 write_fp_dreg(s
, rd
, tcg_rd
);
8658 tcg_temp_free_i64(tcg_rn
);
8659 tcg_temp_free_i64(tcg_rd
);
8662 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
8663 * (signed/unsigned) narrowing */
8664 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
8665 bool is_u_shift
, bool is_u_narrow
,
8666 int immh
, int immb
, int opcode
,
8669 int immhb
= immh
<< 3 | immb
;
8670 int size
= 32 - clz32(immh
) - 1;
8671 int esize
= 8 << size
;
8672 int shift
= (2 * esize
) - immhb
;
8673 int elements
= is_scalar
? 1 : (64 / esize
);
8674 bool round
= extract32(opcode
, 0, 1);
8675 MemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
8676 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
8677 TCGv_i32 tcg_rd_narrowed
;
8680 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
8681 { gen_helper_neon_narrow_sat_s8
,
8682 gen_helper_neon_unarrow_sat8
},
8683 { gen_helper_neon_narrow_sat_s16
,
8684 gen_helper_neon_unarrow_sat16
},
8685 { gen_helper_neon_narrow_sat_s32
,
8686 gen_helper_neon_unarrow_sat32
},
8689 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
8690 gen_helper_neon_narrow_sat_u8
,
8691 gen_helper_neon_narrow_sat_u16
,
8692 gen_helper_neon_narrow_sat_u32
,
8695 NeonGenNarrowEnvFn
*narrowfn
;
8701 if (extract32(immh
, 3, 1)) {
8702 unallocated_encoding(s
);
8706 if (!fp_access_check(s
)) {
8711 narrowfn
= unsigned_narrow_fns
[size
];
8713 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
8716 tcg_rn
= tcg_temp_new_i64();
8717 tcg_rd
= tcg_temp_new_i64();
8718 tcg_rd_narrowed
= tcg_temp_new_i32();
8719 tcg_final
= tcg_const_i64(0);
8722 uint64_t round_const
= 1ULL << (shift
- 1);
8723 tcg_round
= tcg_const_i64(round_const
);
8728 for (i
= 0; i
< elements
; i
++) {
8729 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
8730 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8731 false, is_u_shift
, size
+1, shift
);
8732 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
8733 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
8734 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
8738 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
8740 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
8744 tcg_temp_free_i64(tcg_round
);
8746 tcg_temp_free_i64(tcg_rn
);
8747 tcg_temp_free_i64(tcg_rd
);
8748 tcg_temp_free_i32(tcg_rd_narrowed
);
8749 tcg_temp_free_i64(tcg_final
);
8751 clear_vec_high(s
, is_q
, rd
);
8754 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
8755 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
8756 bool src_unsigned
, bool dst_unsigned
,
8757 int immh
, int immb
, int rn
, int rd
)
8759 int immhb
= immh
<< 3 | immb
;
8760 int size
= 32 - clz32(immh
) - 1;
8761 int shift
= immhb
- (8 << size
);
8765 assert(!(scalar
&& is_q
));
8768 if (!is_q
&& extract32(immh
, 3, 1)) {
8769 unallocated_encoding(s
);
8773 /* Since we use the variable-shift helpers we must
8774 * replicate the shift count into each element of
8775 * the tcg_shift value.
8779 shift
|= shift
<< 8;
8782 shift
|= shift
<< 16;
8788 g_assert_not_reached();
8792 if (!fp_access_check(s
)) {
8797 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
8798 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
8799 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
8800 { NULL
, gen_helper_neon_qshl_u64
},
8802 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
8803 int maxpass
= is_q
? 2 : 1;
8805 for (pass
= 0; pass
< maxpass
; pass
++) {
8806 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8808 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8809 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8810 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
8812 tcg_temp_free_i64(tcg_op
);
8814 tcg_temp_free_i64(tcg_shift
);
8815 clear_vec_high(s
, is_q
, rd
);
8817 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
8818 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
8820 { gen_helper_neon_qshl_s8
,
8821 gen_helper_neon_qshl_s16
,
8822 gen_helper_neon_qshl_s32
},
8823 { gen_helper_neon_qshlu_s8
,
8824 gen_helper_neon_qshlu_s16
,
8825 gen_helper_neon_qshlu_s32
}
8827 { NULL
, NULL
, NULL
},
8828 { gen_helper_neon_qshl_u8
,
8829 gen_helper_neon_qshl_u16
,
8830 gen_helper_neon_qshl_u32
}
8833 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
8834 MemOp memop
= scalar
? size
: MO_32
;
8835 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
8837 for (pass
= 0; pass
< maxpass
; pass
++) {
8838 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8840 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
8841 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8845 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
8848 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
8853 g_assert_not_reached();
8855 write_fp_sreg(s
, rd
, tcg_op
);
8857 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
8860 tcg_temp_free_i32(tcg_op
);
8862 tcg_temp_free_i32(tcg_shift
);
8865 clear_vec_high(s
, is_q
, rd
);
8870 /* Common vector code for handling integer to FP conversion */
8871 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
8872 int elements
, int is_signed
,
8873 int fracbits
, int size
)
8875 TCGv_ptr tcg_fpst
= get_fpstatus_ptr(size
== MO_16
);
8876 TCGv_i32 tcg_shift
= NULL
;
8878 MemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
8881 if (fracbits
|| size
== MO_64
) {
8882 tcg_shift
= tcg_const_i32(fracbits
);
8885 if (size
== MO_64
) {
8886 TCGv_i64 tcg_int64
= tcg_temp_new_i64();
8887 TCGv_i64 tcg_double
= tcg_temp_new_i64();
8889 for (pass
= 0; pass
< elements
; pass
++) {
8890 read_vec_element(s
, tcg_int64
, rn
, pass
, mop
);
8893 gen_helper_vfp_sqtod(tcg_double
, tcg_int64
,
8894 tcg_shift
, tcg_fpst
);
8896 gen_helper_vfp_uqtod(tcg_double
, tcg_int64
,
8897 tcg_shift
, tcg_fpst
);
8899 if (elements
== 1) {
8900 write_fp_dreg(s
, rd
, tcg_double
);
8902 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
8906 tcg_temp_free_i64(tcg_int64
);
8907 tcg_temp_free_i64(tcg_double
);
8910 TCGv_i32 tcg_int32
= tcg_temp_new_i32();
8911 TCGv_i32 tcg_float
= tcg_temp_new_i32();
8913 for (pass
= 0; pass
< elements
; pass
++) {
8914 read_vec_element_i32(s
, tcg_int32
, rn
, pass
, mop
);
8920 gen_helper_vfp_sltos(tcg_float
, tcg_int32
,
8921 tcg_shift
, tcg_fpst
);
8923 gen_helper_vfp_ultos(tcg_float
, tcg_int32
,
8924 tcg_shift
, tcg_fpst
);
8928 gen_helper_vfp_sitos(tcg_float
, tcg_int32
, tcg_fpst
);
8930 gen_helper_vfp_uitos(tcg_float
, tcg_int32
, tcg_fpst
);
8937 gen_helper_vfp_sltoh(tcg_float
, tcg_int32
,
8938 tcg_shift
, tcg_fpst
);
8940 gen_helper_vfp_ultoh(tcg_float
, tcg_int32
,
8941 tcg_shift
, tcg_fpst
);
8945 gen_helper_vfp_sitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8947 gen_helper_vfp_uitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8952 g_assert_not_reached();
8955 if (elements
== 1) {
8956 write_fp_sreg(s
, rd
, tcg_float
);
8958 write_vec_element_i32(s
, tcg_float
, rd
, pass
, size
);
8962 tcg_temp_free_i32(tcg_int32
);
8963 tcg_temp_free_i32(tcg_float
);
8966 tcg_temp_free_ptr(tcg_fpst
);
8968 tcg_temp_free_i32(tcg_shift
);
8971 clear_vec_high(s
, elements
<< size
== 16, rd
);
8974 /* UCVTF/SCVTF - Integer to FP conversion */
8975 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
8976 bool is_q
, bool is_u
,
8977 int immh
, int immb
, int opcode
,
8980 int size
, elements
, fracbits
;
8981 int immhb
= immh
<< 3 | immb
;
8985 if (!is_scalar
&& !is_q
) {
8986 unallocated_encoding(s
);
8989 } else if (immh
& 4) {
8991 } else if (immh
& 2) {
8993 if (!dc_isar_feature(aa64_fp16
, s
)) {
8994 unallocated_encoding(s
);
8998 /* immh == 0 would be a failure of the decode logic */
8999 g_assert(immh
== 1);
9000 unallocated_encoding(s
);
9007 elements
= (8 << is_q
) >> size
;
9009 fracbits
= (16 << size
) - immhb
;
9011 if (!fp_access_check(s
)) {
9015 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
9018 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
9019 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
9020 bool is_q
, bool is_u
,
9021 int immh
, int immb
, int rn
, int rd
)
9023 int immhb
= immh
<< 3 | immb
;
9024 int pass
, size
, fracbits
;
9025 TCGv_ptr tcg_fpstatus
;
9026 TCGv_i32 tcg_rmode
, tcg_shift
;
9030 if (!is_scalar
&& !is_q
) {
9031 unallocated_encoding(s
);
9034 } else if (immh
& 0x4) {
9036 } else if (immh
& 0x2) {
9038 if (!dc_isar_feature(aa64_fp16
, s
)) {
9039 unallocated_encoding(s
);
9043 /* Should have split out AdvSIMD modified immediate earlier. */
9045 unallocated_encoding(s
);
9049 if (!fp_access_check(s
)) {
9053 assert(!(is_scalar
&& is_q
));
9055 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
9056 tcg_fpstatus
= get_fpstatus_ptr(size
== MO_16
);
9057 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
9058 fracbits
= (16 << size
) - immhb
;
9059 tcg_shift
= tcg_const_i32(fracbits
);
9061 if (size
== MO_64
) {
9062 int maxpass
= is_scalar
? 1 : 2;
9064 for (pass
= 0; pass
< maxpass
; pass
++) {
9065 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9067 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9069 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
9071 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
9073 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
9074 tcg_temp_free_i64(tcg_op
);
9076 clear_vec_high(s
, is_q
, rd
);
9078 void (*fn
)(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
9079 int maxpass
= is_scalar
? 1 : ((8 << is_q
) >> size
);
9084 fn
= gen_helper_vfp_touhh
;
9086 fn
= gen_helper_vfp_toshh
;
9091 fn
= gen_helper_vfp_touls
;
9093 fn
= gen_helper_vfp_tosls
;
9097 g_assert_not_reached();
9100 for (pass
= 0; pass
< maxpass
; pass
++) {
9101 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9103 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
9104 fn(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
9106 write_fp_sreg(s
, rd
, tcg_op
);
9108 write_vec_element_i32(s
, tcg_op
, rd
, pass
, size
);
9110 tcg_temp_free_i32(tcg_op
);
9113 clear_vec_high(s
, is_q
, rd
);
9117 tcg_temp_free_ptr(tcg_fpstatus
);
9118 tcg_temp_free_i32(tcg_shift
);
9119 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
9120 tcg_temp_free_i32(tcg_rmode
);
9123 /* AdvSIMD scalar shift by immediate
9124 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
9125 * +-----+---+-------------+------+------+--------+---+------+------+
9126 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
9127 * +-----+---+-------------+------+------+--------+---+------+------+
9129 * This is the scalar version so it works on a fixed sized registers
9131 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
9133 int rd
= extract32(insn
, 0, 5);
9134 int rn
= extract32(insn
, 5, 5);
9135 int opcode
= extract32(insn
, 11, 5);
9136 int immb
= extract32(insn
, 16, 3);
9137 int immh
= extract32(insn
, 19, 4);
9138 bool is_u
= extract32(insn
, 29, 1);
9141 unallocated_encoding(s
);
9146 case 0x08: /* SRI */
9148 unallocated_encoding(s
);
9152 case 0x00: /* SSHR / USHR */
9153 case 0x02: /* SSRA / USRA */
9154 case 0x04: /* SRSHR / URSHR */
9155 case 0x06: /* SRSRA / URSRA */
9156 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
9158 case 0x0a: /* SHL / SLI */
9159 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
9161 case 0x1c: /* SCVTF, UCVTF */
9162 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
9165 case 0x10: /* SQSHRUN, SQSHRUN2 */
9166 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
9168 unallocated_encoding(s
);
9171 handle_vec_simd_sqshrn(s
, true, false, false, true,
9172 immh
, immb
, opcode
, rn
, rd
);
9174 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
9175 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
9176 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
9177 immh
, immb
, opcode
, rn
, rd
);
9179 case 0xc: /* SQSHLU */
9181 unallocated_encoding(s
);
9184 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
9186 case 0xe: /* SQSHL, UQSHL */
9187 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
9189 case 0x1f: /* FCVTZS, FCVTZU */
9190 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
9193 unallocated_encoding(s
);
9198 /* AdvSIMD scalar three different
9199 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
9200 * +-----+---+-----------+------+---+------+--------+-----+------+------+
9201 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
9202 * +-----+---+-----------+------+---+------+--------+-----+------+------+
9204 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
9206 bool is_u
= extract32(insn
, 29, 1);
9207 int size
= extract32(insn
, 22, 2);
9208 int opcode
= extract32(insn
, 12, 4);
9209 int rm
= extract32(insn
, 16, 5);
9210 int rn
= extract32(insn
, 5, 5);
9211 int rd
= extract32(insn
, 0, 5);
9214 unallocated_encoding(s
);
9219 case 0x9: /* SQDMLAL, SQDMLAL2 */
9220 case 0xb: /* SQDMLSL, SQDMLSL2 */
9221 case 0xd: /* SQDMULL, SQDMULL2 */
9222 if (size
== 0 || size
== 3) {
9223 unallocated_encoding(s
);
9228 unallocated_encoding(s
);
9232 if (!fp_access_check(s
)) {
9237 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9238 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9239 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9241 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
9242 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
9244 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
9245 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
9248 case 0xd: /* SQDMULL, SQDMULL2 */
9250 case 0xb: /* SQDMLSL, SQDMLSL2 */
9251 tcg_gen_neg_i64(tcg_res
, tcg_res
);
9253 case 0x9: /* SQDMLAL, SQDMLAL2 */
9254 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
9255 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
9259 g_assert_not_reached();
9262 write_fp_dreg(s
, rd
, tcg_res
);
9264 tcg_temp_free_i64(tcg_op1
);
9265 tcg_temp_free_i64(tcg_op2
);
9266 tcg_temp_free_i64(tcg_res
);
9268 TCGv_i32 tcg_op1
= read_fp_hreg(s
, rn
);
9269 TCGv_i32 tcg_op2
= read_fp_hreg(s
, rm
);
9270 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9272 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
9273 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
9276 case 0xd: /* SQDMULL, SQDMULL2 */
9278 case 0xb: /* SQDMLSL, SQDMLSL2 */
9279 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
9281 case 0x9: /* SQDMLAL, SQDMLAL2 */
9283 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
9284 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
9285 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
9287 tcg_temp_free_i64(tcg_op3
);
9291 g_assert_not_reached();
9294 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
9295 write_fp_dreg(s
, rd
, tcg_res
);
9297 tcg_temp_free_i32(tcg_op1
);
9298 tcg_temp_free_i32(tcg_op2
);
9299 tcg_temp_free_i64(tcg_res
);
9303 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
9304 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
9306 /* Handle 64x64->64 opcodes which are shared between the scalar
9307 * and vector 3-same groups. We cover every opcode where size == 3
9308 * is valid in either the three-reg-same (integer, not pairwise)
9309 * or scalar-three-reg-same groups.
9314 case 0x1: /* SQADD */
9316 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9318 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9321 case 0x5: /* SQSUB */
9323 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9325 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9328 case 0x6: /* CMGT, CMHI */
9329 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
9330 * We implement this using setcond (test) and then negating.
9332 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
9334 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
9335 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
9337 case 0x7: /* CMGE, CMHS */
9338 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
9340 case 0x11: /* CMTST, CMEQ */
9345 gen_cmtst_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9347 case 0x8: /* SSHL, USHL */
9349 gen_ushl_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9351 gen_sshl_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9354 case 0x9: /* SQSHL, UQSHL */
9356 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9358 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9361 case 0xa: /* SRSHL, URSHL */
9363 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
9365 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
9368 case 0xb: /* SQRSHL, UQRSHL */
9370 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9372 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9375 case 0x10: /* ADD, SUB */
9377 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9379 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9383 g_assert_not_reached();
9387 /* Handle the 3-same-operands float operations; shared by the scalar
9388 * and vector encodings. The caller must filter out any encodings
9389 * not allocated for the encoding it is dealing with.
9391 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
9392 int fpopcode
, int rd
, int rn
, int rm
)
9395 TCGv_ptr fpst
= get_fpstatus_ptr(false);
9397 for (pass
= 0; pass
< elements
; pass
++) {
9400 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9401 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9402 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9404 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
9405 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
9408 case 0x39: /* FMLS */
9409 /* As usual for ARM, separate negation for fused multiply-add */
9410 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
9412 case 0x19: /* FMLA */
9413 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9414 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
9417 case 0x18: /* FMAXNM */
9418 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9420 case 0x1a: /* FADD */
9421 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9423 case 0x1b: /* FMULX */
9424 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9426 case 0x1c: /* FCMEQ */
9427 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9429 case 0x1e: /* FMAX */
9430 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9432 case 0x1f: /* FRECPS */
9433 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9435 case 0x38: /* FMINNM */
9436 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9438 case 0x3a: /* FSUB */
9439 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9441 case 0x3e: /* FMIN */
9442 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9444 case 0x3f: /* FRSQRTS */
9445 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9447 case 0x5b: /* FMUL */
9448 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9450 case 0x5c: /* FCMGE */
9451 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9453 case 0x5d: /* FACGE */
9454 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9456 case 0x5f: /* FDIV */
9457 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9459 case 0x7a: /* FABD */
9460 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9461 gen_helper_vfp_absd(tcg_res
, tcg_res
);
9463 case 0x7c: /* FCMGT */
9464 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9466 case 0x7d: /* FACGT */
9467 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9470 g_assert_not_reached();
9473 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9475 tcg_temp_free_i64(tcg_res
);
9476 tcg_temp_free_i64(tcg_op1
);
9477 tcg_temp_free_i64(tcg_op2
);
9480 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9481 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9482 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9484 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
9485 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
9488 case 0x39: /* FMLS */
9489 /* As usual for ARM, separate negation for fused multiply-add */
9490 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
9492 case 0x19: /* FMLA */
9493 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9494 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
9497 case 0x1a: /* FADD */
9498 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9500 case 0x1b: /* FMULX */
9501 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9503 case 0x1c: /* FCMEQ */
9504 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9506 case 0x1e: /* FMAX */
9507 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9509 case 0x1f: /* FRECPS */
9510 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9512 case 0x18: /* FMAXNM */
9513 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9515 case 0x38: /* FMINNM */
9516 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9518 case 0x3a: /* FSUB */
9519 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9521 case 0x3e: /* FMIN */
9522 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9524 case 0x3f: /* FRSQRTS */
9525 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9527 case 0x5b: /* FMUL */
9528 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9530 case 0x5c: /* FCMGE */
9531 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9533 case 0x5d: /* FACGE */
9534 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9536 case 0x5f: /* FDIV */
9537 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9539 case 0x7a: /* FABD */
9540 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9541 gen_helper_vfp_abss(tcg_res
, tcg_res
);
9543 case 0x7c: /* FCMGT */
9544 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9546 case 0x7d: /* FACGT */
9547 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9550 g_assert_not_reached();
9553 if (elements
== 1) {
9554 /* scalar single so clear high part */
9555 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
9557 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
9558 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
9559 tcg_temp_free_i64(tcg_tmp
);
9561 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9564 tcg_temp_free_i32(tcg_res
);
9565 tcg_temp_free_i32(tcg_op1
);
9566 tcg_temp_free_i32(tcg_op2
);
9570 tcg_temp_free_ptr(fpst
);
9572 clear_vec_high(s
, elements
* (size
? 8 : 4) > 8, rd
);
9575 /* AdvSIMD scalar three same
9576 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
9577 * +-----+---+-----------+------+---+------+--------+---+------+------+
9578 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
9579 * +-----+---+-----------+------+---+------+--------+---+------+------+
9581 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
9583 int rd
= extract32(insn
, 0, 5);
9584 int rn
= extract32(insn
, 5, 5);
9585 int opcode
= extract32(insn
, 11, 5);
9586 int rm
= extract32(insn
, 16, 5);
9587 int size
= extract32(insn
, 22, 2);
9588 bool u
= extract32(insn
, 29, 1);
9591 if (opcode
>= 0x18) {
9592 /* Floating point: U, size[1] and opcode indicate operation */
9593 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
9595 case 0x1b: /* FMULX */
9596 case 0x1f: /* FRECPS */
9597 case 0x3f: /* FRSQRTS */
9598 case 0x5d: /* FACGE */
9599 case 0x7d: /* FACGT */
9600 case 0x1c: /* FCMEQ */
9601 case 0x5c: /* FCMGE */
9602 case 0x7c: /* FCMGT */
9603 case 0x7a: /* FABD */
9606 unallocated_encoding(s
);
9610 if (!fp_access_check(s
)) {
9614 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
9619 case 0x1: /* SQADD, UQADD */
9620 case 0x5: /* SQSUB, UQSUB */
9621 case 0x9: /* SQSHL, UQSHL */
9622 case 0xb: /* SQRSHL, UQRSHL */
9624 case 0x8: /* SSHL, USHL */
9625 case 0xa: /* SRSHL, URSHL */
9626 case 0x6: /* CMGT, CMHI */
9627 case 0x7: /* CMGE, CMHS */
9628 case 0x11: /* CMTST, CMEQ */
9629 case 0x10: /* ADD, SUB (vector) */
9631 unallocated_encoding(s
);
9635 case 0x16: /* SQDMULH, SQRDMULH (vector) */
9636 if (size
!= 1 && size
!= 2) {
9637 unallocated_encoding(s
);
9642 unallocated_encoding(s
);
9646 if (!fp_access_check(s
)) {
9650 tcg_rd
= tcg_temp_new_i64();
9653 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
9654 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
9656 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
9657 tcg_temp_free_i64(tcg_rn
);
9658 tcg_temp_free_i64(tcg_rm
);
9660 /* Do a single operation on the lowest element in the vector.
9661 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
9662 * no side effects for all these operations.
9663 * OPTME: special-purpose helpers would avoid doing some
9664 * unnecessary work in the helper for the 8 and 16 bit cases.
9666 NeonGenTwoOpEnvFn
*genenvfn
;
9667 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9668 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
9669 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
9671 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
9672 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
9675 case 0x1: /* SQADD, UQADD */
9677 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9678 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
9679 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
9680 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
9682 genenvfn
= fns
[size
][u
];
9685 case 0x5: /* SQSUB, UQSUB */
9687 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9688 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
9689 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
9690 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
9692 genenvfn
= fns
[size
][u
];
9695 case 0x9: /* SQSHL, UQSHL */
9697 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9698 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
9699 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
9700 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
9702 genenvfn
= fns
[size
][u
];
9705 case 0xb: /* SQRSHL, UQRSHL */
9707 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9708 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
9709 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
9710 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
9712 genenvfn
= fns
[size
][u
];
9715 case 0x16: /* SQDMULH, SQRDMULH */
9717 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
9718 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
9719 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
9721 assert(size
== 1 || size
== 2);
9722 genenvfn
= fns
[size
- 1][u
];
9726 g_assert_not_reached();
9729 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
9730 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
9731 tcg_temp_free_i32(tcg_rd32
);
9732 tcg_temp_free_i32(tcg_rn
);
9733 tcg_temp_free_i32(tcg_rm
);
9736 write_fp_dreg(s
, rd
, tcg_rd
);
9738 tcg_temp_free_i64(tcg_rd
);
9741 /* AdvSIMD scalar three same FP16
9742 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
9743 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9744 * | 0 1 | U | 1 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
9745 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9746 * v: 0101 1110 0100 0000 0000 0100 0000 0000 => 5e400400
9747 * m: 1101 1111 0110 0000 1100 0100 0000 0000 => df60c400
9749 static void disas_simd_scalar_three_reg_same_fp16(DisasContext
*s
,
9752 int rd
= extract32(insn
, 0, 5);
9753 int rn
= extract32(insn
, 5, 5);
9754 int opcode
= extract32(insn
, 11, 3);
9755 int rm
= extract32(insn
, 16, 5);
9756 bool u
= extract32(insn
, 29, 1);
9757 bool a
= extract32(insn
, 23, 1);
9758 int fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
9765 case 0x03: /* FMULX */
9766 case 0x04: /* FCMEQ (reg) */
9767 case 0x07: /* FRECPS */
9768 case 0x0f: /* FRSQRTS */
9769 case 0x14: /* FCMGE (reg) */
9770 case 0x15: /* FACGE */
9771 case 0x1a: /* FABD */
9772 case 0x1c: /* FCMGT (reg) */
9773 case 0x1d: /* FACGT */
9776 unallocated_encoding(s
);
9780 if (!dc_isar_feature(aa64_fp16
, s
)) {
9781 unallocated_encoding(s
);
9784 if (!fp_access_check(s
)) {
9788 fpst
= get_fpstatus_ptr(true);
9790 tcg_op1
= read_fp_hreg(s
, rn
);
9791 tcg_op2
= read_fp_hreg(s
, rm
);
9792 tcg_res
= tcg_temp_new_i32();
9795 case 0x03: /* FMULX */
9796 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9798 case 0x04: /* FCMEQ (reg) */
9799 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9801 case 0x07: /* FRECPS */
9802 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9804 case 0x0f: /* FRSQRTS */
9805 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9807 case 0x14: /* FCMGE (reg) */
9808 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9810 case 0x15: /* FACGE */
9811 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9813 case 0x1a: /* FABD */
9814 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9815 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
9817 case 0x1c: /* FCMGT (reg) */
9818 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9820 case 0x1d: /* FACGT */
9821 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9824 g_assert_not_reached();
9827 write_fp_sreg(s
, rd
, tcg_res
);
9830 tcg_temp_free_i32(tcg_res
);
9831 tcg_temp_free_i32(tcg_op1
);
9832 tcg_temp_free_i32(tcg_op2
);
9833 tcg_temp_free_ptr(fpst
);
9836 /* AdvSIMD scalar three same extra
9837 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
9838 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9839 * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
9840 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9842 static void disas_simd_scalar_three_reg_same_extra(DisasContext
*s
,
9845 int rd
= extract32(insn
, 0, 5);
9846 int rn
= extract32(insn
, 5, 5);
9847 int opcode
= extract32(insn
, 11, 4);
9848 int rm
= extract32(insn
, 16, 5);
9849 int size
= extract32(insn
, 22, 2);
9850 bool u
= extract32(insn
, 29, 1);
9851 TCGv_i32 ele1
, ele2
, ele3
;
9855 switch (u
* 16 + opcode
) {
9856 case 0x10: /* SQRDMLAH (vector) */
9857 case 0x11: /* SQRDMLSH (vector) */
9858 if (size
!= 1 && size
!= 2) {
9859 unallocated_encoding(s
);
9862 feature
= dc_isar_feature(aa64_rdm
, s
);
9865 unallocated_encoding(s
);
9869 unallocated_encoding(s
);
9872 if (!fp_access_check(s
)) {
9876 /* Do a single operation on the lowest element in the vector.
9877 * We use the standard Neon helpers and rely on 0 OP 0 == 0
9878 * with no side effects for all these operations.
9879 * OPTME: special-purpose helpers would avoid doing some
9880 * unnecessary work in the helper for the 16 bit cases.
9882 ele1
= tcg_temp_new_i32();
9883 ele2
= tcg_temp_new_i32();
9884 ele3
= tcg_temp_new_i32();
9886 read_vec_element_i32(s
, ele1
, rn
, 0, size
);
9887 read_vec_element_i32(s
, ele2
, rm
, 0, size
);
9888 read_vec_element_i32(s
, ele3
, rd
, 0, size
);
9891 case 0x0: /* SQRDMLAH */
9893 gen_helper_neon_qrdmlah_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9895 gen_helper_neon_qrdmlah_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9898 case 0x1: /* SQRDMLSH */
9900 gen_helper_neon_qrdmlsh_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9902 gen_helper_neon_qrdmlsh_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9906 g_assert_not_reached();
9908 tcg_temp_free_i32(ele1
);
9909 tcg_temp_free_i32(ele2
);
9911 res
= tcg_temp_new_i64();
9912 tcg_gen_extu_i32_i64(res
, ele3
);
9913 tcg_temp_free_i32(ele3
);
9915 write_fp_dreg(s
, rd
, res
);
9916 tcg_temp_free_i64(res
);
9919 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
9920 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
9921 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
9923 /* Handle 64->64 opcodes which are shared between the scalar and
9924 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
9925 * is valid in either group and also the double-precision fp ops.
9926 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
9932 case 0x4: /* CLS, CLZ */
9934 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
9936 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
9940 /* This opcode is shared with CNT and RBIT but we have earlier
9941 * enforced that size == 3 if and only if this is the NOT insn.
9943 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
9945 case 0x7: /* SQABS, SQNEG */
9947 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
9949 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
9952 case 0xa: /* CMLT */
9953 /* 64 bit integer comparison against zero, result is
9954 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
9959 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
9960 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
9962 case 0x8: /* CMGT, CMGE */
9963 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
9965 case 0x9: /* CMEQ, CMLE */
9966 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
9968 case 0xb: /* ABS, NEG */
9970 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
9972 tcg_gen_abs_i64(tcg_rd
, tcg_rn
);
9975 case 0x2f: /* FABS */
9976 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
9978 case 0x6f: /* FNEG */
9979 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
9981 case 0x7f: /* FSQRT */
9982 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
9984 case 0x1a: /* FCVTNS */
9985 case 0x1b: /* FCVTMS */
9986 case 0x1c: /* FCVTAS */
9987 case 0x3a: /* FCVTPS */
9988 case 0x3b: /* FCVTZS */
9990 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9991 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9992 tcg_temp_free_i32(tcg_shift
);
9995 case 0x5a: /* FCVTNU */
9996 case 0x5b: /* FCVTMU */
9997 case 0x5c: /* FCVTAU */
9998 case 0x7a: /* FCVTPU */
9999 case 0x7b: /* FCVTZU */
10001 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10002 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
10003 tcg_temp_free_i32(tcg_shift
);
10006 case 0x18: /* FRINTN */
10007 case 0x19: /* FRINTM */
10008 case 0x38: /* FRINTP */
10009 case 0x39: /* FRINTZ */
10010 case 0x58: /* FRINTA */
10011 case 0x79: /* FRINTI */
10012 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
10014 case 0x59: /* FRINTX */
10015 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
10017 case 0x1e: /* FRINT32Z */
10018 case 0x5e: /* FRINT32X */
10019 gen_helper_frint32_d(tcg_rd
, tcg_rn
, tcg_fpstatus
);
10021 case 0x1f: /* FRINT64Z */
10022 case 0x5f: /* FRINT64X */
10023 gen_helper_frint64_d(tcg_rd
, tcg_rn
, tcg_fpstatus
);
10026 g_assert_not_reached();
10030 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
10031 bool is_scalar
, bool is_u
, bool is_q
,
10032 int size
, int rn
, int rd
)
10034 bool is_double
= (size
== MO_64
);
10037 if (!fp_access_check(s
)) {
10041 fpst
= get_fpstatus_ptr(size
== MO_16
);
10044 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10045 TCGv_i64 tcg_zero
= tcg_const_i64(0);
10046 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10047 NeonGenTwoDoubleOpFn
*genfn
;
10052 case 0x2e: /* FCMLT (zero) */
10055 case 0x2c: /* FCMGT (zero) */
10056 genfn
= gen_helper_neon_cgt_f64
;
10058 case 0x2d: /* FCMEQ (zero) */
10059 genfn
= gen_helper_neon_ceq_f64
;
10061 case 0x6d: /* FCMLE (zero) */
10064 case 0x6c: /* FCMGE (zero) */
10065 genfn
= gen_helper_neon_cge_f64
;
10068 g_assert_not_reached();
10071 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10072 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10074 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
10076 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
10078 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10080 tcg_temp_free_i64(tcg_res
);
10081 tcg_temp_free_i64(tcg_zero
);
10082 tcg_temp_free_i64(tcg_op
);
10084 clear_vec_high(s
, !is_scalar
, rd
);
10086 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10087 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10088 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10089 NeonGenTwoSingleOpFn
*genfn
;
10091 int pass
, maxpasses
;
10093 if (size
== MO_16
) {
10095 case 0x2e: /* FCMLT (zero) */
10098 case 0x2c: /* FCMGT (zero) */
10099 genfn
= gen_helper_advsimd_cgt_f16
;
10101 case 0x2d: /* FCMEQ (zero) */
10102 genfn
= gen_helper_advsimd_ceq_f16
;
10104 case 0x6d: /* FCMLE (zero) */
10107 case 0x6c: /* FCMGE (zero) */
10108 genfn
= gen_helper_advsimd_cge_f16
;
10111 g_assert_not_reached();
10115 case 0x2e: /* FCMLT (zero) */
10118 case 0x2c: /* FCMGT (zero) */
10119 genfn
= gen_helper_neon_cgt_f32
;
10121 case 0x2d: /* FCMEQ (zero) */
10122 genfn
= gen_helper_neon_ceq_f32
;
10124 case 0x6d: /* FCMLE (zero) */
10127 case 0x6c: /* FCMGE (zero) */
10128 genfn
= gen_helper_neon_cge_f32
;
10131 g_assert_not_reached();
10138 int vector_size
= 8 << is_q
;
10139 maxpasses
= vector_size
>> size
;
10142 for (pass
= 0; pass
< maxpasses
; pass
++) {
10143 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
10145 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
10147 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
10150 write_fp_sreg(s
, rd
, tcg_res
);
10152 write_vec_element_i32(s
, tcg_res
, rd
, pass
, size
);
10155 tcg_temp_free_i32(tcg_res
);
10156 tcg_temp_free_i32(tcg_zero
);
10157 tcg_temp_free_i32(tcg_op
);
10159 clear_vec_high(s
, is_q
, rd
);
10163 tcg_temp_free_ptr(fpst
);
10166 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
10167 bool is_scalar
, bool is_u
, bool is_q
,
10168 int size
, int rn
, int rd
)
10170 bool is_double
= (size
== 3);
10171 TCGv_ptr fpst
= get_fpstatus_ptr(false);
10174 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10175 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10178 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10179 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10181 case 0x3d: /* FRECPE */
10182 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
10184 case 0x3f: /* FRECPX */
10185 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
10187 case 0x7d: /* FRSQRTE */
10188 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
10191 g_assert_not_reached();
10193 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10195 tcg_temp_free_i64(tcg_res
);
10196 tcg_temp_free_i64(tcg_op
);
10197 clear_vec_high(s
, !is_scalar
, rd
);
10199 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10200 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10201 int pass
, maxpasses
;
10206 maxpasses
= is_q
? 4 : 2;
10209 for (pass
= 0; pass
< maxpasses
; pass
++) {
10210 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
10213 case 0x3c: /* URECPE */
10214 gen_helper_recpe_u32(tcg_res
, tcg_op
);
10216 case 0x3d: /* FRECPE */
10217 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
10219 case 0x3f: /* FRECPX */
10220 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
10222 case 0x7d: /* FRSQRTE */
10223 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
10226 g_assert_not_reached();
10230 write_fp_sreg(s
, rd
, tcg_res
);
10232 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10235 tcg_temp_free_i32(tcg_res
);
10236 tcg_temp_free_i32(tcg_op
);
10238 clear_vec_high(s
, is_q
, rd
);
10241 tcg_temp_free_ptr(fpst
);
10244 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
10245 int opcode
, bool u
, bool is_q
,
10246 int size
, int rn
, int rd
)
10248 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
10249 * in the source becomes a size element in the destination).
10252 TCGv_i32 tcg_res
[2];
10253 int destelt
= is_q
? 2 : 0;
10254 int passes
= scalar
? 1 : 2;
10257 tcg_res
[1] = tcg_const_i32(0);
10260 for (pass
= 0; pass
< passes
; pass
++) {
10261 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10262 NeonGenNarrowFn
*genfn
= NULL
;
10263 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
10266 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
10268 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10270 tcg_res
[pass
] = tcg_temp_new_i32();
10273 case 0x12: /* XTN, SQXTUN */
10275 static NeonGenNarrowFn
* const xtnfns
[3] = {
10276 gen_helper_neon_narrow_u8
,
10277 gen_helper_neon_narrow_u16
,
10278 tcg_gen_extrl_i64_i32
,
10280 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
10281 gen_helper_neon_unarrow_sat8
,
10282 gen_helper_neon_unarrow_sat16
,
10283 gen_helper_neon_unarrow_sat32
,
10286 genenvfn
= sqxtunfns
[size
];
10288 genfn
= xtnfns
[size
];
10292 case 0x14: /* SQXTN, UQXTN */
10294 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
10295 { gen_helper_neon_narrow_sat_s8
,
10296 gen_helper_neon_narrow_sat_u8
},
10297 { gen_helper_neon_narrow_sat_s16
,
10298 gen_helper_neon_narrow_sat_u16
},
10299 { gen_helper_neon_narrow_sat_s32
,
10300 gen_helper_neon_narrow_sat_u32
},
10302 genenvfn
= fns
[size
][u
];
10305 case 0x16: /* FCVTN, FCVTN2 */
10306 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
10308 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
10310 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
10311 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
10312 TCGv_ptr fpst
= get_fpstatus_ptr(false);
10313 TCGv_i32 ahp
= get_ahp_flag();
10315 tcg_gen_extr_i64_i32(tcg_lo
, tcg_hi
, tcg_op
);
10316 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, fpst
, ahp
);
10317 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, fpst
, ahp
);
10318 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
10319 tcg_temp_free_i32(tcg_lo
);
10320 tcg_temp_free_i32(tcg_hi
);
10321 tcg_temp_free_ptr(fpst
);
10322 tcg_temp_free_i32(ahp
);
10325 case 0x56: /* FCVTXN, FCVTXN2 */
10326 /* 64 bit to 32 bit float conversion
10327 * with von Neumann rounding (round to odd)
10330 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
10333 g_assert_not_reached();
10337 genfn(tcg_res
[pass
], tcg_op
);
10338 } else if (genenvfn
) {
10339 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
10342 tcg_temp_free_i64(tcg_op
);
10345 for (pass
= 0; pass
< 2; pass
++) {
10346 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
10347 tcg_temp_free_i32(tcg_res
[pass
]);
10349 clear_vec_high(s
, is_q
, rd
);
10352 /* Remaining saturating accumulating ops */
10353 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
10354 bool is_q
, int size
, int rn
, int rd
)
10356 bool is_double
= (size
== 3);
10359 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
10360 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
10363 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10364 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
10365 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
10367 if (is_u
) { /* USQADD */
10368 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10369 } else { /* SUQADD */
10370 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10372 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
10374 tcg_temp_free_i64(tcg_rd
);
10375 tcg_temp_free_i64(tcg_rn
);
10376 clear_vec_high(s
, !is_scalar
, rd
);
10378 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
10379 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
10380 int pass
, maxpasses
;
10385 maxpasses
= is_q
? 4 : 2;
10388 for (pass
= 0; pass
< maxpasses
; pass
++) {
10390 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
10391 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
10393 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
10394 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
10397 if (is_u
) { /* USQADD */
10400 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10403 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10406 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10409 g_assert_not_reached();
10411 } else { /* SUQADD */
10414 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10417 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10420 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10423 g_assert_not_reached();
10428 TCGv_i64 tcg_zero
= tcg_const_i64(0);
10429 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
10430 tcg_temp_free_i64(tcg_zero
);
10432 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
10434 tcg_temp_free_i32(tcg_rd
);
10435 tcg_temp_free_i32(tcg_rn
);
10436 clear_vec_high(s
, is_q
, rd
);
10440 /* AdvSIMD scalar two reg misc
10441 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
10442 * +-----+---+-----------+------+-----------+--------+-----+------+------+
10443 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
10444 * +-----+---+-----------+------+-----------+--------+-----+------+------+
10446 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
10448 int rd
= extract32(insn
, 0, 5);
10449 int rn
= extract32(insn
, 5, 5);
10450 int opcode
= extract32(insn
, 12, 5);
10451 int size
= extract32(insn
, 22, 2);
10452 bool u
= extract32(insn
, 29, 1);
10453 bool is_fcvt
= false;
10455 TCGv_i32 tcg_rmode
;
10456 TCGv_ptr tcg_fpstatus
;
10459 case 0x3: /* USQADD / SUQADD*/
10460 if (!fp_access_check(s
)) {
10463 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
10465 case 0x7: /* SQABS / SQNEG */
10467 case 0xa: /* CMLT */
10469 unallocated_encoding(s
);
10473 case 0x8: /* CMGT, CMGE */
10474 case 0x9: /* CMEQ, CMLE */
10475 case 0xb: /* ABS, NEG */
10477 unallocated_encoding(s
);
10481 case 0x12: /* SQXTUN */
10483 unallocated_encoding(s
);
10487 case 0x14: /* SQXTN, UQXTN */
10489 unallocated_encoding(s
);
10492 if (!fp_access_check(s
)) {
10495 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
10498 case 0x16 ... 0x1d:
10500 /* Floating point: U, size[1] and opcode indicate operation;
10501 * size[0] indicates single or double precision.
10503 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
10504 size
= extract32(size
, 0, 1) ? 3 : 2;
10506 case 0x2c: /* FCMGT (zero) */
10507 case 0x2d: /* FCMEQ (zero) */
10508 case 0x2e: /* FCMLT (zero) */
10509 case 0x6c: /* FCMGE (zero) */
10510 case 0x6d: /* FCMLE (zero) */
10511 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
10513 case 0x1d: /* SCVTF */
10514 case 0x5d: /* UCVTF */
10516 bool is_signed
= (opcode
== 0x1d);
10517 if (!fp_access_check(s
)) {
10520 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
10523 case 0x3d: /* FRECPE */
10524 case 0x3f: /* FRECPX */
10525 case 0x7d: /* FRSQRTE */
10526 if (!fp_access_check(s
)) {
10529 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
10531 case 0x1a: /* FCVTNS */
10532 case 0x1b: /* FCVTMS */
10533 case 0x3a: /* FCVTPS */
10534 case 0x3b: /* FCVTZS */
10535 case 0x5a: /* FCVTNU */
10536 case 0x5b: /* FCVTMU */
10537 case 0x7a: /* FCVTPU */
10538 case 0x7b: /* FCVTZU */
10540 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
10542 case 0x1c: /* FCVTAS */
10543 case 0x5c: /* FCVTAU */
10544 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
10546 rmode
= FPROUNDING_TIEAWAY
;
10548 case 0x56: /* FCVTXN, FCVTXN2 */
10550 unallocated_encoding(s
);
10553 if (!fp_access_check(s
)) {
10556 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
10559 unallocated_encoding(s
);
10564 unallocated_encoding(s
);
10568 if (!fp_access_check(s
)) {
10573 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
10574 tcg_fpstatus
= get_fpstatus_ptr(false);
10575 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
10578 tcg_fpstatus
= NULL
;
10582 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
10583 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
10585 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
10586 write_fp_dreg(s
, rd
, tcg_rd
);
10587 tcg_temp_free_i64(tcg_rd
);
10588 tcg_temp_free_i64(tcg_rn
);
10590 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
10591 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
10593 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
10596 case 0x7: /* SQABS, SQNEG */
10598 NeonGenOneOpEnvFn
*genfn
;
10599 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
10600 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
10601 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
10602 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
10604 genfn
= fns
[size
][u
];
10605 genfn(tcg_rd
, cpu_env
, tcg_rn
);
10608 case 0x1a: /* FCVTNS */
10609 case 0x1b: /* FCVTMS */
10610 case 0x1c: /* FCVTAS */
10611 case 0x3a: /* FCVTPS */
10612 case 0x3b: /* FCVTZS */
10614 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10615 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
10616 tcg_temp_free_i32(tcg_shift
);
10619 case 0x5a: /* FCVTNU */
10620 case 0x5b: /* FCVTMU */
10621 case 0x5c: /* FCVTAU */
10622 case 0x7a: /* FCVTPU */
10623 case 0x7b: /* FCVTZU */
10625 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10626 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
10627 tcg_temp_free_i32(tcg_shift
);
10631 g_assert_not_reached();
10634 write_fp_sreg(s
, rd
, tcg_rd
);
10635 tcg_temp_free_i32(tcg_rd
);
10636 tcg_temp_free_i32(tcg_rn
);
10640 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
10641 tcg_temp_free_i32(tcg_rmode
);
10642 tcg_temp_free_ptr(tcg_fpstatus
);
10646 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
10647 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
10648 int immh
, int immb
, int opcode
, int rn
, int rd
)
10650 int size
= 32 - clz32(immh
) - 1;
10651 int immhb
= immh
<< 3 | immb
;
10652 int shift
= 2 * (8 << size
) - immhb
;
10653 GVecGen2iFn
*gvec_fn
;
10655 if (extract32(immh
, 3, 1) && !is_q
) {
10656 unallocated_encoding(s
);
10659 tcg_debug_assert(size
<= 3);
10661 if (!fp_access_check(s
)) {
10666 case 0x02: /* SSRA / USRA (accumulate) */
10667 gvec_fn
= is_u
? gen_gvec_usra
: gen_gvec_ssra
;
10670 case 0x08: /* SRI */
10671 gvec_fn
= gen_gvec_sri
;
10674 case 0x00: /* SSHR / USHR */
10676 if (shift
== 8 << size
) {
10677 /* Shift count the same size as element size produces zero. */
10678 tcg_gen_gvec_dup_imm(size
, vec_full_reg_offset(s
, rd
),
10679 is_q
? 16 : 8, vec_full_reg_size(s
), 0);
10682 gvec_fn
= tcg_gen_gvec_shri
;
10684 /* Shift count the same size as element size produces all sign. */
10685 if (shift
== 8 << size
) {
10688 gvec_fn
= tcg_gen_gvec_sari
;
10692 case 0x04: /* SRSHR / URSHR (rounding) */
10693 gvec_fn
= is_u
? gen_gvec_urshr
: gen_gvec_srshr
;
10696 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10697 gvec_fn
= is_u
? gen_gvec_ursra
: gen_gvec_srsra
;
10701 g_assert_not_reached();
10704 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, gvec_fn
, size
);
10707 /* SHL/SLI - Vector shift left */
10708 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
10709 int immh
, int immb
, int opcode
, int rn
, int rd
)
10711 int size
= 32 - clz32(immh
) - 1;
10712 int immhb
= immh
<< 3 | immb
;
10713 int shift
= immhb
- (8 << size
);
10715 /* Range of size is limited by decode: immh is a non-zero 4 bit field */
10716 assert(size
>= 0 && size
<= 3);
10718 if (extract32(immh
, 3, 1) && !is_q
) {
10719 unallocated_encoding(s
);
10723 if (!fp_access_check(s
)) {
10728 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, gen_gvec_sli
, size
);
10730 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shli
, size
);
10734 /* USHLL/SHLL - Vector shift left with widening */
10735 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
10736 int immh
, int immb
, int opcode
, int rn
, int rd
)
10738 int size
= 32 - clz32(immh
) - 1;
10739 int immhb
= immh
<< 3 | immb
;
10740 int shift
= immhb
- (8 << size
);
10742 int esize
= 8 << size
;
10743 int elements
= dsize
/esize
;
10744 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
10745 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
10749 unallocated_encoding(s
);
10753 if (!fp_access_check(s
)) {
10757 /* For the LL variants the store is larger than the load,
10758 * so if rd == rn we would overwrite parts of our input.
10759 * So load everything right now and use shifts in the main loop.
10761 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
10763 for (i
= 0; i
< elements
; i
++) {
10764 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
10765 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
10766 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
10767 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
10771 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
10772 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
10773 int immh
, int immb
, int opcode
, int rn
, int rd
)
10775 int immhb
= immh
<< 3 | immb
;
10776 int size
= 32 - clz32(immh
) - 1;
10778 int esize
= 8 << size
;
10779 int elements
= dsize
/esize
;
10780 int shift
= (2 * esize
) - immhb
;
10781 bool round
= extract32(opcode
, 0, 1);
10782 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
10783 TCGv_i64 tcg_round
;
10786 if (extract32(immh
, 3, 1)) {
10787 unallocated_encoding(s
);
10791 if (!fp_access_check(s
)) {
10795 tcg_rn
= tcg_temp_new_i64();
10796 tcg_rd
= tcg_temp_new_i64();
10797 tcg_final
= tcg_temp_new_i64();
10798 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
10801 uint64_t round_const
= 1ULL << (shift
- 1);
10802 tcg_round
= tcg_const_i64(round_const
);
10807 for (i
= 0; i
< elements
; i
++) {
10808 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
10809 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
10810 false, true, size
+1, shift
);
10812 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
10816 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
10818 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
10821 tcg_temp_free_i64(tcg_round
);
10823 tcg_temp_free_i64(tcg_rn
);
10824 tcg_temp_free_i64(tcg_rd
);
10825 tcg_temp_free_i64(tcg_final
);
10827 clear_vec_high(s
, is_q
, rd
);
10831 /* AdvSIMD shift by immediate
10832 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
10833 * +---+---+---+-------------+------+------+--------+---+------+------+
10834 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
10835 * +---+---+---+-------------+------+------+--------+---+------+------+
10837 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
10839 int rd
= extract32(insn
, 0, 5);
10840 int rn
= extract32(insn
, 5, 5);
10841 int opcode
= extract32(insn
, 11, 5);
10842 int immb
= extract32(insn
, 16, 3);
10843 int immh
= extract32(insn
, 19, 4);
10844 bool is_u
= extract32(insn
, 29, 1);
10845 bool is_q
= extract32(insn
, 30, 1);
10847 /* data_proc_simd[] has sent immh == 0 to disas_simd_mod_imm. */
10851 case 0x08: /* SRI */
10853 unallocated_encoding(s
);
10857 case 0x00: /* SSHR / USHR */
10858 case 0x02: /* SSRA / USRA (accumulate) */
10859 case 0x04: /* SRSHR / URSHR (rounding) */
10860 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10861 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10863 case 0x0a: /* SHL / SLI */
10864 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10866 case 0x10: /* SHRN */
10867 case 0x11: /* RSHRN / SQRSHRUN */
10869 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
10872 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
10875 case 0x12: /* SQSHRN / UQSHRN */
10876 case 0x13: /* SQRSHRN / UQRSHRN */
10877 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
10880 case 0x14: /* SSHLL / USHLL */
10881 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10883 case 0x1c: /* SCVTF / UCVTF */
10884 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
10887 case 0xc: /* SQSHLU */
10889 unallocated_encoding(s
);
10892 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
10894 case 0xe: /* SQSHL, UQSHL */
10895 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
10897 case 0x1f: /* FCVTZS/ FCVTZU */
10898 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
10901 unallocated_encoding(s
);
10906 /* Generate code to do a "long" addition or subtraction, ie one done in
10907 * TCGv_i64 on vector lanes twice the width specified by size.
10909 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
10910 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
10912 static NeonGenTwo64OpFn
* const fns
[3][2] = {
10913 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
10914 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
10915 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
10917 NeonGenTwo64OpFn
*genfn
;
10920 genfn
= fns
[size
][is_sub
];
10921 genfn(tcg_res
, tcg_op1
, tcg_op2
);
10924 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
10925 int opcode
, int rd
, int rn
, int rm
)
10927 /* 3-reg-different widening insns: 64 x 64 -> 128 */
10928 TCGv_i64 tcg_res
[2];
10931 tcg_res
[0] = tcg_temp_new_i64();
10932 tcg_res
[1] = tcg_temp_new_i64();
10934 /* Does this op do an adding accumulate, a subtracting accumulate,
10935 * or no accumulate at all?
10953 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10954 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10957 /* size == 2 means two 32x32->64 operations; this is worth special
10958 * casing because we can generally handle it inline.
10961 for (pass
= 0; pass
< 2; pass
++) {
10962 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10963 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10964 TCGv_i64 tcg_passres
;
10965 MemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
10967 int elt
= pass
+ is_q
* 2;
10969 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
10970 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
10973 tcg_passres
= tcg_res
[pass
];
10975 tcg_passres
= tcg_temp_new_i64();
10979 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10980 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10982 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10983 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10985 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10986 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10988 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
10989 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
10991 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
10992 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
10993 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
10995 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
10996 tcg_temp_free_i64(tcg_tmp1
);
10997 tcg_temp_free_i64(tcg_tmp2
);
11000 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
11001 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
11002 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
11003 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
11005 case 9: /* SQDMLAL, SQDMLAL2 */
11006 case 11: /* SQDMLSL, SQDMLSL2 */
11007 case 13: /* SQDMULL, SQDMULL2 */
11008 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
11009 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
11010 tcg_passres
, tcg_passres
);
11013 g_assert_not_reached();
11016 if (opcode
== 9 || opcode
== 11) {
11017 /* saturating accumulate ops */
11019 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
11021 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
11022 tcg_res
[pass
], tcg_passres
);
11023 } else if (accop
> 0) {
11024 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
11025 } else if (accop
< 0) {
11026 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
11030 tcg_temp_free_i64(tcg_passres
);
11033 tcg_temp_free_i64(tcg_op1
);
11034 tcg_temp_free_i64(tcg_op2
);
11037 /* size 0 or 1, generally helper functions */
11038 for (pass
= 0; pass
< 2; pass
++) {
11039 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11040 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11041 TCGv_i64 tcg_passres
;
11042 int elt
= pass
+ is_q
* 2;
11044 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
11045 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
11048 tcg_passres
= tcg_res
[pass
];
11050 tcg_passres
= tcg_temp_new_i64();
11054 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
11055 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
11057 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
11058 static NeonGenWidenFn
* const widenfns
[2][2] = {
11059 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
11060 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
11062 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
11064 widenfn(tcg_op2_64
, tcg_op2
);
11065 widenfn(tcg_passres
, tcg_op1
);
11066 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
11067 tcg_passres
, tcg_op2_64
);
11068 tcg_temp_free_i64(tcg_op2_64
);
11071 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
11072 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
11075 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
11077 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
11081 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
11083 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
11087 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
11088 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
11089 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
11092 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
11094 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
11098 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
11100 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
11104 case 9: /* SQDMLAL, SQDMLAL2 */
11105 case 11: /* SQDMLSL, SQDMLSL2 */
11106 case 13: /* SQDMULL, SQDMULL2 */
11108 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
11109 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
11110 tcg_passres
, tcg_passres
);
11113 g_assert_not_reached();
11115 tcg_temp_free_i32(tcg_op1
);
11116 tcg_temp_free_i32(tcg_op2
);
11119 if (opcode
== 9 || opcode
== 11) {
11120 /* saturating accumulate ops */
11122 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
11124 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
11128 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
11129 tcg_res
[pass
], tcg_passres
);
11131 tcg_temp_free_i64(tcg_passres
);
11136 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
11137 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
11138 tcg_temp_free_i64(tcg_res
[0]);
11139 tcg_temp_free_i64(tcg_res
[1]);
11142 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
11143 int opcode
, int rd
, int rn
, int rm
)
11145 TCGv_i64 tcg_res
[2];
11146 int part
= is_q
? 2 : 0;
11149 for (pass
= 0; pass
< 2; pass
++) {
11150 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11151 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11152 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
11153 static NeonGenWidenFn
* const widenfns
[3][2] = {
11154 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
11155 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
11156 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
11158 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
11160 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
11161 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
11162 widenfn(tcg_op2_wide
, tcg_op2
);
11163 tcg_temp_free_i32(tcg_op2
);
11164 tcg_res
[pass
] = tcg_temp_new_i64();
11165 gen_neon_addl(size
, (opcode
== 3),
11166 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
11167 tcg_temp_free_i64(tcg_op1
);
11168 tcg_temp_free_i64(tcg_op2_wide
);
11171 for (pass
= 0; pass
< 2; pass
++) {
11172 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11173 tcg_temp_free_i64(tcg_res
[pass
]);
11177 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
11179 tcg_gen_addi_i64(in
, in
, 1U << 31);
11180 tcg_gen_extrh_i64_i32(res
, in
);
11183 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
11184 int opcode
, int rd
, int rn
, int rm
)
11186 TCGv_i32 tcg_res
[2];
11187 int part
= is_q
? 2 : 0;
11190 for (pass
= 0; pass
< 2; pass
++) {
11191 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11192 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11193 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
11194 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
11195 { gen_helper_neon_narrow_high_u8
,
11196 gen_helper_neon_narrow_round_high_u8
},
11197 { gen_helper_neon_narrow_high_u16
,
11198 gen_helper_neon_narrow_round_high_u16
},
11199 { tcg_gen_extrh_i64_i32
, do_narrow_round_high_u32
},
11201 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
11203 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
11204 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
11206 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
11208 tcg_temp_free_i64(tcg_op1
);
11209 tcg_temp_free_i64(tcg_op2
);
11211 tcg_res
[pass
] = tcg_temp_new_i32();
11212 gennarrow(tcg_res
[pass
], tcg_wideres
);
11213 tcg_temp_free_i64(tcg_wideres
);
11216 for (pass
= 0; pass
< 2; pass
++) {
11217 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
11218 tcg_temp_free_i32(tcg_res
[pass
]);
11220 clear_vec_high(s
, is_q
, rd
);
11223 /* AdvSIMD three different
11224 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
11225 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
11226 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
11227 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
11229 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
11231 /* Instructions in this group fall into three basic classes
11232 * (in each case with the operation working on each element in
11233 * the input vectors):
11234 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
11236 * (2) wide 64 x 128 -> 128
11237 * (3) narrowing 128 x 128 -> 64
11238 * Here we do initial decode, catch unallocated cases and
11239 * dispatch to separate functions for each class.
11241 int is_q
= extract32(insn
, 30, 1);
11242 int is_u
= extract32(insn
, 29, 1);
11243 int size
= extract32(insn
, 22, 2);
11244 int opcode
= extract32(insn
, 12, 4);
11245 int rm
= extract32(insn
, 16, 5);
11246 int rn
= extract32(insn
, 5, 5);
11247 int rd
= extract32(insn
, 0, 5);
11250 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
11251 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
11252 /* 64 x 128 -> 128 */
11254 unallocated_encoding(s
);
11257 if (!fp_access_check(s
)) {
11260 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
11262 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
11263 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
11264 /* 128 x 128 -> 64 */
11266 unallocated_encoding(s
);
11269 if (!fp_access_check(s
)) {
11272 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
11274 case 14: /* PMULL, PMULL2 */
11276 unallocated_encoding(s
);
11280 case 0: /* PMULL.P8 */
11281 if (!fp_access_check(s
)) {
11284 /* The Q field specifies lo/hi half input for this insn. */
11285 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, is_q
,
11286 gen_helper_neon_pmull_h
);
11289 case 3: /* PMULL.P64 */
11290 if (!dc_isar_feature(aa64_pmull
, s
)) {
11291 unallocated_encoding(s
);
11294 if (!fp_access_check(s
)) {
11297 /* The Q field specifies lo/hi half input for this insn. */
11298 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, is_q
,
11299 gen_helper_gvec_pmull_q
);
11303 unallocated_encoding(s
);
11307 case 9: /* SQDMLAL, SQDMLAL2 */
11308 case 11: /* SQDMLSL, SQDMLSL2 */
11309 case 13: /* SQDMULL, SQDMULL2 */
11310 if (is_u
|| size
== 0) {
11311 unallocated_encoding(s
);
11315 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
11316 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
11317 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
11318 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
11319 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
11320 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
11321 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
11322 /* 64 x 64 -> 128 */
11324 unallocated_encoding(s
);
11327 if (!fp_access_check(s
)) {
11331 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
11334 /* opcode 15 not allocated */
11335 unallocated_encoding(s
);
11340 /* Logic op (opcode == 3) subgroup of C3.6.16. */
11341 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
11343 int rd
= extract32(insn
, 0, 5);
11344 int rn
= extract32(insn
, 5, 5);
11345 int rm
= extract32(insn
, 16, 5);
11346 int size
= extract32(insn
, 22, 2);
11347 bool is_u
= extract32(insn
, 29, 1);
11348 bool is_q
= extract32(insn
, 30, 1);
11350 if (!fp_access_check(s
)) {
11354 switch (size
+ 4 * is_u
) {
11356 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_and
, 0);
11359 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_andc
, 0);
11362 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_or
, 0);
11365 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_orc
, 0);
11368 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_xor
, 0);
11371 case 5: /* BSL bitwise select */
11372 gen_gvec_fn4(s
, is_q
, rd
, rd
, rn
, rm
, tcg_gen_gvec_bitsel
, 0);
11374 case 6: /* BIT, bitwise insert if true */
11375 gen_gvec_fn4(s
, is_q
, rd
, rm
, rn
, rd
, tcg_gen_gvec_bitsel
, 0);
11377 case 7: /* BIF, bitwise insert if false */
11378 gen_gvec_fn4(s
, is_q
, rd
, rm
, rd
, rn
, tcg_gen_gvec_bitsel
, 0);
11382 g_assert_not_reached();
11386 /* Pairwise op subgroup of C3.6.16.
11388 * This is called directly or via the handle_3same_float for float pairwise
11389 * operations where the opcode and size are calculated differently.
11391 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
11392 int size
, int rn
, int rm
, int rd
)
11397 /* Floating point operations need fpst */
11398 if (opcode
>= 0x58) {
11399 fpst
= get_fpstatus_ptr(false);
11404 if (!fp_access_check(s
)) {
11408 /* These operations work on the concatenated rm:rn, with each pair of
11409 * adjacent elements being operated on to produce an element in the result.
11412 TCGv_i64 tcg_res
[2];
11414 for (pass
= 0; pass
< 2; pass
++) {
11415 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11416 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11417 int passreg
= (pass
== 0) ? rn
: rm
;
11419 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
11420 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
11421 tcg_res
[pass
] = tcg_temp_new_i64();
11424 case 0x17: /* ADDP */
11425 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11427 case 0x58: /* FMAXNMP */
11428 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11430 case 0x5a: /* FADDP */
11431 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11433 case 0x5e: /* FMAXP */
11434 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11436 case 0x78: /* FMINNMP */
11437 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11439 case 0x7e: /* FMINP */
11440 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11443 g_assert_not_reached();
11446 tcg_temp_free_i64(tcg_op1
);
11447 tcg_temp_free_i64(tcg_op2
);
11450 for (pass
= 0; pass
< 2; pass
++) {
11451 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11452 tcg_temp_free_i64(tcg_res
[pass
]);
11455 int maxpass
= is_q
? 4 : 2;
11456 TCGv_i32 tcg_res
[4];
11458 for (pass
= 0; pass
< maxpass
; pass
++) {
11459 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11460 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11461 NeonGenTwoOpFn
*genfn
= NULL
;
11462 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
11463 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
11465 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
11466 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
11467 tcg_res
[pass
] = tcg_temp_new_i32();
11470 case 0x17: /* ADDP */
11472 static NeonGenTwoOpFn
* const fns
[3] = {
11473 gen_helper_neon_padd_u8
,
11474 gen_helper_neon_padd_u16
,
11480 case 0x14: /* SMAXP, UMAXP */
11482 static NeonGenTwoOpFn
* const fns
[3][2] = {
11483 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
11484 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
11485 { tcg_gen_smax_i32
, tcg_gen_umax_i32
},
11487 genfn
= fns
[size
][u
];
11490 case 0x15: /* SMINP, UMINP */
11492 static NeonGenTwoOpFn
* const fns
[3][2] = {
11493 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
11494 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
11495 { tcg_gen_smin_i32
, tcg_gen_umin_i32
},
11497 genfn
= fns
[size
][u
];
11500 /* The FP operations are all on single floats (32 bit) */
11501 case 0x58: /* FMAXNMP */
11502 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11504 case 0x5a: /* FADDP */
11505 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11507 case 0x5e: /* FMAXP */
11508 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11510 case 0x78: /* FMINNMP */
11511 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11513 case 0x7e: /* FMINP */
11514 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11517 g_assert_not_reached();
11520 /* FP ops called directly, otherwise call now */
11522 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11525 tcg_temp_free_i32(tcg_op1
);
11526 tcg_temp_free_i32(tcg_op2
);
11529 for (pass
= 0; pass
< maxpass
; pass
++) {
11530 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
11531 tcg_temp_free_i32(tcg_res
[pass
]);
11533 clear_vec_high(s
, is_q
, rd
);
11537 tcg_temp_free_ptr(fpst
);
11541 /* Floating point op subgroup of C3.6.16. */
11542 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
11544 /* For floating point ops, the U, size[1] and opcode bits
11545 * together indicate the operation. size[0] indicates single
11548 int fpopcode
= extract32(insn
, 11, 5)
11549 | (extract32(insn
, 23, 1) << 5)
11550 | (extract32(insn
, 29, 1) << 6);
11551 int is_q
= extract32(insn
, 30, 1);
11552 int size
= extract32(insn
, 22, 1);
11553 int rm
= extract32(insn
, 16, 5);
11554 int rn
= extract32(insn
, 5, 5);
11555 int rd
= extract32(insn
, 0, 5);
11557 int datasize
= is_q
? 128 : 64;
11558 int esize
= 32 << size
;
11559 int elements
= datasize
/ esize
;
11561 if (size
== 1 && !is_q
) {
11562 unallocated_encoding(s
);
11566 switch (fpopcode
) {
11567 case 0x58: /* FMAXNMP */
11568 case 0x5a: /* FADDP */
11569 case 0x5e: /* FMAXP */
11570 case 0x78: /* FMINNMP */
11571 case 0x7e: /* FMINP */
11572 if (size
&& !is_q
) {
11573 unallocated_encoding(s
);
11576 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
11579 case 0x1b: /* FMULX */
11580 case 0x1f: /* FRECPS */
11581 case 0x3f: /* FRSQRTS */
11582 case 0x5d: /* FACGE */
11583 case 0x7d: /* FACGT */
11584 case 0x19: /* FMLA */
11585 case 0x39: /* FMLS */
11586 case 0x18: /* FMAXNM */
11587 case 0x1a: /* FADD */
11588 case 0x1c: /* FCMEQ */
11589 case 0x1e: /* FMAX */
11590 case 0x38: /* FMINNM */
11591 case 0x3a: /* FSUB */
11592 case 0x3e: /* FMIN */
11593 case 0x5b: /* FMUL */
11594 case 0x5c: /* FCMGE */
11595 case 0x5f: /* FDIV */
11596 case 0x7a: /* FABD */
11597 case 0x7c: /* FCMGT */
11598 if (!fp_access_check(s
)) {
11601 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
11604 case 0x1d: /* FMLAL */
11605 case 0x3d: /* FMLSL */
11606 case 0x59: /* FMLAL2 */
11607 case 0x79: /* FMLSL2 */
11608 if (size
& 1 || !dc_isar_feature(aa64_fhm
, s
)) {
11609 unallocated_encoding(s
);
11612 if (fp_access_check(s
)) {
11613 int is_s
= extract32(insn
, 23, 1);
11614 int is_2
= extract32(insn
, 29, 1);
11615 int data
= (is_2
<< 1) | is_s
;
11616 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
11617 vec_full_reg_offset(s
, rn
),
11618 vec_full_reg_offset(s
, rm
), cpu_env
,
11619 is_q
? 16 : 8, vec_full_reg_size(s
),
11620 data
, gen_helper_gvec_fmlal_a64
);
11625 unallocated_encoding(s
);
11630 /* Integer op subgroup of C3.6.16. */
11631 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
11633 int is_q
= extract32(insn
, 30, 1);
11634 int u
= extract32(insn
, 29, 1);
11635 int size
= extract32(insn
, 22, 2);
11636 int opcode
= extract32(insn
, 11, 5);
11637 int rm
= extract32(insn
, 16, 5);
11638 int rn
= extract32(insn
, 5, 5);
11639 int rd
= extract32(insn
, 0, 5);
11644 case 0x13: /* MUL, PMUL */
11645 if (u
&& size
!= 0) {
11646 unallocated_encoding(s
);
11650 case 0x0: /* SHADD, UHADD */
11651 case 0x2: /* SRHADD, URHADD */
11652 case 0x4: /* SHSUB, UHSUB */
11653 case 0xc: /* SMAX, UMAX */
11654 case 0xd: /* SMIN, UMIN */
11655 case 0xe: /* SABD, UABD */
11656 case 0xf: /* SABA, UABA */
11657 case 0x12: /* MLA, MLS */
11659 unallocated_encoding(s
);
11663 case 0x16: /* SQDMULH, SQRDMULH */
11664 if (size
== 0 || size
== 3) {
11665 unallocated_encoding(s
);
11670 if (size
== 3 && !is_q
) {
11671 unallocated_encoding(s
);
11677 if (!fp_access_check(s
)) {
11682 case 0x01: /* SQADD, UQADD */
11684 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uqadd_qc
, size
);
11686 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqadd_qc
, size
);
11689 case 0x05: /* SQSUB, UQSUB */
11691 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uqsub_qc
, size
);
11693 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqsub_qc
, size
);
11696 case 0x08: /* SSHL, USHL */
11698 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_ushl
, size
);
11700 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sshl
, size
);
11703 case 0x0c: /* SMAX, UMAX */
11705 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umax
, size
);
11707 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smax
, size
);
11710 case 0x0d: /* SMIN, UMIN */
11712 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umin
, size
);
11714 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smin
, size
);
11717 case 0xe: /* SABD, UABD */
11719 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uabd
, size
);
11721 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sabd
, size
);
11724 case 0xf: /* SABA, UABA */
11726 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uaba
, size
);
11728 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_saba
, size
);
11731 case 0x10: /* ADD, SUB */
11733 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_sub
, size
);
11735 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_add
, size
);
11738 case 0x13: /* MUL, PMUL */
11739 if (!u
) { /* MUL */
11740 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_mul
, size
);
11741 } else { /* PMUL */
11742 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, 0, gen_helper_gvec_pmul_b
);
11745 case 0x12: /* MLA, MLS */
11747 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_mls
, size
);
11749 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_mla
, size
);
11753 if (!u
) { /* CMTST */
11754 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_cmtst
, size
);
11758 cond
= TCG_COND_EQ
;
11760 case 0x06: /* CMGT, CMHI */
11761 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
11763 case 0x07: /* CMGE, CMHS */
11764 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
11766 tcg_gen_gvec_cmp(cond
, size
, vec_full_reg_offset(s
, rd
),
11767 vec_full_reg_offset(s
, rn
),
11768 vec_full_reg_offset(s
, rm
),
11769 is_q
? 16 : 8, vec_full_reg_size(s
));
11775 for (pass
= 0; pass
< 2; pass
++) {
11776 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11777 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11778 TCGv_i64 tcg_res
= tcg_temp_new_i64();
11780 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
11781 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
11783 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
11785 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
11787 tcg_temp_free_i64(tcg_res
);
11788 tcg_temp_free_i64(tcg_op1
);
11789 tcg_temp_free_i64(tcg_op2
);
11792 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
11793 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11794 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11795 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11796 NeonGenTwoOpFn
*genfn
= NULL
;
11797 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
11799 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
11800 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
11803 case 0x0: /* SHADD, UHADD */
11805 static NeonGenTwoOpFn
* const fns
[3][2] = {
11806 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
11807 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
11808 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
11810 genfn
= fns
[size
][u
];
11813 case 0x2: /* SRHADD, URHADD */
11815 static NeonGenTwoOpFn
* const fns
[3][2] = {
11816 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
11817 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
11818 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
11820 genfn
= fns
[size
][u
];
11823 case 0x4: /* SHSUB, UHSUB */
11825 static NeonGenTwoOpFn
* const fns
[3][2] = {
11826 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
11827 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
11828 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
11830 genfn
= fns
[size
][u
];
11833 case 0x9: /* SQSHL, UQSHL */
11835 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11836 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
11837 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
11838 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
11840 genenvfn
= fns
[size
][u
];
11843 case 0xa: /* SRSHL, URSHL */
11845 static NeonGenTwoOpFn
* const fns
[3][2] = {
11846 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
11847 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
11848 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
11850 genfn
= fns
[size
][u
];
11853 case 0xb: /* SQRSHL, UQRSHL */
11855 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11856 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
11857 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
11858 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
11860 genenvfn
= fns
[size
][u
];
11863 case 0x16: /* SQDMULH, SQRDMULH */
11865 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
11866 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
11867 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
11869 assert(size
== 1 || size
== 2);
11870 genenvfn
= fns
[size
- 1][u
];
11874 g_assert_not_reached();
11878 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
11880 genfn(tcg_res
, tcg_op1
, tcg_op2
);
11883 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
11885 tcg_temp_free_i32(tcg_res
);
11886 tcg_temp_free_i32(tcg_op1
);
11887 tcg_temp_free_i32(tcg_op2
);
11890 clear_vec_high(s
, is_q
, rd
);
11893 /* AdvSIMD three same
11894 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
11895 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11896 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
11897 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11899 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
11901 int opcode
= extract32(insn
, 11, 5);
11904 case 0x3: /* logic ops */
11905 disas_simd_3same_logic(s
, insn
);
11907 case 0x17: /* ADDP */
11908 case 0x14: /* SMAXP, UMAXP */
11909 case 0x15: /* SMINP, UMINP */
11911 /* Pairwise operations */
11912 int is_q
= extract32(insn
, 30, 1);
11913 int u
= extract32(insn
, 29, 1);
11914 int size
= extract32(insn
, 22, 2);
11915 int rm
= extract32(insn
, 16, 5);
11916 int rn
= extract32(insn
, 5, 5);
11917 int rd
= extract32(insn
, 0, 5);
11918 if (opcode
== 0x17) {
11919 if (u
|| (size
== 3 && !is_q
)) {
11920 unallocated_encoding(s
);
11925 unallocated_encoding(s
);
11929 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
11932 case 0x18 ... 0x31:
11933 /* floating point ops, sz[1] and U are part of opcode */
11934 disas_simd_3same_float(s
, insn
);
11937 disas_simd_3same_int(s
, insn
);
11943 * Advanced SIMD three same (ARMv8.2 FP16 variants)
11945 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
11946 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11947 * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
11948 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11950 * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE
11951 * (register), FACGE, FABD, FCMGT (register) and FACGT.
11954 static void disas_simd_three_reg_same_fp16(DisasContext
*s
, uint32_t insn
)
11956 int opcode
, fpopcode
;
11957 int is_q
, u
, a
, rm
, rn
, rd
;
11958 int datasize
, elements
;
11961 bool pairwise
= false;
11963 if (!dc_isar_feature(aa64_fp16
, s
)) {
11964 unallocated_encoding(s
);
11968 if (!fp_access_check(s
)) {
11972 /* For these floating point ops, the U, a and opcode bits
11973 * together indicate the operation.
11975 opcode
= extract32(insn
, 11, 3);
11976 u
= extract32(insn
, 29, 1);
11977 a
= extract32(insn
, 23, 1);
11978 is_q
= extract32(insn
, 30, 1);
11979 rm
= extract32(insn
, 16, 5);
11980 rn
= extract32(insn
, 5, 5);
11981 rd
= extract32(insn
, 0, 5);
11983 fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
11984 datasize
= is_q
? 128 : 64;
11985 elements
= datasize
/ 16;
11987 switch (fpopcode
) {
11988 case 0x10: /* FMAXNMP */
11989 case 0x12: /* FADDP */
11990 case 0x16: /* FMAXP */
11991 case 0x18: /* FMINNMP */
11992 case 0x1e: /* FMINP */
11997 fpst
= get_fpstatus_ptr(true);
12000 int maxpass
= is_q
? 8 : 4;
12001 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
12002 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
12003 TCGv_i32 tcg_res
[8];
12005 for (pass
= 0; pass
< maxpass
; pass
++) {
12006 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
12007 int passelt
= (pass
<< 1) & (maxpass
- 1);
12009 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_16
);
12010 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_16
);
12011 tcg_res
[pass
] = tcg_temp_new_i32();
12013 switch (fpopcode
) {
12014 case 0x10: /* FMAXNMP */
12015 gen_helper_advsimd_maxnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
12018 case 0x12: /* FADDP */
12019 gen_helper_advsimd_addh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
12021 case 0x16: /* FMAXP */
12022 gen_helper_advsimd_maxh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
12024 case 0x18: /* FMINNMP */
12025 gen_helper_advsimd_minnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
12028 case 0x1e: /* FMINP */
12029 gen_helper_advsimd_minh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
12032 g_assert_not_reached();
12036 for (pass
= 0; pass
< maxpass
; pass
++) {
12037 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_16
);
12038 tcg_temp_free_i32(tcg_res
[pass
]);
12041 tcg_temp_free_i32(tcg_op1
);
12042 tcg_temp_free_i32(tcg_op2
);
12045 for (pass
= 0; pass
< elements
; pass
++) {
12046 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
12047 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
12048 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12050 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_16
);
12051 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_16
);
12053 switch (fpopcode
) {
12054 case 0x0: /* FMAXNM */
12055 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12057 case 0x1: /* FMLA */
12058 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12059 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
12062 case 0x2: /* FADD */
12063 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12065 case 0x3: /* FMULX */
12066 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12068 case 0x4: /* FCMEQ */
12069 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12071 case 0x6: /* FMAX */
12072 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12074 case 0x7: /* FRECPS */
12075 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12077 case 0x8: /* FMINNM */
12078 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12080 case 0x9: /* FMLS */
12081 /* As usual for ARM, separate negation for fused multiply-add */
12082 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
12083 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12084 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
12087 case 0xa: /* FSUB */
12088 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12090 case 0xe: /* FMIN */
12091 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12093 case 0xf: /* FRSQRTS */
12094 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12096 case 0x13: /* FMUL */
12097 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12099 case 0x14: /* FCMGE */
12100 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12102 case 0x15: /* FACGE */
12103 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12105 case 0x17: /* FDIV */
12106 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12108 case 0x1a: /* FABD */
12109 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12110 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
12112 case 0x1c: /* FCMGT */
12113 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12115 case 0x1d: /* FACGT */
12116 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12119 fprintf(stderr
, "%s: insn %#04x, fpop %#2x @ %#" PRIx64
"\n",
12120 __func__
, insn
, fpopcode
, s
->pc_curr
);
12121 g_assert_not_reached();
12124 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12125 tcg_temp_free_i32(tcg_res
);
12126 tcg_temp_free_i32(tcg_op1
);
12127 tcg_temp_free_i32(tcg_op2
);
12131 tcg_temp_free_ptr(fpst
);
12133 clear_vec_high(s
, is_q
, rd
);
12136 /* AdvSIMD three same extra
12137 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
12138 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
12139 * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
12140 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
12142 static void disas_simd_three_reg_same_extra(DisasContext
*s
, uint32_t insn
)
12144 int rd
= extract32(insn
, 0, 5);
12145 int rn
= extract32(insn
, 5, 5);
12146 int opcode
= extract32(insn
, 11, 4);
12147 int rm
= extract32(insn
, 16, 5);
12148 int size
= extract32(insn
, 22, 2);
12149 bool u
= extract32(insn
, 29, 1);
12150 bool is_q
= extract32(insn
, 30, 1);
12154 switch (u
* 16 + opcode
) {
12155 case 0x10: /* SQRDMLAH (vector) */
12156 case 0x11: /* SQRDMLSH (vector) */
12157 if (size
!= 1 && size
!= 2) {
12158 unallocated_encoding(s
);
12161 feature
= dc_isar_feature(aa64_rdm
, s
);
12163 case 0x02: /* SDOT (vector) */
12164 case 0x12: /* UDOT (vector) */
12165 if (size
!= MO_32
) {
12166 unallocated_encoding(s
);
12169 feature
= dc_isar_feature(aa64_dp
, s
);
12171 case 0x18: /* FCMLA, #0 */
12172 case 0x19: /* FCMLA, #90 */
12173 case 0x1a: /* FCMLA, #180 */
12174 case 0x1b: /* FCMLA, #270 */
12175 case 0x1c: /* FCADD, #90 */
12176 case 0x1e: /* FCADD, #270 */
12178 || (size
== 1 && !dc_isar_feature(aa64_fp16
, s
))
12179 || (size
== 3 && !is_q
)) {
12180 unallocated_encoding(s
);
12183 feature
= dc_isar_feature(aa64_fcma
, s
);
12186 unallocated_encoding(s
);
12190 unallocated_encoding(s
);
12193 if (!fp_access_check(s
)) {
12198 case 0x0: /* SQRDMLAH (vector) */
12199 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqrdmlah_qc
, size
);
12202 case 0x1: /* SQRDMLSH (vector) */
12203 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqrdmlsh_qc
, size
);
12206 case 0x2: /* SDOT / UDOT */
12207 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, 0,
12208 u
? gen_helper_gvec_udot_b
: gen_helper_gvec_sdot_b
);
12211 case 0x8: /* FCMLA, #0 */
12212 case 0x9: /* FCMLA, #90 */
12213 case 0xa: /* FCMLA, #180 */
12214 case 0xb: /* FCMLA, #270 */
12215 rot
= extract32(opcode
, 0, 2);
12218 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, true, rot
,
12219 gen_helper_gvec_fcmlah
);
12222 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
12223 gen_helper_gvec_fcmlas
);
12226 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
12227 gen_helper_gvec_fcmlad
);
12230 g_assert_not_reached();
12234 case 0xc: /* FCADD, #90 */
12235 case 0xe: /* FCADD, #270 */
12236 rot
= extract32(opcode
, 1, 1);
12239 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
12240 gen_helper_gvec_fcaddh
);
12243 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
12244 gen_helper_gvec_fcadds
);
12247 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
12248 gen_helper_gvec_fcaddd
);
12251 g_assert_not_reached();
12256 g_assert_not_reached();
12260 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
12261 int size
, int rn
, int rd
)
12263 /* Handle 2-reg-misc ops which are widening (so each size element
12264 * in the source becomes a 2*size element in the destination.
12265 * The only instruction like this is FCVTL.
12270 /* 32 -> 64 bit fp conversion */
12271 TCGv_i64 tcg_res
[2];
12272 int srcelt
= is_q
? 2 : 0;
12274 for (pass
= 0; pass
< 2; pass
++) {
12275 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12276 tcg_res
[pass
] = tcg_temp_new_i64();
12278 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
12279 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
12280 tcg_temp_free_i32(tcg_op
);
12282 for (pass
= 0; pass
< 2; pass
++) {
12283 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12284 tcg_temp_free_i64(tcg_res
[pass
]);
12287 /* 16 -> 32 bit fp conversion */
12288 int srcelt
= is_q
? 4 : 0;
12289 TCGv_i32 tcg_res
[4];
12290 TCGv_ptr fpst
= get_fpstatus_ptr(false);
12291 TCGv_i32 ahp
= get_ahp_flag();
12293 for (pass
= 0; pass
< 4; pass
++) {
12294 tcg_res
[pass
] = tcg_temp_new_i32();
12296 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
12297 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
12300 for (pass
= 0; pass
< 4; pass
++) {
12301 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
12302 tcg_temp_free_i32(tcg_res
[pass
]);
12305 tcg_temp_free_ptr(fpst
);
12306 tcg_temp_free_i32(ahp
);
12310 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
12311 bool is_q
, int size
, int rn
, int rd
)
12313 int op
= (opcode
<< 1) | u
;
12314 int opsz
= op
+ size
;
12315 int grp_size
= 3 - opsz
;
12316 int dsize
= is_q
? 128 : 64;
12320 unallocated_encoding(s
);
12324 if (!fp_access_check(s
)) {
12329 /* Special case bytes, use bswap op on each group of elements */
12330 int groups
= dsize
/ (8 << grp_size
);
12332 for (i
= 0; i
< groups
; i
++) {
12333 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
12335 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
12336 switch (grp_size
) {
12338 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
12341 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
12344 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
12347 g_assert_not_reached();
12349 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
12350 tcg_temp_free_i64(tcg_tmp
);
12352 clear_vec_high(s
, is_q
, rd
);
12354 int revmask
= (1 << grp_size
) - 1;
12355 int esize
= 8 << size
;
12356 int elements
= dsize
/ esize
;
12357 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
12358 TCGv_i64 tcg_rd
= tcg_const_i64(0);
12359 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
12361 for (i
= 0; i
< elements
; i
++) {
12362 int e_rev
= (i
& 0xf) ^ revmask
;
12363 int off
= e_rev
* esize
;
12364 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
12366 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
12367 tcg_rn
, off
- 64, esize
);
12369 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
12372 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
12373 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
12375 tcg_temp_free_i64(tcg_rd_hi
);
12376 tcg_temp_free_i64(tcg_rd
);
12377 tcg_temp_free_i64(tcg_rn
);
12381 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
12382 bool is_q
, int size
, int rn
, int rd
)
12384 /* Implement the pairwise operations from 2-misc:
12385 * SADDLP, UADDLP, SADALP, UADALP.
12386 * These all add pairs of elements in the input to produce a
12387 * double-width result element in the output (possibly accumulating).
12389 bool accum
= (opcode
== 0x6);
12390 int maxpass
= is_q
? 2 : 1;
12392 TCGv_i64 tcg_res
[2];
12395 /* 32 + 32 -> 64 op */
12396 MemOp memop
= size
+ (u
? 0 : MO_SIGN
);
12398 for (pass
= 0; pass
< maxpass
; pass
++) {
12399 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
12400 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
12402 tcg_res
[pass
] = tcg_temp_new_i64();
12404 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
12405 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
12406 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
12408 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
12409 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
12412 tcg_temp_free_i64(tcg_op1
);
12413 tcg_temp_free_i64(tcg_op2
);
12416 for (pass
= 0; pass
< maxpass
; pass
++) {
12417 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12418 NeonGenOne64OpFn
*genfn
;
12419 static NeonGenOne64OpFn
* const fns
[2][2] = {
12420 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
12421 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
12424 genfn
= fns
[size
][u
];
12426 tcg_res
[pass
] = tcg_temp_new_i64();
12428 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12429 genfn(tcg_res
[pass
], tcg_op
);
12432 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
12434 gen_helper_neon_addl_u16(tcg_res
[pass
],
12435 tcg_res
[pass
], tcg_op
);
12437 gen_helper_neon_addl_u32(tcg_res
[pass
],
12438 tcg_res
[pass
], tcg_op
);
12441 tcg_temp_free_i64(tcg_op
);
12445 tcg_res
[1] = tcg_const_i64(0);
12447 for (pass
= 0; pass
< 2; pass
++) {
12448 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12449 tcg_temp_free_i64(tcg_res
[pass
]);
12453 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
12455 /* Implement SHLL and SHLL2 */
12457 int part
= is_q
? 2 : 0;
12458 TCGv_i64 tcg_res
[2];
12460 for (pass
= 0; pass
< 2; pass
++) {
12461 static NeonGenWidenFn
* const widenfns
[3] = {
12462 gen_helper_neon_widen_u8
,
12463 gen_helper_neon_widen_u16
,
12464 tcg_gen_extu_i32_i64
,
12466 NeonGenWidenFn
*widenfn
= widenfns
[size
];
12467 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12469 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
12470 tcg_res
[pass
] = tcg_temp_new_i64();
12471 widenfn(tcg_res
[pass
], tcg_op
);
12472 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
12474 tcg_temp_free_i32(tcg_op
);
12477 for (pass
= 0; pass
< 2; pass
++) {
12478 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12479 tcg_temp_free_i64(tcg_res
[pass
]);
12483 /* AdvSIMD two reg misc
12484 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
12485 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
12486 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
12487 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
12489 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
12491 int size
= extract32(insn
, 22, 2);
12492 int opcode
= extract32(insn
, 12, 5);
12493 bool u
= extract32(insn
, 29, 1);
12494 bool is_q
= extract32(insn
, 30, 1);
12495 int rn
= extract32(insn
, 5, 5);
12496 int rd
= extract32(insn
, 0, 5);
12497 bool need_fpstatus
= false;
12498 bool need_rmode
= false;
12500 TCGv_i32 tcg_rmode
;
12501 TCGv_ptr tcg_fpstatus
;
12504 case 0x0: /* REV64, REV32 */
12505 case 0x1: /* REV16 */
12506 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
12508 case 0x5: /* CNT, NOT, RBIT */
12509 if (u
&& size
== 0) {
12512 } else if (u
&& size
== 1) {
12515 } else if (!u
&& size
== 0) {
12519 unallocated_encoding(s
);
12521 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
12522 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
12524 unallocated_encoding(s
);
12527 if (!fp_access_check(s
)) {
12531 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
12533 case 0x4: /* CLS, CLZ */
12535 unallocated_encoding(s
);
12539 case 0x2: /* SADDLP, UADDLP */
12540 case 0x6: /* SADALP, UADALP */
12542 unallocated_encoding(s
);
12545 if (!fp_access_check(s
)) {
12548 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
12550 case 0x13: /* SHLL, SHLL2 */
12551 if (u
== 0 || size
== 3) {
12552 unallocated_encoding(s
);
12555 if (!fp_access_check(s
)) {
12558 handle_shll(s
, is_q
, size
, rn
, rd
);
12560 case 0xa: /* CMLT */
12562 unallocated_encoding(s
);
12566 case 0x8: /* CMGT, CMGE */
12567 case 0x9: /* CMEQ, CMLE */
12568 case 0xb: /* ABS, NEG */
12569 if (size
== 3 && !is_q
) {
12570 unallocated_encoding(s
);
12574 case 0x3: /* SUQADD, USQADD */
12575 if (size
== 3 && !is_q
) {
12576 unallocated_encoding(s
);
12579 if (!fp_access_check(s
)) {
12582 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
12584 case 0x7: /* SQABS, SQNEG */
12585 if (size
== 3 && !is_q
) {
12586 unallocated_encoding(s
);
12591 case 0x16 ... 0x1f:
12593 /* Floating point: U, size[1] and opcode indicate operation;
12594 * size[0] indicates single or double precision.
12596 int is_double
= extract32(size
, 0, 1);
12597 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
12598 size
= is_double
? 3 : 2;
12600 case 0x2f: /* FABS */
12601 case 0x6f: /* FNEG */
12602 if (size
== 3 && !is_q
) {
12603 unallocated_encoding(s
);
12607 case 0x1d: /* SCVTF */
12608 case 0x5d: /* UCVTF */
12610 bool is_signed
= (opcode
== 0x1d) ? true : false;
12611 int elements
= is_double
? 2 : is_q
? 4 : 2;
12612 if (is_double
&& !is_q
) {
12613 unallocated_encoding(s
);
12616 if (!fp_access_check(s
)) {
12619 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
12622 case 0x2c: /* FCMGT (zero) */
12623 case 0x2d: /* FCMEQ (zero) */
12624 case 0x2e: /* FCMLT (zero) */
12625 case 0x6c: /* FCMGE (zero) */
12626 case 0x6d: /* FCMLE (zero) */
12627 if (size
== 3 && !is_q
) {
12628 unallocated_encoding(s
);
12631 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12633 case 0x7f: /* FSQRT */
12634 if (size
== 3 && !is_q
) {
12635 unallocated_encoding(s
);
12639 case 0x1a: /* FCVTNS */
12640 case 0x1b: /* FCVTMS */
12641 case 0x3a: /* FCVTPS */
12642 case 0x3b: /* FCVTZS */
12643 case 0x5a: /* FCVTNU */
12644 case 0x5b: /* FCVTMU */
12645 case 0x7a: /* FCVTPU */
12646 case 0x7b: /* FCVTZU */
12647 need_fpstatus
= true;
12649 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12650 if (size
== 3 && !is_q
) {
12651 unallocated_encoding(s
);
12655 case 0x5c: /* FCVTAU */
12656 case 0x1c: /* FCVTAS */
12657 need_fpstatus
= true;
12659 rmode
= FPROUNDING_TIEAWAY
;
12660 if (size
== 3 && !is_q
) {
12661 unallocated_encoding(s
);
12665 case 0x3c: /* URECPE */
12667 unallocated_encoding(s
);
12671 case 0x3d: /* FRECPE */
12672 case 0x7d: /* FRSQRTE */
12673 if (size
== 3 && !is_q
) {
12674 unallocated_encoding(s
);
12677 if (!fp_access_check(s
)) {
12680 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12682 case 0x56: /* FCVTXN, FCVTXN2 */
12684 unallocated_encoding(s
);
12688 case 0x16: /* FCVTN, FCVTN2 */
12689 /* handle_2misc_narrow does a 2*size -> size operation, but these
12690 * instructions encode the source size rather than dest size.
12692 if (!fp_access_check(s
)) {
12695 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
12697 case 0x17: /* FCVTL, FCVTL2 */
12698 if (!fp_access_check(s
)) {
12701 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
12703 case 0x18: /* FRINTN */
12704 case 0x19: /* FRINTM */
12705 case 0x38: /* FRINTP */
12706 case 0x39: /* FRINTZ */
12708 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12710 case 0x59: /* FRINTX */
12711 case 0x79: /* FRINTI */
12712 need_fpstatus
= true;
12713 if (size
== 3 && !is_q
) {
12714 unallocated_encoding(s
);
12718 case 0x58: /* FRINTA */
12720 rmode
= FPROUNDING_TIEAWAY
;
12721 need_fpstatus
= true;
12722 if (size
== 3 && !is_q
) {
12723 unallocated_encoding(s
);
12727 case 0x7c: /* URSQRTE */
12729 unallocated_encoding(s
);
12733 case 0x1e: /* FRINT32Z */
12734 case 0x1f: /* FRINT64Z */
12736 rmode
= FPROUNDING_ZERO
;
12738 case 0x5e: /* FRINT32X */
12739 case 0x5f: /* FRINT64X */
12740 need_fpstatus
= true;
12741 if ((size
== 3 && !is_q
) || !dc_isar_feature(aa64_frint
, s
)) {
12742 unallocated_encoding(s
);
12747 unallocated_encoding(s
);
12753 unallocated_encoding(s
);
12757 if (!fp_access_check(s
)) {
12761 if (need_fpstatus
|| need_rmode
) {
12762 tcg_fpstatus
= get_fpstatus_ptr(false);
12764 tcg_fpstatus
= NULL
;
12767 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12768 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12775 if (u
&& size
== 0) { /* NOT */
12776 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_not
, 0);
12780 case 0x8: /* CMGT, CMGE */
12782 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_cge0
, size
);
12784 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_cgt0
, size
);
12787 case 0x9: /* CMEQ, CMLE */
12789 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_cle0
, size
);
12791 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_ceq0
, size
);
12794 case 0xa: /* CMLT */
12795 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_clt0
, size
);
12798 if (u
) { /* ABS, NEG */
12799 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_neg
, size
);
12801 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_abs
, size
);
12807 /* All 64-bit element operations can be shared with scalar 2misc */
12810 /* Coverity claims (size == 3 && !is_q) has been eliminated
12811 * from all paths leading to here.
12813 tcg_debug_assert(is_q
);
12814 for (pass
= 0; pass
< 2; pass
++) {
12815 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12816 TCGv_i64 tcg_res
= tcg_temp_new_i64();
12818 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12820 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
12821 tcg_rmode
, tcg_fpstatus
);
12823 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12825 tcg_temp_free_i64(tcg_res
);
12826 tcg_temp_free_i64(tcg_op
);
12831 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
12832 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12833 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12835 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
12838 /* Special cases for 32 bit elements */
12840 case 0x4: /* CLS */
12842 tcg_gen_clzi_i32(tcg_res
, tcg_op
, 32);
12844 tcg_gen_clrsb_i32(tcg_res
, tcg_op
);
12847 case 0x7: /* SQABS, SQNEG */
12849 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
12851 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
12854 case 0x2f: /* FABS */
12855 gen_helper_vfp_abss(tcg_res
, tcg_op
);
12857 case 0x6f: /* FNEG */
12858 gen_helper_vfp_negs(tcg_res
, tcg_op
);
12860 case 0x7f: /* FSQRT */
12861 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
12863 case 0x1a: /* FCVTNS */
12864 case 0x1b: /* FCVTMS */
12865 case 0x1c: /* FCVTAS */
12866 case 0x3a: /* FCVTPS */
12867 case 0x3b: /* FCVTZS */
12869 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12870 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
12871 tcg_shift
, tcg_fpstatus
);
12872 tcg_temp_free_i32(tcg_shift
);
12875 case 0x5a: /* FCVTNU */
12876 case 0x5b: /* FCVTMU */
12877 case 0x5c: /* FCVTAU */
12878 case 0x7a: /* FCVTPU */
12879 case 0x7b: /* FCVTZU */
12881 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12882 gen_helper_vfp_touls(tcg_res
, tcg_op
,
12883 tcg_shift
, tcg_fpstatus
);
12884 tcg_temp_free_i32(tcg_shift
);
12887 case 0x18: /* FRINTN */
12888 case 0x19: /* FRINTM */
12889 case 0x38: /* FRINTP */
12890 case 0x39: /* FRINTZ */
12891 case 0x58: /* FRINTA */
12892 case 0x79: /* FRINTI */
12893 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
12895 case 0x59: /* FRINTX */
12896 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12898 case 0x7c: /* URSQRTE */
12899 gen_helper_rsqrte_u32(tcg_res
, tcg_op
);
12901 case 0x1e: /* FRINT32Z */
12902 case 0x5e: /* FRINT32X */
12903 gen_helper_frint32_s(tcg_res
, tcg_op
, tcg_fpstatus
);
12905 case 0x1f: /* FRINT64Z */
12906 case 0x5f: /* FRINT64X */
12907 gen_helper_frint64_s(tcg_res
, tcg_op
, tcg_fpstatus
);
12910 g_assert_not_reached();
12913 /* Use helpers for 8 and 16 bit elements */
12915 case 0x5: /* CNT, RBIT */
12916 /* For these two insns size is part of the opcode specifier
12917 * (handled earlier); they always operate on byte elements.
12920 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
12922 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
12925 case 0x7: /* SQABS, SQNEG */
12927 NeonGenOneOpEnvFn
*genfn
;
12928 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
12929 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
12930 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
12932 genfn
= fns
[size
][u
];
12933 genfn(tcg_res
, cpu_env
, tcg_op
);
12936 case 0x4: /* CLS, CLZ */
12939 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
12941 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
12945 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
12947 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
12952 g_assert_not_reached();
12956 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
12958 tcg_temp_free_i32(tcg_res
);
12959 tcg_temp_free_i32(tcg_op
);
12962 clear_vec_high(s
, is_q
, rd
);
12965 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12966 tcg_temp_free_i32(tcg_rmode
);
12968 if (need_fpstatus
) {
12969 tcg_temp_free_ptr(tcg_fpstatus
);
12973 /* AdvSIMD [scalar] two register miscellaneous (FP16)
12975 * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0
12976 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12977 * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd |
12978 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12979 * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00
12980 * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800
12982 * This actually covers two groups where scalar access is governed by
12983 * bit 28. A bunch of the instructions (float to integral) only exist
12984 * in the vector form and are un-allocated for the scalar decode. Also
12985 * in the scalar decode Q is always 1.
12987 static void disas_simd_two_reg_misc_fp16(DisasContext
*s
, uint32_t insn
)
12989 int fpop
, opcode
, a
, u
;
12993 bool only_in_vector
= false;
12996 TCGv_i32 tcg_rmode
= NULL
;
12997 TCGv_ptr tcg_fpstatus
= NULL
;
12998 bool need_rmode
= false;
12999 bool need_fpst
= true;
13002 if (!dc_isar_feature(aa64_fp16
, s
)) {
13003 unallocated_encoding(s
);
13007 rd
= extract32(insn
, 0, 5);
13008 rn
= extract32(insn
, 5, 5);
13010 a
= extract32(insn
, 23, 1);
13011 u
= extract32(insn
, 29, 1);
13012 is_scalar
= extract32(insn
, 28, 1);
13013 is_q
= extract32(insn
, 30, 1);
13015 opcode
= extract32(insn
, 12, 5);
13016 fpop
= deposit32(opcode
, 5, 1, a
);
13017 fpop
= deposit32(fpop
, 6, 1, u
);
13019 rd
= extract32(insn
, 0, 5);
13020 rn
= extract32(insn
, 5, 5);
13023 case 0x1d: /* SCVTF */
13024 case 0x5d: /* UCVTF */
13031 elements
= (is_q
? 8 : 4);
13034 if (!fp_access_check(s
)) {
13037 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !u
, 0, MO_16
);
13041 case 0x2c: /* FCMGT (zero) */
13042 case 0x2d: /* FCMEQ (zero) */
13043 case 0x2e: /* FCMLT (zero) */
13044 case 0x6c: /* FCMGE (zero) */
13045 case 0x6d: /* FCMLE (zero) */
13046 handle_2misc_fcmp_zero(s
, fpop
, is_scalar
, 0, is_q
, MO_16
, rn
, rd
);
13048 case 0x3d: /* FRECPE */
13049 case 0x3f: /* FRECPX */
13051 case 0x18: /* FRINTN */
13053 only_in_vector
= true;
13054 rmode
= FPROUNDING_TIEEVEN
;
13056 case 0x19: /* FRINTM */
13058 only_in_vector
= true;
13059 rmode
= FPROUNDING_NEGINF
;
13061 case 0x38: /* FRINTP */
13063 only_in_vector
= true;
13064 rmode
= FPROUNDING_POSINF
;
13066 case 0x39: /* FRINTZ */
13068 only_in_vector
= true;
13069 rmode
= FPROUNDING_ZERO
;
13071 case 0x58: /* FRINTA */
13073 only_in_vector
= true;
13074 rmode
= FPROUNDING_TIEAWAY
;
13076 case 0x59: /* FRINTX */
13077 case 0x79: /* FRINTI */
13078 only_in_vector
= true;
13079 /* current rounding mode */
13081 case 0x1a: /* FCVTNS */
13083 rmode
= FPROUNDING_TIEEVEN
;
13085 case 0x1b: /* FCVTMS */
13087 rmode
= FPROUNDING_NEGINF
;
13089 case 0x1c: /* FCVTAS */
13091 rmode
= FPROUNDING_TIEAWAY
;
13093 case 0x3a: /* FCVTPS */
13095 rmode
= FPROUNDING_POSINF
;
13097 case 0x3b: /* FCVTZS */
13099 rmode
= FPROUNDING_ZERO
;
13101 case 0x5a: /* FCVTNU */
13103 rmode
= FPROUNDING_TIEEVEN
;
13105 case 0x5b: /* FCVTMU */
13107 rmode
= FPROUNDING_NEGINF
;
13109 case 0x5c: /* FCVTAU */
13111 rmode
= FPROUNDING_TIEAWAY
;
13113 case 0x7a: /* FCVTPU */
13115 rmode
= FPROUNDING_POSINF
;
13117 case 0x7b: /* FCVTZU */
13119 rmode
= FPROUNDING_ZERO
;
13121 case 0x2f: /* FABS */
13122 case 0x6f: /* FNEG */
13125 case 0x7d: /* FRSQRTE */
13126 case 0x7f: /* FSQRT (vector) */
13129 fprintf(stderr
, "%s: insn %#04x fpop %#2x\n", __func__
, insn
, fpop
);
13130 g_assert_not_reached();
13134 /* Check additional constraints for the scalar encoding */
13137 unallocated_encoding(s
);
13140 /* FRINTxx is only in the vector form */
13141 if (only_in_vector
) {
13142 unallocated_encoding(s
);
13147 if (!fp_access_check(s
)) {
13151 if (need_rmode
|| need_fpst
) {
13152 tcg_fpstatus
= get_fpstatus_ptr(true);
13156 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
13157 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
13161 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
13162 TCGv_i32 tcg_res
= tcg_temp_new_i32();
13165 case 0x1a: /* FCVTNS */
13166 case 0x1b: /* FCVTMS */
13167 case 0x1c: /* FCVTAS */
13168 case 0x3a: /* FCVTPS */
13169 case 0x3b: /* FCVTZS */
13170 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
13172 case 0x3d: /* FRECPE */
13173 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13175 case 0x3f: /* FRECPX */
13176 gen_helper_frecpx_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13178 case 0x5a: /* FCVTNU */
13179 case 0x5b: /* FCVTMU */
13180 case 0x5c: /* FCVTAU */
13181 case 0x7a: /* FCVTPU */
13182 case 0x7b: /* FCVTZU */
13183 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
13185 case 0x6f: /* FNEG */
13186 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
13188 case 0x7d: /* FRSQRTE */
13189 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13192 g_assert_not_reached();
13195 /* limit any sign extension going on */
13196 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0xffff);
13197 write_fp_sreg(s
, rd
, tcg_res
);
13199 tcg_temp_free_i32(tcg_res
);
13200 tcg_temp_free_i32(tcg_op
);
13202 for (pass
= 0; pass
< (is_q
? 8 : 4); pass
++) {
13203 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13204 TCGv_i32 tcg_res
= tcg_temp_new_i32();
13206 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_16
);
13209 case 0x1a: /* FCVTNS */
13210 case 0x1b: /* FCVTMS */
13211 case 0x1c: /* FCVTAS */
13212 case 0x3a: /* FCVTPS */
13213 case 0x3b: /* FCVTZS */
13214 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
13216 case 0x3d: /* FRECPE */
13217 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13219 case 0x5a: /* FCVTNU */
13220 case 0x5b: /* FCVTMU */
13221 case 0x5c: /* FCVTAU */
13222 case 0x7a: /* FCVTPU */
13223 case 0x7b: /* FCVTZU */
13224 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
13226 case 0x18: /* FRINTN */
13227 case 0x19: /* FRINTM */
13228 case 0x38: /* FRINTP */
13229 case 0x39: /* FRINTZ */
13230 case 0x58: /* FRINTA */
13231 case 0x79: /* FRINTI */
13232 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, tcg_fpstatus
);
13234 case 0x59: /* FRINTX */
13235 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
13237 case 0x2f: /* FABS */
13238 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
13240 case 0x6f: /* FNEG */
13241 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
13243 case 0x7d: /* FRSQRTE */
13244 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13246 case 0x7f: /* FSQRT */
13247 gen_helper_sqrt_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13250 g_assert_not_reached();
13253 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
13255 tcg_temp_free_i32(tcg_res
);
13256 tcg_temp_free_i32(tcg_op
);
13259 clear_vec_high(s
, is_q
, rd
);
13263 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
13264 tcg_temp_free_i32(tcg_rmode
);
13267 if (tcg_fpstatus
) {
13268 tcg_temp_free_ptr(tcg_fpstatus
);
13272 /* AdvSIMD scalar x indexed element
13273 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
13274 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
13275 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
13276 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
13277 * AdvSIMD vector x indexed element
13278 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
13279 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
13280 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
13281 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
13283 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
13285 /* This encoding has two kinds of instruction:
13286 * normal, where we perform elt x idxelt => elt for each
13287 * element in the vector
13288 * long, where we perform elt x idxelt and generate a result of
13289 * double the width of the input element
13290 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
13292 bool is_scalar
= extract32(insn
, 28, 1);
13293 bool is_q
= extract32(insn
, 30, 1);
13294 bool u
= extract32(insn
, 29, 1);
13295 int size
= extract32(insn
, 22, 2);
13296 int l
= extract32(insn
, 21, 1);
13297 int m
= extract32(insn
, 20, 1);
13298 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
13299 int rm
= extract32(insn
, 16, 4);
13300 int opcode
= extract32(insn
, 12, 4);
13301 int h
= extract32(insn
, 11, 1);
13302 int rn
= extract32(insn
, 5, 5);
13303 int rd
= extract32(insn
, 0, 5);
13304 bool is_long
= false;
13306 bool is_fp16
= false;
13310 switch (16 * u
+ opcode
) {
13311 case 0x08: /* MUL */
13312 case 0x10: /* MLA */
13313 case 0x14: /* MLS */
13315 unallocated_encoding(s
);
13319 case 0x02: /* SMLAL, SMLAL2 */
13320 case 0x12: /* UMLAL, UMLAL2 */
13321 case 0x06: /* SMLSL, SMLSL2 */
13322 case 0x16: /* UMLSL, UMLSL2 */
13323 case 0x0a: /* SMULL, SMULL2 */
13324 case 0x1a: /* UMULL, UMULL2 */
13326 unallocated_encoding(s
);
13331 case 0x03: /* SQDMLAL, SQDMLAL2 */
13332 case 0x07: /* SQDMLSL, SQDMLSL2 */
13333 case 0x0b: /* SQDMULL, SQDMULL2 */
13336 case 0x0c: /* SQDMULH */
13337 case 0x0d: /* SQRDMULH */
13339 case 0x01: /* FMLA */
13340 case 0x05: /* FMLS */
13341 case 0x09: /* FMUL */
13342 case 0x19: /* FMULX */
13345 case 0x1d: /* SQRDMLAH */
13346 case 0x1f: /* SQRDMLSH */
13347 if (!dc_isar_feature(aa64_rdm
, s
)) {
13348 unallocated_encoding(s
);
13352 case 0x0e: /* SDOT */
13353 case 0x1e: /* UDOT */
13354 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_dp
, s
)) {
13355 unallocated_encoding(s
);
13359 case 0x11: /* FCMLA #0 */
13360 case 0x13: /* FCMLA #90 */
13361 case 0x15: /* FCMLA #180 */
13362 case 0x17: /* FCMLA #270 */
13363 if (is_scalar
|| !dc_isar_feature(aa64_fcma
, s
)) {
13364 unallocated_encoding(s
);
13369 case 0x00: /* FMLAL */
13370 case 0x04: /* FMLSL */
13371 case 0x18: /* FMLAL2 */
13372 case 0x1c: /* FMLSL2 */
13373 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_fhm
, s
)) {
13374 unallocated_encoding(s
);
13378 /* is_fp, but we pass cpu_env not fp_status. */
13381 unallocated_encoding(s
);
13386 case 1: /* normal fp */
13387 /* convert insn encoded size to MemOp size */
13389 case 0: /* half-precision */
13393 case MO_32
: /* single precision */
13394 case MO_64
: /* double precision */
13397 unallocated_encoding(s
);
13402 case 2: /* complex fp */
13403 /* Each indexable element is a complex pair. */
13408 unallocated_encoding(s
);
13416 unallocated_encoding(s
);
13421 default: /* integer */
13425 unallocated_encoding(s
);
13430 if (is_fp16
&& !dc_isar_feature(aa64_fp16
, s
)) {
13431 unallocated_encoding(s
);
13435 /* Given MemOp size, adjust register and indexing. */
13438 index
= h
<< 2 | l
<< 1 | m
;
13441 index
= h
<< 1 | l
;
13446 unallocated_encoding(s
);
13453 g_assert_not_reached();
13456 if (!fp_access_check(s
)) {
13461 fpst
= get_fpstatus_ptr(is_fp16
);
13466 switch (16 * u
+ opcode
) {
13467 case 0x0e: /* SDOT */
13468 case 0x1e: /* UDOT */
13469 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, index
,
13470 u
? gen_helper_gvec_udot_idx_b
13471 : gen_helper_gvec_sdot_idx_b
);
13473 case 0x11: /* FCMLA #0 */
13474 case 0x13: /* FCMLA #90 */
13475 case 0x15: /* FCMLA #180 */
13476 case 0x17: /* FCMLA #270 */
13478 int rot
= extract32(insn
, 13, 2);
13479 int data
= (index
<< 2) | rot
;
13480 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
13481 vec_full_reg_offset(s
, rn
),
13482 vec_full_reg_offset(s
, rm
), fpst
,
13483 is_q
? 16 : 8, vec_full_reg_size(s
), data
,
13485 ? gen_helper_gvec_fcmlas_idx
13486 : gen_helper_gvec_fcmlah_idx
);
13487 tcg_temp_free_ptr(fpst
);
13491 case 0x00: /* FMLAL */
13492 case 0x04: /* FMLSL */
13493 case 0x18: /* FMLAL2 */
13494 case 0x1c: /* FMLSL2 */
13496 int is_s
= extract32(opcode
, 2, 1);
13498 int data
= (index
<< 2) | (is_2
<< 1) | is_s
;
13499 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
13500 vec_full_reg_offset(s
, rn
),
13501 vec_full_reg_offset(s
, rm
), cpu_env
,
13502 is_q
? 16 : 8, vec_full_reg_size(s
),
13503 data
, gen_helper_gvec_fmlal_idx_a64
);
13509 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13512 assert(is_fp
&& is_q
&& !is_long
);
13514 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
13516 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13517 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13518 TCGv_i64 tcg_res
= tcg_temp_new_i64();
13520 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
13522 switch (16 * u
+ opcode
) {
13523 case 0x05: /* FMLS */
13524 /* As usual for ARM, separate negation for fused multiply-add */
13525 gen_helper_vfp_negd(tcg_op
, tcg_op
);
13527 case 0x01: /* FMLA */
13528 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
13529 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
13531 case 0x09: /* FMUL */
13532 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13534 case 0x19: /* FMULX */
13535 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13538 g_assert_not_reached();
13541 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
13542 tcg_temp_free_i64(tcg_op
);
13543 tcg_temp_free_i64(tcg_res
);
13546 tcg_temp_free_i64(tcg_idx
);
13547 clear_vec_high(s
, !is_scalar
, rd
);
13548 } else if (!is_long
) {
13549 /* 32 bit floating point, or 16 or 32 bit integer.
13550 * For the 16 bit scalar case we use the usual Neon helpers and
13551 * rely on the fact that 0 op 0 == 0 with no side effects.
13553 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13554 int pass
, maxpasses
;
13559 maxpasses
= is_q
? 4 : 2;
13562 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13564 if (size
== 1 && !is_scalar
) {
13565 /* The simplest way to handle the 16x16 indexed ops is to duplicate
13566 * the index into both halves of the 32 bit tcg_idx and then use
13567 * the usual Neon helpers.
13569 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13572 for (pass
= 0; pass
< maxpasses
; pass
++) {
13573 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13574 TCGv_i32 tcg_res
= tcg_temp_new_i32();
13576 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
13578 switch (16 * u
+ opcode
) {
13579 case 0x08: /* MUL */
13580 case 0x10: /* MLA */
13581 case 0x14: /* MLS */
13583 static NeonGenTwoOpFn
* const fns
[2][2] = {
13584 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
13585 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
13587 NeonGenTwoOpFn
*genfn
;
13588 bool is_sub
= opcode
== 0x4;
13591 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
13593 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
13595 if (opcode
== 0x8) {
13598 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
13599 genfn
= fns
[size
- 1][is_sub
];
13600 genfn(tcg_res
, tcg_op
, tcg_res
);
13603 case 0x05: /* FMLS */
13604 case 0x01: /* FMLA */
13605 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13606 is_scalar
? size
: MO_32
);
13609 if (opcode
== 0x5) {
13610 /* As usual for ARM, separate negation for fused
13612 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80008000);
13615 gen_helper_advsimd_muladdh(tcg_res
, tcg_op
, tcg_idx
,
13618 gen_helper_advsimd_muladd2h(tcg_res
, tcg_op
, tcg_idx
,
13623 if (opcode
== 0x5) {
13624 /* As usual for ARM, separate negation for
13625 * fused multiply-add */
13626 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80000000);
13628 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
,
13632 g_assert_not_reached();
13635 case 0x09: /* FMUL */
13639 gen_helper_advsimd_mulh(tcg_res
, tcg_op
,
13642 gen_helper_advsimd_mul2h(tcg_res
, tcg_op
,
13647 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13650 g_assert_not_reached();
13653 case 0x19: /* FMULX */
13657 gen_helper_advsimd_mulxh(tcg_res
, tcg_op
,
13660 gen_helper_advsimd_mulx2h(tcg_res
, tcg_op
,
13665 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13668 g_assert_not_reached();
13671 case 0x0c: /* SQDMULH */
13673 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
13676 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
13680 case 0x0d: /* SQRDMULH */
13682 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
13685 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
13689 case 0x1d: /* SQRDMLAH */
13690 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13691 is_scalar
? size
: MO_32
);
13693 gen_helper_neon_qrdmlah_s16(tcg_res
, cpu_env
,
13694 tcg_op
, tcg_idx
, tcg_res
);
13696 gen_helper_neon_qrdmlah_s32(tcg_res
, cpu_env
,
13697 tcg_op
, tcg_idx
, tcg_res
);
13700 case 0x1f: /* SQRDMLSH */
13701 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13702 is_scalar
? size
: MO_32
);
13704 gen_helper_neon_qrdmlsh_s16(tcg_res
, cpu_env
,
13705 tcg_op
, tcg_idx
, tcg_res
);
13707 gen_helper_neon_qrdmlsh_s32(tcg_res
, cpu_env
,
13708 tcg_op
, tcg_idx
, tcg_res
);
13712 g_assert_not_reached();
13716 write_fp_sreg(s
, rd
, tcg_res
);
13718 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
13721 tcg_temp_free_i32(tcg_op
);
13722 tcg_temp_free_i32(tcg_res
);
13725 tcg_temp_free_i32(tcg_idx
);
13726 clear_vec_high(s
, is_q
, rd
);
13728 /* long ops: 16x16->32 or 32x32->64 */
13729 TCGv_i64 tcg_res
[2];
13731 bool satop
= extract32(opcode
, 0, 1);
13732 MemOp memop
= MO_32
;
13739 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13741 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
13743 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13744 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13745 TCGv_i64 tcg_passres
;
13751 passelt
= pass
+ (is_q
* 2);
13754 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
13756 tcg_res
[pass
] = tcg_temp_new_i64();
13758 if (opcode
== 0xa || opcode
== 0xb) {
13759 /* Non-accumulating ops */
13760 tcg_passres
= tcg_res
[pass
];
13762 tcg_passres
= tcg_temp_new_i64();
13765 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
13766 tcg_temp_free_i64(tcg_op
);
13769 /* saturating, doubling */
13770 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
13771 tcg_passres
, tcg_passres
);
13774 if (opcode
== 0xa || opcode
== 0xb) {
13778 /* Accumulating op: handle accumulate step */
13779 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13782 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13783 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13785 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13786 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13788 case 0x7: /* SQDMLSL, SQDMLSL2 */
13789 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
13791 case 0x3: /* SQDMLAL, SQDMLAL2 */
13792 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
13797 g_assert_not_reached();
13799 tcg_temp_free_i64(tcg_passres
);
13801 tcg_temp_free_i64(tcg_idx
);
13803 clear_vec_high(s
, !is_scalar
, rd
);
13805 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13808 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13811 /* The simplest way to handle the 16x16 indexed ops is to
13812 * duplicate the index into both halves of the 32 bit tcg_idx
13813 * and then use the usual Neon helpers.
13815 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13818 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13819 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13820 TCGv_i64 tcg_passres
;
13823 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
13825 read_vec_element_i32(s
, tcg_op
, rn
,
13826 pass
+ (is_q
* 2), MO_32
);
13829 tcg_res
[pass
] = tcg_temp_new_i64();
13831 if (opcode
== 0xa || opcode
== 0xb) {
13832 /* Non-accumulating ops */
13833 tcg_passres
= tcg_res
[pass
];
13835 tcg_passres
= tcg_temp_new_i64();
13838 if (memop
& MO_SIGN
) {
13839 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
13841 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
13844 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
13845 tcg_passres
, tcg_passres
);
13847 tcg_temp_free_i32(tcg_op
);
13849 if (opcode
== 0xa || opcode
== 0xb) {
13853 /* Accumulating op: handle accumulate step */
13854 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13857 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13858 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
13861 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13862 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
13865 case 0x7: /* SQDMLSL, SQDMLSL2 */
13866 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
13868 case 0x3: /* SQDMLAL, SQDMLAL2 */
13869 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
13874 g_assert_not_reached();
13876 tcg_temp_free_i64(tcg_passres
);
13878 tcg_temp_free_i32(tcg_idx
);
13881 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
13886 tcg_res
[1] = tcg_const_i64(0);
13889 for (pass
= 0; pass
< 2; pass
++) {
13890 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13891 tcg_temp_free_i64(tcg_res
[pass
]);
13896 tcg_temp_free_ptr(fpst
);
13901 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13902 * +-----------------+------+-----------+--------+-----+------+------+
13903 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13904 * +-----------------+------+-----------+--------+-----+------+------+
13906 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
13908 int size
= extract32(insn
, 22, 2);
13909 int opcode
= extract32(insn
, 12, 5);
13910 int rn
= extract32(insn
, 5, 5);
13911 int rd
= extract32(insn
, 0, 5);
13913 gen_helper_gvec_2
*genfn2
= NULL
;
13914 gen_helper_gvec_3
*genfn3
= NULL
;
13916 if (!dc_isar_feature(aa64_aes
, s
) || size
!= 0) {
13917 unallocated_encoding(s
);
13922 case 0x4: /* AESE */
13924 genfn3
= gen_helper_crypto_aese
;
13926 case 0x6: /* AESMC */
13928 genfn2
= gen_helper_crypto_aesmc
;
13930 case 0x5: /* AESD */
13932 genfn3
= gen_helper_crypto_aese
;
13934 case 0x7: /* AESIMC */
13936 genfn2
= gen_helper_crypto_aesmc
;
13939 unallocated_encoding(s
);
13943 if (!fp_access_check(s
)) {
13947 gen_gvec_op2_ool(s
, true, rd
, rn
, decrypt
, genfn2
);
13949 gen_gvec_op3_ool(s
, true, rd
, rd
, rn
, decrypt
, genfn3
);
13953 /* Crypto three-reg SHA
13954 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
13955 * +-----------------+------+---+------+---+--------+-----+------+------+
13956 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
13957 * +-----------------+------+---+------+---+--------+-----+------+------+
13959 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
13961 int size
= extract32(insn
, 22, 2);
13962 int opcode
= extract32(insn
, 12, 3);
13963 int rm
= extract32(insn
, 16, 5);
13964 int rn
= extract32(insn
, 5, 5);
13965 int rd
= extract32(insn
, 0, 5);
13966 gen_helper_gvec_3
*genfn
;
13970 unallocated_encoding(s
);
13975 case 0: /* SHA1C */
13976 genfn
= gen_helper_crypto_sha1c
;
13977 feature
= dc_isar_feature(aa64_sha1
, s
);
13979 case 1: /* SHA1P */
13980 genfn
= gen_helper_crypto_sha1p
;
13981 feature
= dc_isar_feature(aa64_sha1
, s
);
13983 case 2: /* SHA1M */
13984 genfn
= gen_helper_crypto_sha1m
;
13985 feature
= dc_isar_feature(aa64_sha1
, s
);
13987 case 3: /* SHA1SU0 */
13988 genfn
= gen_helper_crypto_sha1su0
;
13989 feature
= dc_isar_feature(aa64_sha1
, s
);
13991 case 4: /* SHA256H */
13992 genfn
= gen_helper_crypto_sha256h
;
13993 feature
= dc_isar_feature(aa64_sha256
, s
);
13995 case 5: /* SHA256H2 */
13996 genfn
= gen_helper_crypto_sha256h2
;
13997 feature
= dc_isar_feature(aa64_sha256
, s
);
13999 case 6: /* SHA256SU1 */
14000 genfn
= gen_helper_crypto_sha256su1
;
14001 feature
= dc_isar_feature(aa64_sha256
, s
);
14004 unallocated_encoding(s
);
14009 unallocated_encoding(s
);
14013 if (!fp_access_check(s
)) {
14016 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, 0, genfn
);
14019 /* Crypto two-reg SHA
14020 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
14021 * +-----------------+------+-----------+--------+-----+------+------+
14022 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
14023 * +-----------------+------+-----------+--------+-----+------+------+
14025 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
14027 int size
= extract32(insn
, 22, 2);
14028 int opcode
= extract32(insn
, 12, 5);
14029 int rn
= extract32(insn
, 5, 5);
14030 int rd
= extract32(insn
, 0, 5);
14031 gen_helper_gvec_2
*genfn
;
14035 unallocated_encoding(s
);
14040 case 0: /* SHA1H */
14041 feature
= dc_isar_feature(aa64_sha1
, s
);
14042 genfn
= gen_helper_crypto_sha1h
;
14044 case 1: /* SHA1SU1 */
14045 feature
= dc_isar_feature(aa64_sha1
, s
);
14046 genfn
= gen_helper_crypto_sha1su1
;
14048 case 2: /* SHA256SU0 */
14049 feature
= dc_isar_feature(aa64_sha256
, s
);
14050 genfn
= gen_helper_crypto_sha256su0
;
14053 unallocated_encoding(s
);
14058 unallocated_encoding(s
);
14062 if (!fp_access_check(s
)) {
14065 gen_gvec_op2_ool(s
, true, rd
, rn
, 0, genfn
);
14068 static void gen_rax1_i64(TCGv_i64 d
, TCGv_i64 n
, TCGv_i64 m
)
14070 tcg_gen_rotli_i64(d
, m
, 1);
14071 tcg_gen_xor_i64(d
, d
, n
);
14074 static void gen_rax1_vec(unsigned vece
, TCGv_vec d
, TCGv_vec n
, TCGv_vec m
)
14076 tcg_gen_rotli_vec(vece
, d
, m
, 1);
14077 tcg_gen_xor_vec(vece
, d
, d
, n
);
14080 void gen_gvec_rax1(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
14081 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
)
14083 static const TCGOpcode vecop_list
[] = { INDEX_op_rotli_vec
, 0 };
14084 static const GVecGen3 op
= {
14085 .fni8
= gen_rax1_i64
,
14086 .fniv
= gen_rax1_vec
,
14087 .opt_opc
= vecop_list
,
14088 .fno
= gen_helper_crypto_rax1
,
14091 tcg_gen_gvec_3(rd_ofs
, rn_ofs
, rm_ofs
, opr_sz
, max_sz
, &op
);
14094 /* Crypto three-reg SHA512
14095 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
14096 * +-----------------------+------+---+---+-----+--------+------+------+
14097 * | 1 1 0 0 1 1 1 0 0 1 1 | Rm | 1 | O | 0 0 | opcode | Rn | Rd |
14098 * +-----------------------+------+---+---+-----+--------+------+------+
14100 static void disas_crypto_three_reg_sha512(DisasContext
*s
, uint32_t insn
)
14102 int opcode
= extract32(insn
, 10, 2);
14103 int o
= extract32(insn
, 14, 1);
14104 int rm
= extract32(insn
, 16, 5);
14105 int rn
= extract32(insn
, 5, 5);
14106 int rd
= extract32(insn
, 0, 5);
14108 gen_helper_gvec_3
*oolfn
= NULL
;
14109 GVecGen3Fn
*gvecfn
= NULL
;
14113 case 0: /* SHA512H */
14114 feature
= dc_isar_feature(aa64_sha512
, s
);
14115 oolfn
= gen_helper_crypto_sha512h
;
14117 case 1: /* SHA512H2 */
14118 feature
= dc_isar_feature(aa64_sha512
, s
);
14119 oolfn
= gen_helper_crypto_sha512h2
;
14121 case 2: /* SHA512SU1 */
14122 feature
= dc_isar_feature(aa64_sha512
, s
);
14123 oolfn
= gen_helper_crypto_sha512su1
;
14126 feature
= dc_isar_feature(aa64_sha3
, s
);
14127 gvecfn
= gen_gvec_rax1
;
14130 g_assert_not_reached();
14134 case 0: /* SM3PARTW1 */
14135 feature
= dc_isar_feature(aa64_sm3
, s
);
14136 oolfn
= gen_helper_crypto_sm3partw1
;
14138 case 1: /* SM3PARTW2 */
14139 feature
= dc_isar_feature(aa64_sm3
, s
);
14140 oolfn
= gen_helper_crypto_sm3partw2
;
14142 case 2: /* SM4EKEY */
14143 feature
= dc_isar_feature(aa64_sm4
, s
);
14144 oolfn
= gen_helper_crypto_sm4ekey
;
14147 unallocated_encoding(s
);
14153 unallocated_encoding(s
);
14157 if (!fp_access_check(s
)) {
14162 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, 0, oolfn
);
14164 gen_gvec_fn3(s
, true, rd
, rn
, rm
, gvecfn
, MO_64
);
14168 /* Crypto two-reg SHA512
14169 * 31 12 11 10 9 5 4 0
14170 * +-----------------------------------------+--------+------+------+
14171 * | 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 | opcode | Rn | Rd |
14172 * +-----------------------------------------+--------+------+------+
14174 static void disas_crypto_two_reg_sha512(DisasContext
*s
, uint32_t insn
)
14176 int opcode
= extract32(insn
, 10, 2);
14177 int rn
= extract32(insn
, 5, 5);
14178 int rd
= extract32(insn
, 0, 5);
14182 case 0: /* SHA512SU0 */
14183 feature
= dc_isar_feature(aa64_sha512
, s
);
14186 feature
= dc_isar_feature(aa64_sm4
, s
);
14189 unallocated_encoding(s
);
14194 unallocated_encoding(s
);
14198 if (!fp_access_check(s
)) {
14203 case 0: /* SHA512SU0 */
14204 gen_gvec_op2_ool(s
, true, rd
, rn
, 0, gen_helper_crypto_sha512su0
);
14207 gen_gvec_op3_ool(s
, true, rd
, rd
, rn
, 0, gen_helper_crypto_sm4e
);
14210 g_assert_not_reached();
14214 /* Crypto four-register
14215 * 31 23 22 21 20 16 15 14 10 9 5 4 0
14216 * +-------------------+-----+------+---+------+------+------+
14217 * | 1 1 0 0 1 1 1 0 0 | Op0 | Rm | 0 | Ra | Rn | Rd |
14218 * +-------------------+-----+------+---+------+------+------+
14220 static void disas_crypto_four_reg(DisasContext
*s
, uint32_t insn
)
14222 int op0
= extract32(insn
, 21, 2);
14223 int rm
= extract32(insn
, 16, 5);
14224 int ra
= extract32(insn
, 10, 5);
14225 int rn
= extract32(insn
, 5, 5);
14226 int rd
= extract32(insn
, 0, 5);
14232 feature
= dc_isar_feature(aa64_sha3
, s
);
14234 case 2: /* SM3SS1 */
14235 feature
= dc_isar_feature(aa64_sm3
, s
);
14238 unallocated_encoding(s
);
14243 unallocated_encoding(s
);
14247 if (!fp_access_check(s
)) {
14252 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
[2];
14255 tcg_op1
= tcg_temp_new_i64();
14256 tcg_op2
= tcg_temp_new_i64();
14257 tcg_op3
= tcg_temp_new_i64();
14258 tcg_res
[0] = tcg_temp_new_i64();
14259 tcg_res
[1] = tcg_temp_new_i64();
14261 for (pass
= 0; pass
< 2; pass
++) {
14262 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
14263 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
14264 read_vec_element(s
, tcg_op3
, ra
, pass
, MO_64
);
14268 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
14271 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
14273 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
14275 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
14276 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
14278 tcg_temp_free_i64(tcg_op1
);
14279 tcg_temp_free_i64(tcg_op2
);
14280 tcg_temp_free_i64(tcg_op3
);
14281 tcg_temp_free_i64(tcg_res
[0]);
14282 tcg_temp_free_i64(tcg_res
[1]);
14284 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
, tcg_zero
;
14286 tcg_op1
= tcg_temp_new_i32();
14287 tcg_op2
= tcg_temp_new_i32();
14288 tcg_op3
= tcg_temp_new_i32();
14289 tcg_res
= tcg_temp_new_i32();
14290 tcg_zero
= tcg_const_i32(0);
14292 read_vec_element_i32(s
, tcg_op1
, rn
, 3, MO_32
);
14293 read_vec_element_i32(s
, tcg_op2
, rm
, 3, MO_32
);
14294 read_vec_element_i32(s
, tcg_op3
, ra
, 3, MO_32
);
14296 tcg_gen_rotri_i32(tcg_res
, tcg_op1
, 20);
14297 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op2
);
14298 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op3
);
14299 tcg_gen_rotri_i32(tcg_res
, tcg_res
, 25);
14301 write_vec_element_i32(s
, tcg_zero
, rd
, 0, MO_32
);
14302 write_vec_element_i32(s
, tcg_zero
, rd
, 1, MO_32
);
14303 write_vec_element_i32(s
, tcg_zero
, rd
, 2, MO_32
);
14304 write_vec_element_i32(s
, tcg_res
, rd
, 3, MO_32
);
14306 tcg_temp_free_i32(tcg_op1
);
14307 tcg_temp_free_i32(tcg_op2
);
14308 tcg_temp_free_i32(tcg_op3
);
14309 tcg_temp_free_i32(tcg_res
);
14310 tcg_temp_free_i32(tcg_zero
);
14315 * 31 21 20 16 15 10 9 5 4 0
14316 * +-----------------------+------+--------+------+------+
14317 * | 1 1 0 0 1 1 1 0 1 0 0 | Rm | imm6 | Rn | Rd |
14318 * +-----------------------+------+--------+------+------+
14320 static void disas_crypto_xar(DisasContext
*s
, uint32_t insn
)
14322 int rm
= extract32(insn
, 16, 5);
14323 int imm6
= extract32(insn
, 10, 6);
14324 int rn
= extract32(insn
, 5, 5);
14325 int rd
= extract32(insn
, 0, 5);
14326 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
14329 if (!dc_isar_feature(aa64_sha3
, s
)) {
14330 unallocated_encoding(s
);
14334 if (!fp_access_check(s
)) {
14338 tcg_op1
= tcg_temp_new_i64();
14339 tcg_op2
= tcg_temp_new_i64();
14340 tcg_res
[0] = tcg_temp_new_i64();
14341 tcg_res
[1] = tcg_temp_new_i64();
14343 for (pass
= 0; pass
< 2; pass
++) {
14344 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
14345 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
14347 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
14348 tcg_gen_rotri_i64(tcg_res
[pass
], tcg_res
[pass
], imm6
);
14350 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
14351 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
14353 tcg_temp_free_i64(tcg_op1
);
14354 tcg_temp_free_i64(tcg_op2
);
14355 tcg_temp_free_i64(tcg_res
[0]);
14356 tcg_temp_free_i64(tcg_res
[1]);
14359 /* Crypto three-reg imm2
14360 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
14361 * +-----------------------+------+-----+------+--------+------+------+
14362 * | 1 1 0 0 1 1 1 0 0 1 0 | Rm | 1 0 | imm2 | opcode | Rn | Rd |
14363 * +-----------------------+------+-----+------+--------+------+------+
14365 static void disas_crypto_three_reg_imm2(DisasContext
*s
, uint32_t insn
)
14367 static gen_helper_gvec_3
* const fns
[4] = {
14368 gen_helper_crypto_sm3tt1a
, gen_helper_crypto_sm3tt1b
,
14369 gen_helper_crypto_sm3tt2a
, gen_helper_crypto_sm3tt2b
,
14371 int opcode
= extract32(insn
, 10, 2);
14372 int imm2
= extract32(insn
, 12, 2);
14373 int rm
= extract32(insn
, 16, 5);
14374 int rn
= extract32(insn
, 5, 5);
14375 int rd
= extract32(insn
, 0, 5);
14377 if (!dc_isar_feature(aa64_sm3
, s
)) {
14378 unallocated_encoding(s
);
14382 if (!fp_access_check(s
)) {
14386 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, imm2
, fns
[opcode
]);
14389 /* C3.6 Data processing - SIMD, inc Crypto
14391 * As the decode gets a little complex we are using a table based
14392 * approach for this part of the decode.
14394 static const AArch64DecodeTable data_proc_simd
[] = {
14395 /* pattern , mask , fn */
14396 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
14397 { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra
},
14398 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
14399 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
14400 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
14401 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
14402 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
14403 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
14404 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
14405 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
14406 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
14407 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
14408 { 0x2e000000, 0xbf208400, disas_simd_ext
},
14409 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
14410 { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra
},
14411 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
14412 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
14413 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
14414 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
14415 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
14416 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
14417 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
14418 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
14419 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
14420 { 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512
},
14421 { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512
},
14422 { 0xce000000, 0xff808000, disas_crypto_four_reg
},
14423 { 0xce800000, 0xffe00000, disas_crypto_xar
},
14424 { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2
},
14425 { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16
},
14426 { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16
},
14427 { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16
},
14428 { 0x00000000, 0x00000000, NULL
}
14431 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
14433 /* Note that this is called with all non-FP cases from
14434 * table C3-6 so it must UNDEF for entries not specifically
14435 * allocated to instructions in that table.
14437 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
14441 unallocated_encoding(s
);
14445 /* C3.6 Data processing - SIMD and floating point */
14446 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
14448 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
14449 disas_data_proc_fp(s
, insn
);
14451 /* SIMD, including crypto */
14452 disas_data_proc_simd(s
, insn
);
14458 * @env: The cpu environment
14459 * @s: The DisasContext
14461 * Return true if the page is guarded.
14463 static bool is_guarded_page(CPUARMState
*env
, DisasContext
*s
)
14465 #ifdef CONFIG_USER_ONLY
14466 return false; /* FIXME */
14468 uint64_t addr
= s
->base
.pc_first
;
14469 int mmu_idx
= arm_to_core_mmu_idx(s
->mmu_idx
);
14470 unsigned int index
= tlb_index(env
, mmu_idx
, addr
);
14471 CPUTLBEntry
*entry
= tlb_entry(env
, mmu_idx
, addr
);
14474 * We test this immediately after reading an insn, which means
14475 * that any normal page must be in the TLB. The only exception
14476 * would be for executing from flash or device memory, which
14477 * does not retain the TLB entry.
14479 * FIXME: Assume false for those, for now. We could use
14480 * arm_cpu_get_phys_page_attrs_debug to re-read the page
14481 * table entry even for that case.
14483 return (tlb_hit(entry
->addr_code
, addr
) &&
14484 arm_tlb_bti_gp(&env_tlb(env
)->d
[mmu_idx
].iotlb
[index
].attrs
));
14489 * btype_destination_ok:
14490 * @insn: The instruction at the branch destination
14491 * @bt: SCTLR_ELx.BT
14492 * @btype: PSTATE.BTYPE, and is non-zero
14494 * On a guarded page, there are a limited number of insns
14495 * that may be present at the branch target:
14496 * - branch target identifiers,
14497 * - paciasp, pacibsp,
14500 * Anything else causes a Branch Target Exception.
14502 * Return true if the branch is compatible, false to raise BTITRAP.
14504 static bool btype_destination_ok(uint32_t insn
, bool bt
, int btype
)
14506 if ((insn
& 0xfffff01fu
) == 0xd503201fu
) {
14508 switch (extract32(insn
, 5, 7)) {
14509 case 0b011001: /* PACIASP */
14510 case 0b011011: /* PACIBSP */
14512 * If SCTLR_ELx.BT, then PACI*SP are not compatible
14513 * with btype == 3. Otherwise all btype are ok.
14515 return !bt
|| btype
!= 3;
14516 case 0b100000: /* BTI */
14517 /* Not compatible with any btype. */
14519 case 0b100010: /* BTI c */
14520 /* Not compatible with btype == 3 */
14522 case 0b100100: /* BTI j */
14523 /* Not compatible with btype == 2 */
14525 case 0b100110: /* BTI jc */
14526 /* Compatible with any btype. */
14530 switch (insn
& 0xffe0001fu
) {
14531 case 0xd4200000u
: /* BRK */
14532 case 0xd4400000u
: /* HLT */
14533 /* Give priority to the breakpoint exception. */
14540 /* C3.1 A64 instruction index by encoding */
14541 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
14545 s
->pc_curr
= s
->base
.pc_next
;
14546 insn
= arm_ldl_code(env
, s
->base
.pc_next
, s
->sctlr_b
);
14548 s
->base
.pc_next
+= 4;
14550 s
->fp_access_checked
= false;
14552 if (dc_isar_feature(aa64_bti
, s
)) {
14553 if (s
->base
.num_insns
== 1) {
14555 * At the first insn of the TB, compute s->guarded_page.
14556 * We delayed computing this until successfully reading
14557 * the first insn of the TB, above. This (mostly) ensures
14558 * that the softmmu tlb entry has been populated, and the
14559 * page table GP bit is available.
14561 * Note that we need to compute this even if btype == 0,
14562 * because this value is used for BR instructions later
14563 * where ENV is not available.
14565 s
->guarded_page
= is_guarded_page(env
, s
);
14567 /* First insn can have btype set to non-zero. */
14568 tcg_debug_assert(s
->btype
>= 0);
14571 * Note that the Branch Target Exception has fairly high
14572 * priority -- below debugging exceptions but above most
14573 * everything else. This allows us to handle this now
14574 * instead of waiting until the insn is otherwise decoded.
14578 && !btype_destination_ok(insn
, s
->bt
, s
->btype
)) {
14579 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
14580 syn_btitrap(s
->btype
),
14581 default_exception_el(s
));
14585 /* Not the first insn: btype must be 0. */
14586 tcg_debug_assert(s
->btype
== 0);
14590 switch (extract32(insn
, 25, 4)) {
14591 case 0x0: case 0x1: case 0x3: /* UNALLOCATED */
14592 unallocated_encoding(s
);
14595 if (!dc_isar_feature(aa64_sve
, s
) || !disas_sve(s
, insn
)) {
14596 unallocated_encoding(s
);
14599 case 0x8: case 0x9: /* Data processing - immediate */
14600 disas_data_proc_imm(s
, insn
);
14602 case 0xa: case 0xb: /* Branch, exception generation and system insns */
14603 disas_b_exc_sys(s
, insn
);
14608 case 0xe: /* Loads and stores */
14609 disas_ldst(s
, insn
);
14612 case 0xd: /* Data processing - register */
14613 disas_data_proc_reg(s
, insn
);
14616 case 0xf: /* Data processing - SIMD and floating point */
14617 disas_data_proc_simd_fp(s
, insn
);
14620 assert(FALSE
); /* all 15 cases should be handled above */
14624 /* if we allocated any temporaries, free them here */
14628 * After execution of most insns, btype is reset to 0.
14629 * Note that we set btype == -1 when the insn sets btype.
14631 if (s
->btype
> 0 && s
->base
.is_jmp
!= DISAS_NORETURN
) {
14636 static void aarch64_tr_init_disas_context(DisasContextBase
*dcbase
,
14639 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14640 CPUARMState
*env
= cpu
->env_ptr
;
14641 ARMCPU
*arm_cpu
= env_archcpu(env
);
14642 uint32_t tb_flags
= dc
->base
.tb
->flags
;
14643 int bound
, core_mmu_idx
;
14645 dc
->isar
= &arm_cpu
->isar
;
14649 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
14650 * there is no secure EL1, so we route exceptions to EL3.
14652 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
14653 !arm_el_is_aa64(env
, 3);
14656 dc
->be_data
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, BE_DATA
) ? MO_BE
: MO_LE
;
14657 dc
->condexec_mask
= 0;
14658 dc
->condexec_cond
= 0;
14659 core_mmu_idx
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, MMUIDX
);
14660 dc
->mmu_idx
= core_to_aa64_mmu_idx(core_mmu_idx
);
14661 dc
->tbii
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TBII
);
14662 dc
->tbid
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TBID
);
14663 dc
->tcma
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TCMA
);
14664 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
14665 #if !defined(CONFIG_USER_ONLY)
14666 dc
->user
= (dc
->current_el
== 0);
14668 dc
->fp_excp_el
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, FPEXC_EL
);
14669 dc
->sve_excp_el
= FIELD_EX32(tb_flags
, TBFLAG_A64
, SVEEXC_EL
);
14670 dc
->sve_len
= (FIELD_EX32(tb_flags
, TBFLAG_A64
, ZCR_LEN
) + 1) * 16;
14671 dc
->pauth_active
= FIELD_EX32(tb_flags
, TBFLAG_A64
, PAUTH_ACTIVE
);
14672 dc
->bt
= FIELD_EX32(tb_flags
, TBFLAG_A64
, BT
);
14673 dc
->btype
= FIELD_EX32(tb_flags
, TBFLAG_A64
, BTYPE
);
14674 dc
->unpriv
= FIELD_EX32(tb_flags
, TBFLAG_A64
, UNPRIV
);
14675 dc
->ata
= FIELD_EX32(tb_flags
, TBFLAG_A64
, ATA
);
14676 dc
->mte_active
[0] = FIELD_EX32(tb_flags
, TBFLAG_A64
, MTE_ACTIVE
);
14677 dc
->mte_active
[1] = FIELD_EX32(tb_flags
, TBFLAG_A64
, MTE0_ACTIVE
);
14679 dc
->vec_stride
= 0;
14680 dc
->cp_regs
= arm_cpu
->cp_regs
;
14681 dc
->features
= env
->features
;
14682 dc
->dcz_blocksize
= arm_cpu
->dcz_blocksize
;
14684 #ifdef CONFIG_USER_ONLY
14685 /* In sve_probe_page, we assume TBI is enabled. */
14686 tcg_debug_assert(dc
->tbid
& 1);
14689 /* Single step state. The code-generation logic here is:
14691 * generate code with no special handling for single-stepping (except
14692 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
14693 * this happens anyway because those changes are all system register or
14695 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
14696 * emit code for one insn
14697 * emit code to clear PSTATE.SS
14698 * emit code to generate software step exception for completed step
14699 * end TB (as usual for having generated an exception)
14700 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
14701 * emit code to generate a software step exception
14704 dc
->ss_active
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, SS_ACTIVE
);
14705 dc
->pstate_ss
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, PSTATE_SS
);
14706 dc
->is_ldex
= false;
14707 dc
->debug_target_el
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, DEBUG_TARGET_EL
);
14709 /* Bound the number of insns to execute to those left on the page. */
14710 bound
= -(dc
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
14712 /* If architectural single step active, limit to 1. */
14713 if (dc
->ss_active
) {
14716 dc
->base
.max_insns
= MIN(dc
->base
.max_insns
, bound
);
14718 init_tmp_a64_array(dc
);
14721 static void aarch64_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
14725 static void aarch64_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
14727 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14729 tcg_gen_insn_start(dc
->base
.pc_next
, 0, 0);
14730 dc
->insn_start
= tcg_last_op();
14733 static bool aarch64_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cpu
,
14734 const CPUBreakpoint
*bp
)
14736 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14738 if (bp
->flags
& BP_CPU
) {
14739 gen_a64_set_pc_im(dc
->base
.pc_next
);
14740 gen_helper_check_breakpoints(cpu_env
);
14741 /* End the TB early; it likely won't be executed */
14742 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
14744 gen_exception_internal_insn(dc
, dc
->base
.pc_next
, EXCP_DEBUG
);
14745 /* The address covered by the breakpoint must be
14746 included in [tb->pc, tb->pc + tb->size) in order
14747 to for it to be properly cleared -- thus we
14748 increment the PC here so that the logic setting
14749 tb->size below does the right thing. */
14750 dc
->base
.pc_next
+= 4;
14751 dc
->base
.is_jmp
= DISAS_NORETURN
;
14757 static void aarch64_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
14759 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14760 CPUARMState
*env
= cpu
->env_ptr
;
14762 if (dc
->ss_active
&& !dc
->pstate_ss
) {
14763 /* Singlestep state is Active-pending.
14764 * If we're in this state at the start of a TB then either
14765 * a) we just took an exception to an EL which is being debugged
14766 * and this is the first insn in the exception handler
14767 * b) debug exceptions were masked and we just unmasked them
14768 * without changing EL (eg by clearing PSTATE.D)
14769 * In either case we're going to take a swstep exception in the
14770 * "did not step an insn" case, and so the syndrome ISV and EX
14771 * bits should be zero.
14773 assert(dc
->base
.num_insns
== 1);
14774 gen_swstep_exception(dc
, 0, 0);
14775 dc
->base
.is_jmp
= DISAS_NORETURN
;
14777 disas_a64_insn(env
, dc
);
14780 translator_loop_temp_check(&dc
->base
);
14783 static void aarch64_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
14785 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14787 if (unlikely(dc
->base
.singlestep_enabled
|| dc
->ss_active
)) {
14788 /* Note that this means single stepping WFI doesn't halt the CPU.
14789 * For conditional branch insns this is harmless unreachable code as
14790 * gen_goto_tb() has already handled emitting the debug exception
14791 * (and thus a tb-jump is not possible when singlestepping).
14793 switch (dc
->base
.is_jmp
) {
14795 gen_a64_set_pc_im(dc
->base
.pc_next
);
14799 if (dc
->base
.singlestep_enabled
) {
14800 gen_exception_internal(EXCP_DEBUG
);
14802 gen_step_complete_exception(dc
);
14805 case DISAS_NORETURN
:
14809 switch (dc
->base
.is_jmp
) {
14811 case DISAS_TOO_MANY
:
14812 gen_goto_tb(dc
, 1, dc
->base
.pc_next
);
14815 case DISAS_UPDATE_EXIT
:
14816 gen_a64_set_pc_im(dc
->base
.pc_next
);
14819 tcg_gen_exit_tb(NULL
, 0);
14821 case DISAS_UPDATE_NOCHAIN
:
14822 gen_a64_set_pc_im(dc
->base
.pc_next
);
14825 tcg_gen_lookup_and_goto_ptr();
14827 case DISAS_NORETURN
:
14831 gen_a64_set_pc_im(dc
->base
.pc_next
);
14832 gen_helper_wfe(cpu_env
);
14835 gen_a64_set_pc_im(dc
->base
.pc_next
);
14836 gen_helper_yield(cpu_env
);
14840 /* This is a special case because we don't want to just halt the CPU
14841 * if trying to debug across a WFI.
14843 TCGv_i32 tmp
= tcg_const_i32(4);
14845 gen_a64_set_pc_im(dc
->base
.pc_next
);
14846 gen_helper_wfi(cpu_env
, tmp
);
14847 tcg_temp_free_i32(tmp
);
14848 /* The helper doesn't necessarily throw an exception, but we
14849 * must go back to the main loop to check for interrupts anyway.
14851 tcg_gen_exit_tb(NULL
, 0);
14858 static void aarch64_tr_disas_log(const DisasContextBase
*dcbase
,
14861 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14863 qemu_log("IN: %s\n", lookup_symbol(dc
->base
.pc_first
));
14864 log_target_disas(cpu
, dc
->base
.pc_first
, dc
->base
.tb
->size
);
14867 const TranslatorOps aarch64_translator_ops
= {
14868 .init_disas_context
= aarch64_tr_init_disas_context
,
14869 .tb_start
= aarch64_tr_tb_start
,
14870 .insn_start
= aarch64_tr_insn_start
,
14871 .breakpoint_check
= aarch64_tr_breakpoint_check
,
14872 .translate_insn
= aarch64_tr_translate_insn
,
14873 .tb_stop
= aarch64_tr_tb_stop
,
14874 .disas_log
= aarch64_tr_disas_log
,