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apb: split simba PCI bridge into hw/pci-bridge/simba.c
[qemu/ar7.git] / target / mips / msa_helper.c
blob8fb7a369ca9d6884eff5e40de78260c77f3dd7e6
1 /*
2 * MIPS SIMD Architecture Module Instruction emulation helpers for QEMU.
3 *
4 * Copyright (c) 2014 Imagination Technologies
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "cpu.h"
22 #include "internal.h"
23 #include "exec/exec-all.h"
24 #include "exec/helper-proto.h"
25
26 /* Data format min and max values */
27 #define DF_BITS(df) (1 << ((df) + 3))
28
29 #define DF_MAX_INT(df) (int64_t)((1LL << (DF_BITS(df) - 1)) - 1)
30 #define M_MAX_INT(m) (int64_t)((1LL << ((m) - 1)) - 1)
31
32 #define DF_MIN_INT(df) (int64_t)(-(1LL << (DF_BITS(df) - 1)))
33 #define M_MIN_INT(m) (int64_t)(-(1LL << ((m) - 1)))
34
35 #define DF_MAX_UINT(df) (uint64_t)(-1ULL >> (64 - DF_BITS(df)))
36 #define M_MAX_UINT(m) (uint64_t)(-1ULL >> (64 - (m)))
37
38 #define UNSIGNED(x, df) ((x) & DF_MAX_UINT(df))
39 #define SIGNED(x, df) \
40 ((((int64_t)x) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df)))
41
42 /* Element-by-element access macros */
43 #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
44
45 static inline void msa_move_v(wr_t *pwd, wr_t *pws)
46 {
47 uint32_t i;
48
49 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
50 pwd->d[i] = pws->d[i];
51 }
52 }
53
54 #define MSA_FN_IMM8(FUNC, DEST, OPERATION) \
55 void helper_msa_ ## FUNC(CPUMIPSState *env, uint32_t wd, uint32_t ws, \
56 uint32_t i8) \
57 { \
58 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
59 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
60 uint32_t i; \
61 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
62 DEST = OPERATION; \
63 } \
64 }
65
66 MSA_FN_IMM8(andi_b, pwd->b[i], pws->b[i] & i8)
67 MSA_FN_IMM8(ori_b, pwd->b[i], pws->b[i] | i8)
68 MSA_FN_IMM8(nori_b, pwd->b[i], ~(pws->b[i] | i8))
69 MSA_FN_IMM8(xori_b, pwd->b[i], pws->b[i] ^ i8)
70
71 #define BIT_MOVE_IF_NOT_ZERO(dest, arg1, arg2, df) \
72 UNSIGNED(((dest & (~arg2)) | (arg1 & arg2)), df)
73 MSA_FN_IMM8(bmnzi_b, pwd->b[i],
74 BIT_MOVE_IF_NOT_ZERO(pwd->b[i], pws->b[i], i8, DF_BYTE))
75
76 #define BIT_MOVE_IF_ZERO(dest, arg1, arg2, df) \
77 UNSIGNED((dest & arg2) | (arg1 & (~arg2)), df)
78 MSA_FN_IMM8(bmzi_b, pwd->b[i],
79 BIT_MOVE_IF_ZERO(pwd->b[i], pws->b[i], i8, DF_BYTE))
80
81 #define BIT_SELECT(dest, arg1, arg2, df) \
82 UNSIGNED((arg1 & (~dest)) | (arg2 & dest), df)
83 MSA_FN_IMM8(bseli_b, pwd->b[i],
84 BIT_SELECT(pwd->b[i], pws->b[i], i8, DF_BYTE))
85
86 #undef MSA_FN_IMM8
87
88 #define SHF_POS(i, imm) (((i) & 0xfc) + (((imm) >> (2 * ((i) & 0x03))) & 0x03))
89
90 void helper_msa_shf_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
91 uint32_t ws, uint32_t imm)
92 {
93 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
94 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
95 wr_t wx, *pwx = &wx;
96 uint32_t i;
97
98 switch (df) {
99 case DF_BYTE:
100 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
101 pwx->b[i] = pws->b[SHF_POS(i, imm)];
102 }
103 break;
104 case DF_HALF:
105 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
106 pwx->h[i] = pws->h[SHF_POS(i, imm)];
107 }
108 break;
109 case DF_WORD:
110 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
111 pwx->w[i] = pws->w[SHF_POS(i, imm)];
112 }
113 break;
114 default:
115 assert(0);
116 }
117 msa_move_v(pwd, pwx);
118 }
119
120 #define MSA_FN_VECTOR(FUNC, DEST, OPERATION) \
121 void helper_msa_ ## FUNC(CPUMIPSState *env, uint32_t wd, uint32_t ws, \
122 uint32_t wt) \
123 { \
124 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
125 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
126 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
127 uint32_t i; \
128 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
129 DEST = OPERATION; \
130 } \
131 }
132
133 MSA_FN_VECTOR(and_v, pwd->d[i], pws->d[i] & pwt->d[i])
134 MSA_FN_VECTOR(or_v, pwd->d[i], pws->d[i] | pwt->d[i])
135 MSA_FN_VECTOR(nor_v, pwd->d[i], ~(pws->d[i] | pwt->d[i]))
136 MSA_FN_VECTOR(xor_v, pwd->d[i], pws->d[i] ^ pwt->d[i])
137 MSA_FN_VECTOR(bmnz_v, pwd->d[i],
138 BIT_MOVE_IF_NOT_ZERO(pwd->d[i], pws->d[i], pwt->d[i], DF_DOUBLE))
139 MSA_FN_VECTOR(bmz_v, pwd->d[i],
140 BIT_MOVE_IF_ZERO(pwd->d[i], pws->d[i], pwt->d[i], DF_DOUBLE))
141 MSA_FN_VECTOR(bsel_v, pwd->d[i],
142 BIT_SELECT(pwd->d[i], pws->d[i], pwt->d[i], DF_DOUBLE))
143 #undef BIT_MOVE_IF_NOT_ZERO
144 #undef BIT_MOVE_IF_ZERO
145 #undef BIT_SELECT
146 #undef MSA_FN_VECTOR
147
148 static inline int64_t msa_addv_df(uint32_t df, int64_t arg1, int64_t arg2)
149 {
150 return arg1 + arg2;
151 }
152
153 static inline int64_t msa_subv_df(uint32_t df, int64_t arg1, int64_t arg2)
154 {
155 return arg1 - arg2;
156 }
157
158 static inline int64_t msa_ceq_df(uint32_t df, int64_t arg1, int64_t arg2)
159 {
160 return arg1 == arg2 ? -1 : 0;
161 }
162
163 static inline int64_t msa_cle_s_df(uint32_t df, int64_t arg1, int64_t arg2)
164 {
165 return arg1 <= arg2 ? -1 : 0;
166 }
167
168 static inline int64_t msa_cle_u_df(uint32_t df, int64_t arg1, int64_t arg2)
169 {
170 uint64_t u_arg1 = UNSIGNED(arg1, df);
171 uint64_t u_arg2 = UNSIGNED(arg2, df);
172 return u_arg1 <= u_arg2 ? -1 : 0;
173 }
174
175 static inline int64_t msa_clt_s_df(uint32_t df, int64_t arg1, int64_t arg2)
176 {
177 return arg1 < arg2 ? -1 : 0;
178 }
179
180 static inline int64_t msa_clt_u_df(uint32_t df, int64_t arg1, int64_t arg2)
181 {
182 uint64_t u_arg1 = UNSIGNED(arg1, df);
183 uint64_t u_arg2 = UNSIGNED(arg2, df);
184 return u_arg1 < u_arg2 ? -1 : 0;
185 }
186
187 static inline int64_t msa_max_s_df(uint32_t df, int64_t arg1, int64_t arg2)
188 {
189 return arg1 > arg2 ? arg1 : arg2;
190 }
191
192 static inline int64_t msa_max_u_df(uint32_t df, int64_t arg1, int64_t arg2)
193 {
194 uint64_t u_arg1 = UNSIGNED(arg1, df);
195 uint64_t u_arg2 = UNSIGNED(arg2, df);
196 return u_arg1 > u_arg2 ? arg1 : arg2;
197 }
198
199 static inline int64_t msa_min_s_df(uint32_t df, int64_t arg1, int64_t arg2)
200 {
201 return arg1 < arg2 ? arg1 : arg2;
202 }
203
204 static inline int64_t msa_min_u_df(uint32_t df, int64_t arg1, int64_t arg2)
205 {
206 uint64_t u_arg1 = UNSIGNED(arg1, df);
207 uint64_t u_arg2 = UNSIGNED(arg2, df);
208 return u_arg1 < u_arg2 ? arg1 : arg2;
209 }
210
211 #define MSA_BINOP_IMM_DF(helper, func) \
212 void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, \
213 uint32_t wd, uint32_t ws, int32_t u5) \
214 { \
215 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
216 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
217 uint32_t i; \
218 \
219 switch (df) { \
220 case DF_BYTE: \
221 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
222 pwd->b[i] = msa_ ## func ## _df(df, pws->b[i], u5); \
223 } \
224 break; \
225 case DF_HALF: \
226 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
227 pwd->h[i] = msa_ ## func ## _df(df, pws->h[i], u5); \
228 } \
229 break; \
230 case DF_WORD: \
231 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
232 pwd->w[i] = msa_ ## func ## _df(df, pws->w[i], u5); \
233 } \
234 break; \
235 case DF_DOUBLE: \
236 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
237 pwd->d[i] = msa_ ## func ## _df(df, pws->d[i], u5); \
238 } \
239 break; \
240 default: \
241 assert(0); \
242 } \
243 }
244
245 MSA_BINOP_IMM_DF(addvi, addv)
246 MSA_BINOP_IMM_DF(subvi, subv)
247 MSA_BINOP_IMM_DF(ceqi, ceq)
248 MSA_BINOP_IMM_DF(clei_s, cle_s)
249 MSA_BINOP_IMM_DF(clei_u, cle_u)
250 MSA_BINOP_IMM_DF(clti_s, clt_s)
251 MSA_BINOP_IMM_DF(clti_u, clt_u)
252 MSA_BINOP_IMM_DF(maxi_s, max_s)
253 MSA_BINOP_IMM_DF(maxi_u, max_u)
254 MSA_BINOP_IMM_DF(mini_s, min_s)
255 MSA_BINOP_IMM_DF(mini_u, min_u)
256 #undef MSA_BINOP_IMM_DF
257
258 void helper_msa_ldi_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
259 int32_t s10)
260 {
261 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
262 uint32_t i;
263
264 switch (df) {
265 case DF_BYTE:
266 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
267 pwd->b[i] = (int8_t)s10;
268 }
269 break;
270 case DF_HALF:
271 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
272 pwd->h[i] = (int16_t)s10;
273 }
274 break;
275 case DF_WORD:
276 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
277 pwd->w[i] = (int32_t)s10;
278 }
279 break;
280 case DF_DOUBLE:
281 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
282 pwd->d[i] = (int64_t)s10;
283 }
284 break;
285 default:
286 assert(0);
287 }
288 }
289
290 /* Data format bit position and unsigned values */
291 #define BIT_POSITION(x, df) ((uint64_t)(x) % DF_BITS(df))
292
293 static inline int64_t msa_sll_df(uint32_t df, int64_t arg1, int64_t arg2)
294 {
295 int32_t b_arg2 = BIT_POSITION(arg2, df);
296 return arg1 << b_arg2;
297 }
298
299 static inline int64_t msa_sra_df(uint32_t df, int64_t arg1, int64_t arg2)
300 {
301 int32_t b_arg2 = BIT_POSITION(arg2, df);
302 return arg1 >> b_arg2;
303 }
304
305 static inline int64_t msa_srl_df(uint32_t df, int64_t arg1, int64_t arg2)
306 {
307 uint64_t u_arg1 = UNSIGNED(arg1, df);
308 int32_t b_arg2 = BIT_POSITION(arg2, df);
309 return u_arg1 >> b_arg2;
310 }
311
312 static inline int64_t msa_bclr_df(uint32_t df, int64_t arg1, int64_t arg2)
313 {
314 int32_t b_arg2 = BIT_POSITION(arg2, df);
315 return UNSIGNED(arg1 & (~(1LL << b_arg2)), df);
316 }
317
318 static inline int64_t msa_bset_df(uint32_t df, int64_t arg1,
319 int64_t arg2)
320 {
321 int32_t b_arg2 = BIT_POSITION(arg2, df);
322 return UNSIGNED(arg1 | (1LL << b_arg2), df);
323 }
324
325 static inline int64_t msa_bneg_df(uint32_t df, int64_t arg1, int64_t arg2)
326 {
327 int32_t b_arg2 = BIT_POSITION(arg2, df);
328 return UNSIGNED(arg1 ^ (1LL << b_arg2), df);
329 }
330
331 static inline int64_t msa_binsl_df(uint32_t df, int64_t dest, int64_t arg1,
332 int64_t arg2)
333 {
334 uint64_t u_arg1 = UNSIGNED(arg1, df);
335 uint64_t u_dest = UNSIGNED(dest, df);
336 int32_t sh_d = BIT_POSITION(arg2, df) + 1;
337 int32_t sh_a = DF_BITS(df) - sh_d;
338 if (sh_d == DF_BITS(df)) {
339 return u_arg1;
340 } else {
341 return UNSIGNED(UNSIGNED(u_dest << sh_d, df) >> sh_d, df) |
342 UNSIGNED(UNSIGNED(u_arg1 >> sh_a, df) << sh_a, df);
343 }
344 }
345
346 static inline int64_t msa_binsr_df(uint32_t df, int64_t dest, int64_t arg1,
347 int64_t arg2)
348 {
349 uint64_t u_arg1 = UNSIGNED(arg1, df);
350 uint64_t u_dest = UNSIGNED(dest, df);
351 int32_t sh_d = BIT_POSITION(arg2, df) + 1;
352 int32_t sh_a = DF_BITS(df) - sh_d;
353 if (sh_d == DF_BITS(df)) {
354 return u_arg1;
355 } else {
356 return UNSIGNED(UNSIGNED(u_dest >> sh_d, df) << sh_d, df) |
357 UNSIGNED(UNSIGNED(u_arg1 << sh_a, df) >> sh_a, df);
358 }
359 }
360
361 static inline int64_t msa_sat_s_df(uint32_t df, int64_t arg, uint32_t m)
362 {
363 return arg < M_MIN_INT(m+1) ? M_MIN_INT(m+1) :
364 arg > M_MAX_INT(m+1) ? M_MAX_INT(m+1) :
365 arg;
366 }
367
368 static inline int64_t msa_sat_u_df(uint32_t df, int64_t arg, uint32_t m)
369 {
370 uint64_t u_arg = UNSIGNED(arg, df);
371 return u_arg < M_MAX_UINT(m+1) ? u_arg :
372 M_MAX_UINT(m+1);
373 }
374
375 static inline int64_t msa_srar_df(uint32_t df, int64_t arg1, int64_t arg2)
376 {
377 int32_t b_arg2 = BIT_POSITION(arg2, df);
378 if (b_arg2 == 0) {
379 return arg1;
380 } else {
381 int64_t r_bit = (arg1 >> (b_arg2 - 1)) & 1;
382 return (arg1 >> b_arg2) + r_bit;
383 }
384 }
385
386 static inline int64_t msa_srlr_df(uint32_t df, int64_t arg1, int64_t arg2)
387 {
388 uint64_t u_arg1 = UNSIGNED(arg1, df);
389 int32_t b_arg2 = BIT_POSITION(arg2, df);
390 if (b_arg2 == 0) {
391 return u_arg1;
392 } else {
393 uint64_t r_bit = (u_arg1 >> (b_arg2 - 1)) & 1;
394 return (u_arg1 >> b_arg2) + r_bit;
395 }
396 }
397
398 #define MSA_BINOP_IMMU_DF(helper, func) \
399 void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, uint32_t wd, \
400 uint32_t ws, uint32_t u5) \
401 { \
402 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
403 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
404 uint32_t i; \
405 \
406 switch (df) { \
407 case DF_BYTE: \
408 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
409 pwd->b[i] = msa_ ## func ## _df(df, pws->b[i], u5); \
410 } \
411 break; \
412 case DF_HALF: \
413 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
414 pwd->h[i] = msa_ ## func ## _df(df, pws->h[i], u5); \
415 } \
416 break; \
417 case DF_WORD: \
418 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
419 pwd->w[i] = msa_ ## func ## _df(df, pws->w[i], u5); \
420 } \
421 break; \
422 case DF_DOUBLE: \
423 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
424 pwd->d[i] = msa_ ## func ## _df(df, pws->d[i], u5); \
425 } \
426 break; \
427 default: \
428 assert(0); \
429 } \
430 }
431
432 MSA_BINOP_IMMU_DF(slli, sll)
433 MSA_BINOP_IMMU_DF(srai, sra)
434 MSA_BINOP_IMMU_DF(srli, srl)
435 MSA_BINOP_IMMU_DF(bclri, bclr)
436 MSA_BINOP_IMMU_DF(bseti, bset)
437 MSA_BINOP_IMMU_DF(bnegi, bneg)
438 MSA_BINOP_IMMU_DF(sat_s, sat_s)
439 MSA_BINOP_IMMU_DF(sat_u, sat_u)
440 MSA_BINOP_IMMU_DF(srari, srar)
441 MSA_BINOP_IMMU_DF(srlri, srlr)
442 #undef MSA_BINOP_IMMU_DF
443
444 #define MSA_TEROP_IMMU_DF(helper, func) \
445 void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, \
446 uint32_t wd, uint32_t ws, uint32_t u5) \
447 { \
448 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
449 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
450 uint32_t i; \
451 \
452 switch (df) { \
453 case DF_BYTE: \
454 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
455 pwd->b[i] = msa_ ## func ## _df(df, pwd->b[i], pws->b[i], \
456 u5); \
457 } \
458 break; \
459 case DF_HALF: \
460 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
461 pwd->h[i] = msa_ ## func ## _df(df, pwd->h[i], pws->h[i], \
462 u5); \
463 } \
464 break; \
465 case DF_WORD: \
466 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
467 pwd->w[i] = msa_ ## func ## _df(df, pwd->w[i], pws->w[i], \
468 u5); \
469 } \
470 break; \
471 case DF_DOUBLE: \
472 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
473 pwd->d[i] = msa_ ## func ## _df(df, pwd->d[i], pws->d[i], \
474 u5); \
475 } \
476 break; \
477 default: \
478 assert(0); \
479 } \
480 }
481
482 MSA_TEROP_IMMU_DF(binsli, binsl)
483 MSA_TEROP_IMMU_DF(binsri, binsr)
484 #undef MSA_TEROP_IMMU_DF
485
486 static inline int64_t msa_max_a_df(uint32_t df, int64_t arg1, int64_t arg2)
487 {
488 uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
489 uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
490 return abs_arg1 > abs_arg2 ? arg1 : arg2;
491 }
492
493 static inline int64_t msa_min_a_df(uint32_t df, int64_t arg1, int64_t arg2)
494 {
495 uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
496 uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
497 return abs_arg1 < abs_arg2 ? arg1 : arg2;
498 }
499
500 static inline int64_t msa_add_a_df(uint32_t df, int64_t arg1, int64_t arg2)
501 {
502 uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
503 uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
504 return abs_arg1 + abs_arg2;
505 }
506
507 static inline int64_t msa_adds_a_df(uint32_t df, int64_t arg1, int64_t arg2)
508 {
509 uint64_t max_int = (uint64_t)DF_MAX_INT(df);
510 uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
511 uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
512 if (abs_arg1 > max_int || abs_arg2 > max_int) {
513 return (int64_t)max_int;
514 } else {
515 return (abs_arg1 < max_int - abs_arg2) ? abs_arg1 + abs_arg2 : max_int;
516 }
517 }
518
519 static inline int64_t msa_adds_s_df(uint32_t df, int64_t arg1, int64_t arg2)
520 {
521 int64_t max_int = DF_MAX_INT(df);
522 int64_t min_int = DF_MIN_INT(df);
523 if (arg1 < 0) {
524 return (min_int - arg1 < arg2) ? arg1 + arg2 : min_int;
525 } else {
526 return (arg2 < max_int - arg1) ? arg1 + arg2 : max_int;
527 }
528 }
529
530 static inline uint64_t msa_adds_u_df(uint32_t df, uint64_t arg1, uint64_t arg2)
531 {
532 uint64_t max_uint = DF_MAX_UINT(df);
533 uint64_t u_arg1 = UNSIGNED(arg1, df);
534 uint64_t u_arg2 = UNSIGNED(arg2, df);
535 return (u_arg1 < max_uint - u_arg2) ? u_arg1 + u_arg2 : max_uint;
536 }
537
538 static inline int64_t msa_ave_s_df(uint32_t df, int64_t arg1, int64_t arg2)
539 {
540 /* signed shift */
541 return (arg1 >> 1) + (arg2 >> 1) + (arg1 & arg2 & 1);
542 }
543
544 static inline uint64_t msa_ave_u_df(uint32_t df, uint64_t arg1, uint64_t arg2)
545 {
546 uint64_t u_arg1 = UNSIGNED(arg1, df);
547 uint64_t u_arg2 = UNSIGNED(arg2, df);
548 /* unsigned shift */
549 return (u_arg1 >> 1) + (u_arg2 >> 1) + (u_arg1 & u_arg2 & 1);
550 }
551
552 static inline int64_t msa_aver_s_df(uint32_t df, int64_t arg1, int64_t arg2)
553 {
554 /* signed shift */
555 return (arg1 >> 1) + (arg2 >> 1) + ((arg1 | arg2) & 1);
556 }
557
558 static inline uint64_t msa_aver_u_df(uint32_t df, uint64_t arg1, uint64_t arg2)
559 {
560 uint64_t u_arg1 = UNSIGNED(arg1, df);
561 uint64_t u_arg2 = UNSIGNED(arg2, df);
562 /* unsigned shift */
563 return (u_arg1 >> 1) + (u_arg2 >> 1) + ((u_arg1 | u_arg2) & 1);
564 }
565
566 static inline int64_t msa_subs_s_df(uint32_t df, int64_t arg1, int64_t arg2)
567 {
568 int64_t max_int = DF_MAX_INT(df);
569 int64_t min_int = DF_MIN_INT(df);
570 if (arg2 > 0) {
571 return (min_int + arg2 < arg1) ? arg1 - arg2 : min_int;
572 } else {
573 return (arg1 < max_int + arg2) ? arg1 - arg2 : max_int;
574 }
575 }
576
577 static inline int64_t msa_subs_u_df(uint32_t df, int64_t arg1, int64_t arg2)
578 {
579 uint64_t u_arg1 = UNSIGNED(arg1, df);
580 uint64_t u_arg2 = UNSIGNED(arg2, df);
581 return (u_arg1 > u_arg2) ? u_arg1 - u_arg2 : 0;
582 }
583
584 static inline int64_t msa_subsus_u_df(uint32_t df, int64_t arg1, int64_t arg2)
585 {
586 uint64_t u_arg1 = UNSIGNED(arg1, df);
587 uint64_t max_uint = DF_MAX_UINT(df);
588 if (arg2 >= 0) {
589 uint64_t u_arg2 = (uint64_t)arg2;
590 return (u_arg1 > u_arg2) ?
591 (int64_t)(u_arg1 - u_arg2) :
592 0;
593 } else {
594 uint64_t u_arg2 = (uint64_t)(-arg2);
595 return (u_arg1 < max_uint - u_arg2) ?
596 (int64_t)(u_arg1 + u_arg2) :
597 (int64_t)max_uint;
598 }
599 }
600
601 static inline int64_t msa_subsuu_s_df(uint32_t df, int64_t arg1, int64_t arg2)
602 {
603 uint64_t u_arg1 = UNSIGNED(arg1, df);
604 uint64_t u_arg2 = UNSIGNED(arg2, df);
605 int64_t max_int = DF_MAX_INT(df);
606 int64_t min_int = DF_MIN_INT(df);
607 if (u_arg1 > u_arg2) {
608 return u_arg1 - u_arg2 < (uint64_t)max_int ?
609 (int64_t)(u_arg1 - u_arg2) :
610 max_int;
611 } else {
612 return u_arg2 - u_arg1 < (uint64_t)(-min_int) ?
613 (int64_t)(u_arg1 - u_arg2) :
614 min_int;
615 }
616 }
617
618 static inline int64_t msa_asub_s_df(uint32_t df, int64_t arg1, int64_t arg2)
619 {
620 /* signed compare */
621 return (arg1 < arg2) ?
622 (uint64_t)(arg2 - arg1) : (uint64_t)(arg1 - arg2);
623 }
624
625 static inline uint64_t msa_asub_u_df(uint32_t df, uint64_t arg1, uint64_t arg2)
626 {
627 uint64_t u_arg1 = UNSIGNED(arg1, df);
628 uint64_t u_arg2 = UNSIGNED(arg2, df);
629 /* unsigned compare */
630 return (u_arg1 < u_arg2) ?
631 (uint64_t)(u_arg2 - u_arg1) : (uint64_t)(u_arg1 - u_arg2);
632 }
633
634 static inline int64_t msa_mulv_df(uint32_t df, int64_t arg1, int64_t arg2)
635 {
636 return arg1 * arg2;
637 }
638
639 static inline int64_t msa_div_s_df(uint32_t df, int64_t arg1, int64_t arg2)
640 {
641 if (arg1 == DF_MIN_INT(df) && arg2 == -1) {
642 return DF_MIN_INT(df);
643 }
644 return arg2 ? arg1 / arg2 : 0;
645 }
646
647 static inline int64_t msa_div_u_df(uint32_t df, int64_t arg1, int64_t arg2)
648 {
649 uint64_t u_arg1 = UNSIGNED(arg1, df);
650 uint64_t u_arg2 = UNSIGNED(arg2, df);
651 return u_arg2 ? u_arg1 / u_arg2 : 0;
652 }
653
654 static inline int64_t msa_mod_s_df(uint32_t df, int64_t arg1, int64_t arg2)
655 {
656 if (arg1 == DF_MIN_INT(df) && arg2 == -1) {
657 return 0;
658 }
659 return arg2 ? arg1 % arg2 : 0;
660 }
661
662 static inline int64_t msa_mod_u_df(uint32_t df, int64_t arg1, int64_t arg2)
663 {
664 uint64_t u_arg1 = UNSIGNED(arg1, df);
665 uint64_t u_arg2 = UNSIGNED(arg2, df);
666 return u_arg2 ? u_arg1 % u_arg2 : 0;
667 }
668
669 #define SIGNED_EVEN(a, df) \
670 ((((int64_t)(a)) << (64 - DF_BITS(df)/2)) >> (64 - DF_BITS(df)/2))
671
672 #define UNSIGNED_EVEN(a, df) \
673 ((((uint64_t)(a)) << (64 - DF_BITS(df)/2)) >> (64 - DF_BITS(df)/2))
674
675 #define SIGNED_ODD(a, df) \
676 ((((int64_t)(a)) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df)/2))
677
678 #define UNSIGNED_ODD(a, df) \
679 ((((uint64_t)(a)) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df)/2))
680
681 #define SIGNED_EXTRACT(e, o, a, df) \
682 do { \
683 e = SIGNED_EVEN(a, df); \
684 o = SIGNED_ODD(a, df); \
685 } while (0)
686
687 #define UNSIGNED_EXTRACT(e, o, a, df) \
688 do { \
689 e = UNSIGNED_EVEN(a, df); \
690 o = UNSIGNED_ODD(a, df); \
691 } while (0)
692
693 static inline int64_t msa_dotp_s_df(uint32_t df, int64_t arg1, int64_t arg2)
694 {
695 int64_t even_arg1;
696 int64_t even_arg2;
697 int64_t odd_arg1;
698 int64_t odd_arg2;
699 SIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
700 SIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
701 return (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
702 }
703
704 static inline int64_t msa_dotp_u_df(uint32_t df, int64_t arg1, int64_t arg2)
705 {
706 int64_t even_arg1;
707 int64_t even_arg2;
708 int64_t odd_arg1;
709 int64_t odd_arg2;
710 UNSIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
711 UNSIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
712 return (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
713 }
714
715 #define CONCATENATE_AND_SLIDE(s, k) \
716 do { \
717 for (i = 0; i < s; i++) { \
718 v[i] = pws->b[s * k + i]; \
719 v[i + s] = pwd->b[s * k + i]; \
720 } \
721 for (i = 0; i < s; i++) { \
722 pwd->b[s * k + i] = v[i + n]; \
723 } \
724 } while (0)
725
726 static inline void msa_sld_df(uint32_t df, wr_t *pwd,
727 wr_t *pws, target_ulong rt)
728 {
729 uint32_t n = rt % DF_ELEMENTS(df);
730 uint8_t v[64];
731 uint32_t i, k;
732
733 switch (df) {
734 case DF_BYTE:
735 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_BYTE), 0);
736 break;
737 case DF_HALF:
738 for (k = 0; k < 2; k++) {
739 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_HALF), k);
740 }
741 break;
742 case DF_WORD:
743 for (k = 0; k < 4; k++) {
744 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_WORD), k);
745 }
746 break;
747 case DF_DOUBLE:
748 for (k = 0; k < 8; k++) {
749 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_DOUBLE), k);
750 }
751 break;
752 default:
753 assert(0);
754 }
755 }
756
757 static inline int64_t msa_hadd_s_df(uint32_t df, int64_t arg1, int64_t arg2)
758 {
759 return SIGNED_ODD(arg1, df) + SIGNED_EVEN(arg2, df);
760 }
761
762 static inline int64_t msa_hadd_u_df(uint32_t df, int64_t arg1, int64_t arg2)
763 {
764 return UNSIGNED_ODD(arg1, df) + UNSIGNED_EVEN(arg2, df);
765 }
766
767 static inline int64_t msa_hsub_s_df(uint32_t df, int64_t arg1, int64_t arg2)
768 {
769 return SIGNED_ODD(arg1, df) - SIGNED_EVEN(arg2, df);
770 }
771
772 static inline int64_t msa_hsub_u_df(uint32_t df, int64_t arg1, int64_t arg2)
773 {
774 return UNSIGNED_ODD(arg1, df) - UNSIGNED_EVEN(arg2, df);
775 }
776
777 static inline int64_t msa_mul_q_df(uint32_t df, int64_t arg1, int64_t arg2)
778 {
779 int64_t q_min = DF_MIN_INT(df);
780 int64_t q_max = DF_MAX_INT(df);
781
782 if (arg1 == q_min && arg2 == q_min) {
783 return q_max;
784 }
785 return (arg1 * arg2) >> (DF_BITS(df) - 1);
786 }
787
788 static inline int64_t msa_mulr_q_df(uint32_t df, int64_t arg1, int64_t arg2)
789 {
790 int64_t q_min = DF_MIN_INT(df);
791 int64_t q_max = DF_MAX_INT(df);
792 int64_t r_bit = 1 << (DF_BITS(df) - 2);
793
794 if (arg1 == q_min && arg2 == q_min) {
795 return q_max;
796 }
797 return (arg1 * arg2 + r_bit) >> (DF_BITS(df) - 1);
798 }
799
800 #define MSA_BINOP_DF(func) \
801 void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, \
802 uint32_t wd, uint32_t ws, uint32_t wt) \
803 { \
804 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
805 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
806 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
807 uint32_t i; \
808 \
809 switch (df) { \
810 case DF_BYTE: \
811 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
812 pwd->b[i] = msa_ ## func ## _df(df, pws->b[i], pwt->b[i]); \
813 } \
814 break; \
815 case DF_HALF: \
816 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
817 pwd->h[i] = msa_ ## func ## _df(df, pws->h[i], pwt->h[i]); \
818 } \
819 break; \
820 case DF_WORD: \
821 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
822 pwd->w[i] = msa_ ## func ## _df(df, pws->w[i], pwt->w[i]); \
823 } \
824 break; \
825 case DF_DOUBLE: \
826 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
827 pwd->d[i] = msa_ ## func ## _df(df, pws->d[i], pwt->d[i]); \
828 } \
829 break; \
830 default: \
831 assert(0); \
832 } \
833 }
834
835 MSA_BINOP_DF(sll)
836 MSA_BINOP_DF(sra)
837 MSA_BINOP_DF(srl)
838 MSA_BINOP_DF(bclr)
839 MSA_BINOP_DF(bset)
840 MSA_BINOP_DF(bneg)
841 MSA_BINOP_DF(addv)
842 MSA_BINOP_DF(subv)
843 MSA_BINOP_DF(max_s)
844 MSA_BINOP_DF(max_u)
845 MSA_BINOP_DF(min_s)
846 MSA_BINOP_DF(min_u)
847 MSA_BINOP_DF(max_a)
848 MSA_BINOP_DF(min_a)
849 MSA_BINOP_DF(ceq)
850 MSA_BINOP_DF(clt_s)
851 MSA_BINOP_DF(clt_u)
852 MSA_BINOP_DF(cle_s)
853 MSA_BINOP_DF(cle_u)
854 MSA_BINOP_DF(add_a)
855 MSA_BINOP_DF(adds_a)
856 MSA_BINOP_DF(adds_s)
857 MSA_BINOP_DF(adds_u)
858 MSA_BINOP_DF(ave_s)
859 MSA_BINOP_DF(ave_u)
860 MSA_BINOP_DF(aver_s)
861 MSA_BINOP_DF(aver_u)
862 MSA_BINOP_DF(subs_s)
863 MSA_BINOP_DF(subs_u)
864 MSA_BINOP_DF(subsus_u)
865 MSA_BINOP_DF(subsuu_s)
866 MSA_BINOP_DF(asub_s)
867 MSA_BINOP_DF(asub_u)
868 MSA_BINOP_DF(mulv)
869 MSA_BINOP_DF(div_s)
870 MSA_BINOP_DF(div_u)
871 MSA_BINOP_DF(mod_s)
872 MSA_BINOP_DF(mod_u)
873 MSA_BINOP_DF(dotp_s)
874 MSA_BINOP_DF(dotp_u)
875 MSA_BINOP_DF(srar)
876 MSA_BINOP_DF(srlr)
877 MSA_BINOP_DF(hadd_s)
878 MSA_BINOP_DF(hadd_u)
879 MSA_BINOP_DF(hsub_s)
880 MSA_BINOP_DF(hsub_u)
881
882 MSA_BINOP_DF(mul_q)
883 MSA_BINOP_DF(mulr_q)
884 #undef MSA_BINOP_DF
885
886 void helper_msa_sld_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
887 uint32_t ws, uint32_t rt)
888 {
889 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
890 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
891
892 msa_sld_df(df, pwd, pws, env->active_tc.gpr[rt]);
893 }
894
895 static inline int64_t msa_maddv_df(uint32_t df, int64_t dest, int64_t arg1,
896 int64_t arg2)
897 {
898 return dest + arg1 * arg2;
899 }
900
901 static inline int64_t msa_msubv_df(uint32_t df, int64_t dest, int64_t arg1,
902 int64_t arg2)
903 {
904 return dest - arg1 * arg2;
905 }
906
907 static inline int64_t msa_dpadd_s_df(uint32_t df, int64_t dest, int64_t arg1,
908 int64_t arg2)
909 {
910 int64_t even_arg1;
911 int64_t even_arg2;
912 int64_t odd_arg1;
913 int64_t odd_arg2;
914 SIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
915 SIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
916 return dest + (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
917 }
918
919 static inline int64_t msa_dpadd_u_df(uint32_t df, int64_t dest, int64_t arg1,
920 int64_t arg2)
921 {
922 int64_t even_arg1;
923 int64_t even_arg2;
924 int64_t odd_arg1;
925 int64_t odd_arg2;
926 UNSIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
927 UNSIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
928 return dest + (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
929 }
930
931 static inline int64_t msa_dpsub_s_df(uint32_t df, int64_t dest, int64_t arg1,
932 int64_t arg2)
933 {
934 int64_t even_arg1;
935 int64_t even_arg2;
936 int64_t odd_arg1;
937 int64_t odd_arg2;
938 SIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
939 SIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
940 return dest - ((even_arg1 * even_arg2) + (odd_arg1 * odd_arg2));
941 }
942
943 static inline int64_t msa_dpsub_u_df(uint32_t df, int64_t dest, int64_t arg1,
944 int64_t arg2)
945 {
946 int64_t even_arg1;
947 int64_t even_arg2;
948 int64_t odd_arg1;
949 int64_t odd_arg2;
950 UNSIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
951 UNSIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
952 return dest - ((even_arg1 * even_arg2) + (odd_arg1 * odd_arg2));
953 }
954
955 static inline int64_t msa_madd_q_df(uint32_t df, int64_t dest, int64_t arg1,
956 int64_t arg2)
957 {
958 int64_t q_prod, q_ret;
959
960 int64_t q_max = DF_MAX_INT(df);
961 int64_t q_min = DF_MIN_INT(df);
962
963 q_prod = arg1 * arg2;
964 q_ret = ((dest << (DF_BITS(df) - 1)) + q_prod) >> (DF_BITS(df) - 1);
965
966 return (q_ret < q_min) ? q_min : (q_max < q_ret) ? q_max : q_ret;
967 }
968
969 static inline int64_t msa_msub_q_df(uint32_t df, int64_t dest, int64_t arg1,
970 int64_t arg2)
971 {
972 int64_t q_prod, q_ret;
973
974 int64_t q_max = DF_MAX_INT(df);
975 int64_t q_min = DF_MIN_INT(df);
976
977 q_prod = arg1 * arg2;
978 q_ret = ((dest << (DF_BITS(df) - 1)) - q_prod) >> (DF_BITS(df) - 1);
979
980 return (q_ret < q_min) ? q_min : (q_max < q_ret) ? q_max : q_ret;
981 }
982
983 static inline int64_t msa_maddr_q_df(uint32_t df, int64_t dest, int64_t arg1,
984 int64_t arg2)
985 {
986 int64_t q_prod, q_ret;
987
988 int64_t q_max = DF_MAX_INT(df);
989 int64_t q_min = DF_MIN_INT(df);
990 int64_t r_bit = 1 << (DF_BITS(df) - 2);
991
992 q_prod = arg1 * arg2;
993 q_ret = ((dest << (DF_BITS(df) - 1)) + q_prod + r_bit) >> (DF_BITS(df) - 1);
994
995 return (q_ret < q_min) ? q_min : (q_max < q_ret) ? q_max : q_ret;
996 }
997
998 static inline int64_t msa_msubr_q_df(uint32_t df, int64_t dest, int64_t arg1,
999 int64_t arg2)
1000 {
1001 int64_t q_prod, q_ret;
1002
1003 int64_t q_max = DF_MAX_INT(df);
1004 int64_t q_min = DF_MIN_INT(df);
1005 int64_t r_bit = 1 << (DF_BITS(df) - 2);
1006
1007 q_prod = arg1 * arg2;
1008 q_ret = ((dest << (DF_BITS(df) - 1)) - q_prod + r_bit) >> (DF_BITS(df) - 1);
1009
1010 return (q_ret < q_min) ? q_min : (q_max < q_ret) ? q_max : q_ret;
1011 }
1012
1013 #define MSA_TEROP_DF(func) \
1014 void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, uint32_t wd, \
1015 uint32_t ws, uint32_t wt) \
1016 { \
1017 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
1018 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
1019 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
1020 uint32_t i; \
1021 \
1022 switch (df) { \
1023 case DF_BYTE: \
1024 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
1025 pwd->b[i] = msa_ ## func ## _df(df, pwd->b[i], pws->b[i], \
1026 pwt->b[i]); \
1027 } \
1028 break; \
1029 case DF_HALF: \
1030 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
1031 pwd->h[i] = msa_ ## func ## _df(df, pwd->h[i], pws->h[i], \
1032 pwt->h[i]); \
1033 } \
1034 break; \
1035 case DF_WORD: \
1036 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
1037 pwd->w[i] = msa_ ## func ## _df(df, pwd->w[i], pws->w[i], \
1038 pwt->w[i]); \
1039 } \
1040 break; \
1041 case DF_DOUBLE: \
1042 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
1043 pwd->d[i] = msa_ ## func ## _df(df, pwd->d[i], pws->d[i], \
1044 pwt->d[i]); \
1045 } \
1046 break; \
1047 default: \
1048 assert(0); \
1049 } \
1050 }
1051
1052 MSA_TEROP_DF(maddv)
1053 MSA_TEROP_DF(msubv)
1054 MSA_TEROP_DF(dpadd_s)
1055 MSA_TEROP_DF(dpadd_u)
1056 MSA_TEROP_DF(dpsub_s)
1057 MSA_TEROP_DF(dpsub_u)
1058 MSA_TEROP_DF(binsl)
1059 MSA_TEROP_DF(binsr)
1060 MSA_TEROP_DF(madd_q)
1061 MSA_TEROP_DF(msub_q)
1062 MSA_TEROP_DF(maddr_q)
1063 MSA_TEROP_DF(msubr_q)
1064 #undef MSA_TEROP_DF
1065
1066 static inline void msa_splat_df(uint32_t df, wr_t *pwd,
1067 wr_t *pws, target_ulong rt)
1068 {
1069 uint32_t n = rt % DF_ELEMENTS(df);
1070 uint32_t i;
1071
1072 switch (df) {
1073 case DF_BYTE:
1074 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
1075 pwd->b[i] = pws->b[n];
1076 }
1077 break;
1078 case DF_HALF:
1079 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
1080 pwd->h[i] = pws->h[n];
1081 }
1082 break;
1083 case DF_WORD:
1084 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1085 pwd->w[i] = pws->w[n];
1086 }
1087 break;
1088 case DF_DOUBLE:
1089 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1090 pwd->d[i] = pws->d[n];
1091 }
1092 break;
1093 default:
1094 assert(0);
1095 }
1096 }
1097
1098 void helper_msa_splat_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1099 uint32_t ws, uint32_t rt)
1100 {
1101 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1102 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1103
1104 msa_splat_df(df, pwd, pws, env->active_tc.gpr[rt]);
1105 }
1106
1107 #define MSA_DO_B MSA_DO(b)
1108 #define MSA_DO_H MSA_DO(h)
1109 #define MSA_DO_W MSA_DO(w)
1110 #define MSA_DO_D MSA_DO(d)
1111
1112 #define MSA_LOOP_B MSA_LOOP(B)
1113 #define MSA_LOOP_H MSA_LOOP(H)
1114 #define MSA_LOOP_W MSA_LOOP(W)
1115 #define MSA_LOOP_D MSA_LOOP(D)
1116
1117 #define MSA_LOOP_COND_B MSA_LOOP_COND(DF_BYTE)
1118 #define MSA_LOOP_COND_H MSA_LOOP_COND(DF_HALF)
1119 #define MSA_LOOP_COND_W MSA_LOOP_COND(DF_WORD)
1120 #define MSA_LOOP_COND_D MSA_LOOP_COND(DF_DOUBLE)
1121
1122 #define MSA_LOOP(DF) \
1123 do { \
1124 for (i = 0; i < (MSA_LOOP_COND_ ## DF) ; i++) { \
1125 MSA_DO_ ## DF; \
1126 } \
1127 } while (0)
1128
1129 #define MSA_FN_DF(FUNC) \
1130 void helper_msa_##FUNC(CPUMIPSState *env, uint32_t df, uint32_t wd, \
1131 uint32_t ws, uint32_t wt) \
1132 { \
1133 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
1134 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
1135 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
1136 wr_t wx, *pwx = &wx; \
1137 uint32_t i; \
1138 switch (df) { \
1139 case DF_BYTE: \
1140 MSA_LOOP_B; \
1141 break; \
1142 case DF_HALF: \
1143 MSA_LOOP_H; \
1144 break; \
1145 case DF_WORD: \
1146 MSA_LOOP_W; \
1147 break; \
1148 case DF_DOUBLE: \
1149 MSA_LOOP_D; \
1150 break; \
1151 default: \
1152 assert(0); \
1153 } \
1154 msa_move_v(pwd, pwx); \
1155 }
1156
1157 #define MSA_LOOP_COND(DF) \
1158 (DF_ELEMENTS(DF) / 2)
1159
1160 #define Rb(pwr, i) (pwr->b[i])
1161 #define Lb(pwr, i) (pwr->b[i + DF_ELEMENTS(DF_BYTE)/2])
1162 #define Rh(pwr, i) (pwr->h[i])
1163 #define Lh(pwr, i) (pwr->h[i + DF_ELEMENTS(DF_HALF)/2])
1164 #define Rw(pwr, i) (pwr->w[i])
1165 #define Lw(pwr, i) (pwr->w[i + DF_ELEMENTS(DF_WORD)/2])
1166 #define Rd(pwr, i) (pwr->d[i])
1167 #define Ld(pwr, i) (pwr->d[i + DF_ELEMENTS(DF_DOUBLE)/2])
1168
1169 #define MSA_DO(DF) \
1170 do { \
1171 R##DF(pwx, i) = pwt->DF[2*i]; \
1172 L##DF(pwx, i) = pws->DF[2*i]; \
1173 } while (0)
1174 MSA_FN_DF(pckev_df)
1175 #undef MSA_DO
1176
1177 #define MSA_DO(DF) \
1178 do { \
1179 R##DF(pwx, i) = pwt->DF[2*i+1]; \
1180 L##DF(pwx, i) = pws->DF[2*i+1]; \
1181 } while (0)
1182 MSA_FN_DF(pckod_df)
1183 #undef MSA_DO
1184
1185 #define MSA_DO(DF) \
1186 do { \
1187 pwx->DF[2*i] = L##DF(pwt, i); \
1188 pwx->DF[2*i+1] = L##DF(pws, i); \
1189 } while (0)
1190 MSA_FN_DF(ilvl_df)
1191 #undef MSA_DO
1192
1193 #define MSA_DO(DF) \
1194 do { \
1195 pwx->DF[2*i] = R##DF(pwt, i); \
1196 pwx->DF[2*i+1] = R##DF(pws, i); \
1197 } while (0)
1198 MSA_FN_DF(ilvr_df)
1199 #undef MSA_DO
1200
1201 #define MSA_DO(DF) \
1202 do { \
1203 pwx->DF[2*i] = pwt->DF[2*i]; \
1204 pwx->DF[2*i+1] = pws->DF[2*i]; \
1205 } while (0)
1206 MSA_FN_DF(ilvev_df)
1207 #undef MSA_DO
1208
1209 #define MSA_DO(DF) \
1210 do { \
1211 pwx->DF[2*i] = pwt->DF[2*i+1]; \
1212 pwx->DF[2*i+1] = pws->DF[2*i+1]; \
1213 } while (0)
1214 MSA_FN_DF(ilvod_df)
1215 #undef MSA_DO
1216 #undef MSA_LOOP_COND
1217
1218 #define MSA_LOOP_COND(DF) \
1219 (DF_ELEMENTS(DF))
1220
1221 #define MSA_DO(DF) \
1222 do { \
1223 uint32_t n = DF_ELEMENTS(df); \
1224 uint32_t k = (pwd->DF[i] & 0x3f) % (2 * n); \
1225 pwx->DF[i] = \
1226 (pwd->DF[i] & 0xc0) ? 0 : k < n ? pwt->DF[k] : pws->DF[k - n]; \
1227 } while (0)
1228 MSA_FN_DF(vshf_df)
1229 #undef MSA_DO
1230 #undef MSA_LOOP_COND
1231 #undef MSA_FN_DF
1232
1233 void helper_msa_sldi_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1234 uint32_t ws, uint32_t n)
1235 {
1236 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1237 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1238
1239 msa_sld_df(df, pwd, pws, n);
1240 }
1241
1242 void helper_msa_splati_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1243 uint32_t ws, uint32_t n)
1244 {
1245 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1246 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1247
1248 msa_splat_df(df, pwd, pws, n);
1249 }
1250
1251 void helper_msa_copy_s_df(CPUMIPSState *env, uint32_t df, uint32_t rd,
1252 uint32_t ws, uint32_t n)
1253 {
1254 n %= DF_ELEMENTS(df);
1255
1256 switch (df) {
1257 case DF_BYTE:
1258 env->active_tc.gpr[rd] = (int8_t)env->active_fpu.fpr[ws].wr.b[n];
1259 break;
1260 case DF_HALF:
1261 env->active_tc.gpr[rd] = (int16_t)env->active_fpu.fpr[ws].wr.h[n];
1262 break;
1263 case DF_WORD:
1264 env->active_tc.gpr[rd] = (int32_t)env->active_fpu.fpr[ws].wr.w[n];
1265 break;
1266 #ifdef TARGET_MIPS64
1267 case DF_DOUBLE:
1268 env->active_tc.gpr[rd] = (int64_t)env->active_fpu.fpr[ws].wr.d[n];
1269 break;
1270 #endif
1271 default:
1272 assert(0);
1273 }
1274 }
1275
1276 void helper_msa_copy_u_df(CPUMIPSState *env, uint32_t df, uint32_t rd,
1277 uint32_t ws, uint32_t n)
1278 {
1279 n %= DF_ELEMENTS(df);
1280
1281 switch (df) {
1282 case DF_BYTE:
1283 env->active_tc.gpr[rd] = (uint8_t)env->active_fpu.fpr[ws].wr.b[n];
1284 break;
1285 case DF_HALF:
1286 env->active_tc.gpr[rd] = (uint16_t)env->active_fpu.fpr[ws].wr.h[n];
1287 break;
1288 case DF_WORD:
1289 env->active_tc.gpr[rd] = (uint32_t)env->active_fpu.fpr[ws].wr.w[n];
1290 break;
1291 #ifdef TARGET_MIPS64
1292 case DF_DOUBLE:
1293 env->active_tc.gpr[rd] = (uint64_t)env->active_fpu.fpr[ws].wr.d[n];
1294 break;
1295 #endif
1296 default:
1297 assert(0);
1298 }
1299 }
1300
1301 void helper_msa_insert_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1302 uint32_t rs_num, uint32_t n)
1303 {
1304 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1305 target_ulong rs = env->active_tc.gpr[rs_num];
1306
1307 switch (df) {
1308 case DF_BYTE:
1309 pwd->b[n] = (int8_t)rs;
1310 break;
1311 case DF_HALF:
1312 pwd->h[n] = (int16_t)rs;
1313 break;
1314 case DF_WORD:
1315 pwd->w[n] = (int32_t)rs;
1316 break;
1317 case DF_DOUBLE:
1318 pwd->d[n] = (int64_t)rs;
1319 break;
1320 default:
1321 assert(0);
1322 }
1323 }
1324
1325 void helper_msa_insve_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1326 uint32_t ws, uint32_t n)
1327 {
1328 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1329 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1330
1331 switch (df) {
1332 case DF_BYTE:
1333 pwd->b[n] = (int8_t)pws->b[0];
1334 break;
1335 case DF_HALF:
1336 pwd->h[n] = (int16_t)pws->h[0];
1337 break;
1338 case DF_WORD:
1339 pwd->w[n] = (int32_t)pws->w[0];
1340 break;
1341 case DF_DOUBLE:
1342 pwd->d[n] = (int64_t)pws->d[0];
1343 break;
1344 default:
1345 assert(0);
1346 }
1347 }
1348
1349 void helper_msa_ctcmsa(CPUMIPSState *env, target_ulong elm, uint32_t cd)
1350 {
1351 switch (cd) {
1352 case 0:
1353 break;
1354 case 1:
1355 env->active_tc.msacsr = (int32_t)elm & MSACSR_MASK;
1356 restore_msa_fp_status(env);
1357 /* check exception */
1358 if ((GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED)
1359 & GET_FP_CAUSE(env->active_tc.msacsr)) {
1360 do_raise_exception(env, EXCP_MSAFPE, GETPC());
1361 }
1362 break;
1363 }
1364 }
1365
1366 target_ulong helper_msa_cfcmsa(CPUMIPSState *env, uint32_t cs)
1367 {
1368 switch (cs) {
1369 case 0:
1370 return env->msair;
1371 case 1:
1372 return env->active_tc.msacsr & MSACSR_MASK;
1373 }
1374 return 0;
1375 }
1376
1377 void helper_msa_move_v(CPUMIPSState *env, uint32_t wd, uint32_t ws)
1378 {
1379 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1380 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1381
1382 msa_move_v(pwd, pws);
1383 }
1384
1385 static inline int64_t msa_pcnt_df(uint32_t df, int64_t arg)
1386 {
1387 uint64_t x;
1388
1389 x = UNSIGNED(arg, df);
1390
1391 x = (x & 0x5555555555555555ULL) + ((x >> 1) & 0x5555555555555555ULL);
1392 x = (x & 0x3333333333333333ULL) + ((x >> 2) & 0x3333333333333333ULL);
1393 x = (x & 0x0F0F0F0F0F0F0F0FULL) + ((x >> 4) & 0x0F0F0F0F0F0F0F0FULL);
1394 x = (x & 0x00FF00FF00FF00FFULL) + ((x >> 8) & 0x00FF00FF00FF00FFULL);
1395 x = (x & 0x0000FFFF0000FFFFULL) + ((x >> 16) & 0x0000FFFF0000FFFFULL);
1396 x = (x & 0x00000000FFFFFFFFULL) + ((x >> 32));
1397
1398 return x;
1399 }
1400
1401 static inline int64_t msa_nlzc_df(uint32_t df, int64_t arg)
1402 {
1403 uint64_t x, y;
1404 int n, c;
1405
1406 x = UNSIGNED(arg, df);
1407 n = DF_BITS(df);
1408 c = DF_BITS(df) / 2;
1409
1410 do {
1411 y = x >> c;
1412 if (y != 0) {
1413 n = n - c;
1414 x = y;
1415 }
1416 c = c >> 1;
1417 } while (c != 0);
1418
1419 return n - x;
1420 }
1421
1422 static inline int64_t msa_nloc_df(uint32_t df, int64_t arg)
1423 {
1424 return msa_nlzc_df(df, UNSIGNED((~arg), df));
1425 }
1426
1427 void helper_msa_fill_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1428 uint32_t rs)
1429 {
1430 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1431 uint32_t i;
1432
1433 switch (df) {
1434 case DF_BYTE:
1435 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
1436 pwd->b[i] = (int8_t)env->active_tc.gpr[rs];
1437 }
1438 break;
1439 case DF_HALF:
1440 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
1441 pwd->h[i] = (int16_t)env->active_tc.gpr[rs];
1442 }
1443 break;
1444 case DF_WORD:
1445 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1446 pwd->w[i] = (int32_t)env->active_tc.gpr[rs];
1447 }
1448 break;
1449 case DF_DOUBLE:
1450 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1451 pwd->d[i] = (int64_t)env->active_tc.gpr[rs];
1452 }
1453 break;
1454 default:
1455 assert(0);
1456 }
1457 }
1458
1459 #define MSA_UNOP_DF(func) \
1460 void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, \
1461 uint32_t wd, uint32_t ws) \
1462 { \
1463 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
1464 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
1465 uint32_t i; \
1466 \
1467 switch (df) { \
1468 case DF_BYTE: \
1469 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
1470 pwd->b[i] = msa_ ## func ## _df(df, pws->b[i]); \
1471 } \
1472 break; \
1473 case DF_HALF: \
1474 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
1475 pwd->h[i] = msa_ ## func ## _df(df, pws->h[i]); \
1476 } \
1477 break; \
1478 case DF_WORD: \
1479 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
1480 pwd->w[i] = msa_ ## func ## _df(df, pws->w[i]); \
1481 } \
1482 break; \
1483 case DF_DOUBLE: \
1484 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
1485 pwd->d[i] = msa_ ## func ## _df(df, pws->d[i]); \
1486 } \
1487 break; \
1488 default: \
1489 assert(0); \
1490 } \
1491 }
1492
1493 MSA_UNOP_DF(nlzc)
1494 MSA_UNOP_DF(nloc)
1495 MSA_UNOP_DF(pcnt)
1496 #undef MSA_UNOP_DF
1497
1498 #define FLOAT_ONE32 make_float32(0x3f8 << 20)
1499 #define FLOAT_ONE64 make_float64(0x3ffULL << 52)
1500
1501 #define FLOAT_SNAN16(s) (float16_default_nan(s) ^ 0x0220)
1502 /* 0x7c20 */
1503 #define FLOAT_SNAN32(s) (float32_default_nan(s) ^ 0x00400020)
1504 /* 0x7f800020 */
1505 #define FLOAT_SNAN64(s) (float64_default_nan(s) ^ 0x0008000000000020ULL)
1506 /* 0x7ff0000000000020 */
1507
1508 static inline void clear_msacsr_cause(CPUMIPSState *env)
1509 {
1510 SET_FP_CAUSE(env->active_tc.msacsr, 0);
1511 }
1512
1513 static inline void check_msacsr_cause(CPUMIPSState *env, uintptr_t retaddr)
1514 {
1515 if ((GET_FP_CAUSE(env->active_tc.msacsr) &
1516 (GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED)) == 0) {
1517 UPDATE_FP_FLAGS(env->active_tc.msacsr,
1518 GET_FP_CAUSE(env->active_tc.msacsr));
1519 } else {
1520 do_raise_exception(env, EXCP_MSAFPE, retaddr);
1521 }
1522 }
1523
1524 /* Flush-to-zero use cases for update_msacsr() */
1525 #define CLEAR_FS_UNDERFLOW 1
1526 #define CLEAR_IS_INEXACT 2
1527 #define RECIPROCAL_INEXACT 4
1528
1529 static inline int update_msacsr(CPUMIPSState *env, int action, int denormal)
1530 {
1531 int ieee_ex;
1532
1533 int c;
1534 int cause;
1535 int enable;
1536
1537 ieee_ex = get_float_exception_flags(&env->active_tc.msa_fp_status);
1538
1539 /* QEMU softfloat does not signal all underflow cases */
1540 if (denormal) {
1541 ieee_ex |= float_flag_underflow;
1542 }
1543
1544 c = ieee_ex_to_mips(ieee_ex);
1545 enable = GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED;
1546
1547 /* Set Inexact (I) when flushing inputs to zero */
1548 if ((ieee_ex & float_flag_input_denormal) &&
1549 (env->active_tc.msacsr & MSACSR_FS_MASK) != 0) {
1550 if (action & CLEAR_IS_INEXACT) {
1551 c &= ~FP_INEXACT;
1552 } else {
1553 c |= FP_INEXACT;
1554 }
1555 }
1556
1557 /* Set Inexact (I) and Underflow (U) when flushing outputs to zero */
1558 if ((ieee_ex & float_flag_output_denormal) &&
1559 (env->active_tc.msacsr & MSACSR_FS_MASK) != 0) {
1560 c |= FP_INEXACT;
1561 if (action & CLEAR_FS_UNDERFLOW) {
1562 c &= ~FP_UNDERFLOW;
1563 } else {
1564 c |= FP_UNDERFLOW;
1565 }
1566 }
1567
1568 /* Set Inexact (I) when Overflow (O) is not enabled */
1569 if ((c & FP_OVERFLOW) != 0 && (enable & FP_OVERFLOW) == 0) {
1570 c |= FP_INEXACT;
1571 }
1572
1573 /* Clear Exact Underflow when Underflow (U) is not enabled */
1574 if ((c & FP_UNDERFLOW) != 0 && (enable & FP_UNDERFLOW) == 0 &&
1575 (c & FP_INEXACT) == 0) {
1576 c &= ~FP_UNDERFLOW;
1577 }
1578
1579 /* Reciprocal operations set only Inexact when valid and not
1580 divide by zero */
1581 if ((action & RECIPROCAL_INEXACT) &&
1582 (c & (FP_INVALID | FP_DIV0)) == 0) {
1583 c = FP_INEXACT;
1584 }
1585
1586 cause = c & enable; /* all current enabled exceptions */
1587
1588 if (cause == 0) {
1589 /* No enabled exception, update the MSACSR Cause
1590 with all current exceptions */
1591 SET_FP_CAUSE(env->active_tc.msacsr,
1592 (GET_FP_CAUSE(env->active_tc.msacsr) | c));
1593 } else {
1594 /* Current exceptions are enabled */
1595 if ((env->active_tc.msacsr & MSACSR_NX_MASK) == 0) {
1596 /* Exception(s) will trap, update MSACSR Cause
1597 with all enabled exceptions */
1598 SET_FP_CAUSE(env->active_tc.msacsr,
1599 (GET_FP_CAUSE(env->active_tc.msacsr) | c));
1600 }
1601 }
1602
1603 return c;
1604 }
1605
1606 static inline int get_enabled_exceptions(const CPUMIPSState *env, int c)
1607 {
1608 int enable = GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED;
1609 return c & enable;
1610 }
1611
1612 static inline float16 float16_from_float32(int32_t a, flag ieee,
1613 float_status *status)
1614 {
1615 float16 f_val;
1616
1617 f_val = float32_to_float16((float32)a, ieee, status);
1618 f_val = float16_maybe_silence_nan(f_val, status);
1619
1620 return a < 0 ? (f_val | (1 << 15)) : f_val;
1621 }
1622
1623 static inline float32 float32_from_float64(int64_t a, float_status *status)
1624 {
1625 float32 f_val;
1626
1627 f_val = float64_to_float32((float64)a, status);
1628 f_val = float32_maybe_silence_nan(f_val, status);
1629
1630 return a < 0 ? (f_val | (1 << 31)) : f_val;
1631 }
1632
1633 static inline float32 float32_from_float16(int16_t a, flag ieee,
1634 float_status *status)
1635 {
1636 float32 f_val;
1637
1638 f_val = float16_to_float32((float16)a, ieee, status);
1639 f_val = float32_maybe_silence_nan(f_val, status);
1640
1641 return a < 0 ? (f_val | (1 << 31)) : f_val;
1642 }
1643
1644 static inline float64 float64_from_float32(int32_t a, float_status *status)
1645 {
1646 float64 f_val;
1647
1648 f_val = float32_to_float64((float64)a, status);
1649 f_val = float64_maybe_silence_nan(f_val, status);
1650
1651 return a < 0 ? (f_val | (1ULL << 63)) : f_val;
1652 }
1653
1654 static inline float32 float32_from_q16(int16_t a, float_status *status)
1655 {
1656 float32 f_val;
1657
1658 /* conversion as integer and scaling */
1659 f_val = int32_to_float32(a, status);
1660 f_val = float32_scalbn(f_val, -15, status);
1661
1662 return f_val;
1663 }
1664
1665 static inline float64 float64_from_q32(int32_t a, float_status *status)
1666 {
1667 float64 f_val;
1668
1669 /* conversion as integer and scaling */
1670 f_val = int32_to_float64(a, status);
1671 f_val = float64_scalbn(f_val, -31, status);
1672
1673 return f_val;
1674 }
1675
1676 static inline int16_t float32_to_q16(float32 a, float_status *status)
1677 {
1678 int32_t q_val;
1679 int32_t q_min = 0xffff8000;
1680 int32_t q_max = 0x00007fff;
1681
1682 int ieee_ex;
1683
1684 if (float32_is_any_nan(a)) {
1685 float_raise(float_flag_invalid, status);
1686 return 0;
1687 }
1688
1689 /* scaling */
1690 a = float32_scalbn(a, 15, status);
1691
1692 ieee_ex = get_float_exception_flags(status);
1693 set_float_exception_flags(ieee_ex & (~float_flag_underflow)
1694 , status);
1695
1696 if (ieee_ex & float_flag_overflow) {
1697 float_raise(float_flag_inexact, status);
1698 return (int32_t)a < 0 ? q_min : q_max;
1699 }
1700
1701 /* conversion to int */
1702 q_val = float32_to_int32(a, status);
1703
1704 ieee_ex = get_float_exception_flags(status);
1705 set_float_exception_flags(ieee_ex & (~float_flag_underflow)
1706 , status);
1707
1708 if (ieee_ex & float_flag_invalid) {
1709 set_float_exception_flags(ieee_ex & (~float_flag_invalid)
1710 , status);
1711 float_raise(float_flag_overflow | float_flag_inexact, status);
1712 return (int32_t)a < 0 ? q_min : q_max;
1713 }
1714
1715 if (q_val < q_min) {
1716 float_raise(float_flag_overflow | float_flag_inexact, status);
1717 return (int16_t)q_min;
1718 }
1719
1720 if (q_max < q_val) {
1721 float_raise(float_flag_overflow | float_flag_inexact, status);
1722 return (int16_t)q_max;
1723 }
1724
1725 return (int16_t)q_val;
1726 }
1727
1728 static inline int32_t float64_to_q32(float64 a, float_status *status)
1729 {
1730 int64_t q_val;
1731 int64_t q_min = 0xffffffff80000000LL;
1732 int64_t q_max = 0x000000007fffffffLL;
1733
1734 int ieee_ex;
1735
1736 if (float64_is_any_nan(a)) {
1737 float_raise(float_flag_invalid, status);
1738 return 0;
1739 }
1740
1741 /* scaling */
1742 a = float64_scalbn(a, 31, status);
1743
1744 ieee_ex = get_float_exception_flags(status);
1745 set_float_exception_flags(ieee_ex & (~float_flag_underflow)
1746 , status);
1747
1748 if (ieee_ex & float_flag_overflow) {
1749 float_raise(float_flag_inexact, status);
1750 return (int64_t)a < 0 ? q_min : q_max;
1751 }
1752
1753 /* conversion to integer */
1754 q_val = float64_to_int64(a, status);
1755
1756 ieee_ex = get_float_exception_flags(status);
1757 set_float_exception_flags(ieee_ex & (~float_flag_underflow)
1758 , status);
1759
1760 if (ieee_ex & float_flag_invalid) {
1761 set_float_exception_flags(ieee_ex & (~float_flag_invalid)
1762 , status);
1763 float_raise(float_flag_overflow | float_flag_inexact, status);
1764 return (int64_t)a < 0 ? q_min : q_max;
1765 }
1766
1767 if (q_val < q_min) {
1768 float_raise(float_flag_overflow | float_flag_inexact, status);
1769 return (int32_t)q_min;
1770 }
1771
1772 if (q_max < q_val) {
1773 float_raise(float_flag_overflow | float_flag_inexact, status);
1774 return (int32_t)q_max;
1775 }
1776
1777 return (int32_t)q_val;
1778 }
1779
1780 #define MSA_FLOAT_COND(DEST, OP, ARG1, ARG2, BITS, QUIET) \
1781 do { \
1782 float_status *status = &env->active_tc.msa_fp_status; \
1783 int c; \
1784 int64_t cond; \
1785 set_float_exception_flags(0, status); \
1786 if (!QUIET) { \
1787 cond = float ## BITS ## _ ## OP(ARG1, ARG2, status); \
1788 } else { \
1789 cond = float ## BITS ## _ ## OP ## _quiet(ARG1, ARG2, status); \
1790 } \
1791 DEST = cond ? M_MAX_UINT(BITS) : 0; \
1792 c = update_msacsr(env, CLEAR_IS_INEXACT, 0); \
1793 \
1794 if (get_enabled_exceptions(env, c)) { \
1795 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
1796 } \
1797 } while (0)
1798
1799 #define MSA_FLOAT_AF(DEST, ARG1, ARG2, BITS, QUIET) \
1800 do { \
1801 MSA_FLOAT_COND(DEST, eq, ARG1, ARG2, BITS, QUIET); \
1802 if ((DEST & M_MAX_UINT(BITS)) == M_MAX_UINT(BITS)) { \
1803 DEST = 0; \
1804 } \
1805 } while (0)
1806
1807 #define MSA_FLOAT_UEQ(DEST, ARG1, ARG2, BITS, QUIET) \
1808 do { \
1809 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
1810 if (DEST == 0) { \
1811 MSA_FLOAT_COND(DEST, eq, ARG1, ARG2, BITS, QUIET); \
1812 } \
1813 } while (0)
1814
1815 #define MSA_FLOAT_NE(DEST, ARG1, ARG2, BITS, QUIET) \
1816 do { \
1817 MSA_FLOAT_COND(DEST, lt, ARG1, ARG2, BITS, QUIET); \
1818 if (DEST == 0) { \
1819 MSA_FLOAT_COND(DEST, lt, ARG2, ARG1, BITS, QUIET); \
1820 } \
1821 } while (0)
1822
1823 #define MSA_FLOAT_UNE(DEST, ARG1, ARG2, BITS, QUIET) \
1824 do { \
1825 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
1826 if (DEST == 0) { \
1827 MSA_FLOAT_COND(DEST, lt, ARG1, ARG2, BITS, QUIET); \
1828 if (DEST == 0) { \
1829 MSA_FLOAT_COND(DEST, lt, ARG2, ARG1, BITS, QUIET); \
1830 } \
1831 } \
1832 } while (0)
1833
1834 #define MSA_FLOAT_ULE(DEST, ARG1, ARG2, BITS, QUIET) \
1835 do { \
1836 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
1837 if (DEST == 0) { \
1838 MSA_FLOAT_COND(DEST, le, ARG1, ARG2, BITS, QUIET); \
1839 } \
1840 } while (0)
1841
1842 #define MSA_FLOAT_ULT(DEST, ARG1, ARG2, BITS, QUIET) \
1843 do { \
1844 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
1845 if (DEST == 0) { \
1846 MSA_FLOAT_COND(DEST, lt, ARG1, ARG2, BITS, QUIET); \
1847 } \
1848 } while (0)
1849
1850 #define MSA_FLOAT_OR(DEST, ARG1, ARG2, BITS, QUIET) \
1851 do { \
1852 MSA_FLOAT_COND(DEST, le, ARG1, ARG2, BITS, QUIET); \
1853 if (DEST == 0) { \
1854 MSA_FLOAT_COND(DEST, le, ARG2, ARG1, BITS, QUIET); \
1855 } \
1856 } while (0)
1857
1858 static inline void compare_af(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
1859 wr_t *pwt, uint32_t df, int quiet,
1860 uintptr_t retaddr)
1861 {
1862 wr_t wx, *pwx = &wx;
1863 uint32_t i;
1864
1865 clear_msacsr_cause(env);
1866
1867 switch (df) {
1868 case DF_WORD:
1869 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1870 MSA_FLOAT_AF(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
1871 }
1872 break;
1873 case DF_DOUBLE:
1874 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1875 MSA_FLOAT_AF(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
1876 }
1877 break;
1878 default:
1879 assert(0);
1880 }
1881
1882 check_msacsr_cause(env, retaddr);
1883
1884 msa_move_v(pwd, pwx);
1885 }
1886
1887 static inline void compare_un(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
1888 wr_t *pwt, uint32_t df, int quiet,
1889 uintptr_t retaddr)
1890 {
1891 wr_t wx, *pwx = &wx;
1892 uint32_t i;
1893
1894 clear_msacsr_cause(env);
1895
1896 switch (df) {
1897 case DF_WORD:
1898 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1899 MSA_FLOAT_COND(pwx->w[i], unordered, pws->w[i], pwt->w[i], 32,
1900 quiet);
1901 }
1902 break;
1903 case DF_DOUBLE:
1904 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1905 MSA_FLOAT_COND(pwx->d[i], unordered, pws->d[i], pwt->d[i], 64,
1906 quiet);
1907 }
1908 break;
1909 default:
1910 assert(0);
1911 }
1912
1913 check_msacsr_cause(env, retaddr);
1914
1915 msa_move_v(pwd, pwx);
1916 }
1917
1918 static inline void compare_eq(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
1919 wr_t *pwt, uint32_t df, int quiet,
1920 uintptr_t retaddr)
1921 {
1922 wr_t wx, *pwx = &wx;
1923 uint32_t i;
1924
1925 clear_msacsr_cause(env);
1926
1927 switch (df) {
1928 case DF_WORD:
1929 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1930 MSA_FLOAT_COND(pwx->w[i], eq, pws->w[i], pwt->w[i], 32, quiet);
1931 }
1932 break;
1933 case DF_DOUBLE:
1934 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1935 MSA_FLOAT_COND(pwx->d[i], eq, pws->d[i], pwt->d[i], 64, quiet);
1936 }
1937 break;
1938 default:
1939 assert(0);
1940 }
1941
1942 check_msacsr_cause(env, retaddr);
1943
1944 msa_move_v(pwd, pwx);
1945 }
1946
1947 static inline void compare_ueq(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
1948 wr_t *pwt, uint32_t df, int quiet,
1949 uintptr_t retaddr)
1950 {
1951 wr_t wx, *pwx = &wx;
1952 uint32_t i;
1953
1954 clear_msacsr_cause(env);
1955
1956 switch (df) {
1957 case DF_WORD:
1958 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1959 MSA_FLOAT_UEQ(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
1960 }
1961 break;
1962 case DF_DOUBLE:
1963 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1964 MSA_FLOAT_UEQ(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
1965 }
1966 break;
1967 default:
1968 assert(0);
1969 }
1970
1971 check_msacsr_cause(env, retaddr);
1972
1973 msa_move_v(pwd, pwx);
1974 }
1975
1976 static inline void compare_lt(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
1977 wr_t *pwt, uint32_t df, int quiet,
1978 uintptr_t retaddr)
1979 {
1980 wr_t wx, *pwx = &wx;
1981 uint32_t i;
1982
1983 clear_msacsr_cause(env);
1984
1985 switch (df) {
1986 case DF_WORD:
1987 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1988 MSA_FLOAT_COND(pwx->w[i], lt, pws->w[i], pwt->w[i], 32, quiet);
1989 }
1990 break;
1991 case DF_DOUBLE:
1992 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1993 MSA_FLOAT_COND(pwx->d[i], lt, pws->d[i], pwt->d[i], 64, quiet);
1994 }
1995 break;
1996 default:
1997 assert(0);
1998 }
1999
2000 check_msacsr_cause(env, retaddr);
2001
2002 msa_move_v(pwd, pwx);
2003 }
2004
2005 static inline void compare_ult(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2006 wr_t *pwt, uint32_t df, int quiet,
2007 uintptr_t retaddr)
2008 {
2009 wr_t wx, *pwx = &wx;
2010 uint32_t i;
2011
2012 clear_msacsr_cause(env);
2013
2014 switch (df) {
2015 case DF_WORD:
2016 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2017 MSA_FLOAT_ULT(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
2018 }
2019 break;
2020 case DF_DOUBLE:
2021 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2022 MSA_FLOAT_ULT(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
2023 }
2024 break;
2025 default:
2026 assert(0);
2027 }
2028
2029 check_msacsr_cause(env, retaddr);
2030
2031 msa_move_v(pwd, pwx);
2032 }
2033
2034 static inline void compare_le(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2035 wr_t *pwt, uint32_t df, int quiet,
2036 uintptr_t retaddr)
2037 {
2038 wr_t wx, *pwx = &wx;
2039 uint32_t i;
2040
2041 clear_msacsr_cause(env);
2042
2043 switch (df) {
2044 case DF_WORD:
2045 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2046 MSA_FLOAT_COND(pwx->w[i], le, pws->w[i], pwt->w[i], 32, quiet);
2047 }
2048 break;
2049 case DF_DOUBLE:
2050 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2051 MSA_FLOAT_COND(pwx->d[i], le, pws->d[i], pwt->d[i], 64, quiet);
2052 }
2053 break;
2054 default:
2055 assert(0);
2056 }
2057
2058 check_msacsr_cause(env, retaddr);
2059
2060 msa_move_v(pwd, pwx);
2061 }
2062
2063 static inline void compare_ule(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2064 wr_t *pwt, uint32_t df, int quiet,
2065 uintptr_t retaddr)
2066 {
2067 wr_t wx, *pwx = &wx;
2068 uint32_t i;
2069
2070 clear_msacsr_cause(env);
2071
2072 switch (df) {
2073 case DF_WORD:
2074 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2075 MSA_FLOAT_ULE(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
2076 }
2077 break;
2078 case DF_DOUBLE:
2079 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2080 MSA_FLOAT_ULE(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
2081 }
2082 break;
2083 default:
2084 assert(0);
2085 }
2086
2087 check_msacsr_cause(env, retaddr);
2088
2089 msa_move_v(pwd, pwx);
2090 }
2091
2092 static inline void compare_or(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2093 wr_t *pwt, uint32_t df, int quiet,
2094 uintptr_t retaddr)
2095 {
2096 wr_t wx, *pwx = &wx;
2097 uint32_t i;
2098
2099 clear_msacsr_cause(env);
2100
2101 switch (df) {
2102 case DF_WORD:
2103 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2104 MSA_FLOAT_OR(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
2105 }
2106 break;
2107 case DF_DOUBLE:
2108 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2109 MSA_FLOAT_OR(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
2110 }
2111 break;
2112 default:
2113 assert(0);
2114 }
2115
2116 check_msacsr_cause(env, retaddr);
2117
2118 msa_move_v(pwd, pwx);
2119 }
2120
2121 static inline void compare_une(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2122 wr_t *pwt, uint32_t df, int quiet,
2123 uintptr_t retaddr)
2124 {
2125 wr_t wx, *pwx = &wx;
2126 uint32_t i;
2127
2128 clear_msacsr_cause(env);
2129
2130 switch (df) {
2131 case DF_WORD:
2132 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2133 MSA_FLOAT_UNE(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
2134 }
2135 break;
2136 case DF_DOUBLE:
2137 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2138 MSA_FLOAT_UNE(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
2139 }
2140 break;
2141 default:
2142 assert(0);
2143 }
2144
2145 check_msacsr_cause(env, retaddr);
2146
2147 msa_move_v(pwd, pwx);
2148 }
2149
2150 static inline void compare_ne(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2151 wr_t *pwt, uint32_t df, int quiet,
2152 uintptr_t retaddr)
2153 {
2154 wr_t wx, *pwx = &wx;
2155 uint32_t i;
2156
2157 clear_msacsr_cause(env);
2158
2159 switch (df) {
2160 case DF_WORD:
2161 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2162 MSA_FLOAT_NE(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
2163 }
2164 break;
2165 case DF_DOUBLE:
2166 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2167 MSA_FLOAT_NE(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
2168 }
2169 break;
2170 default:
2171 assert(0);
2172 }
2173
2174 check_msacsr_cause(env, retaddr);
2175
2176 msa_move_v(pwd, pwx);
2177 }
2178
2179 void helper_msa_fcaf_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2180 uint32_t ws, uint32_t wt)
2181 {
2182 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2183 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2184 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2185 compare_af(env, pwd, pws, pwt, df, 1, GETPC());
2186 }
2187
2188 void helper_msa_fcun_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2189 uint32_t ws, uint32_t wt)
2190 {
2191 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2192 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2193 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2194 compare_un(env, pwd, pws, pwt, df, 1, GETPC());
2195 }
2196
2197 void helper_msa_fceq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2198 uint32_t ws, uint32_t wt)
2199 {
2200 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2201 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2202 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2203 compare_eq(env, pwd, pws, pwt, df, 1, GETPC());
2204 }
2205
2206 void helper_msa_fcueq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2207 uint32_t ws, uint32_t wt)
2208 {
2209 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2210 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2211 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2212 compare_ueq(env, pwd, pws, pwt, df, 1, GETPC());
2213 }
2214
2215 void helper_msa_fclt_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2216 uint32_t ws, uint32_t wt)
2217 {
2218 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2219 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2220 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2221 compare_lt(env, pwd, pws, pwt, df, 1, GETPC());
2222 }
2223
2224 void helper_msa_fcult_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2225 uint32_t ws, uint32_t wt)
2226 {
2227 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2228 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2229 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2230 compare_ult(env, pwd, pws, pwt, df, 1, GETPC());
2231 }
2232
2233 void helper_msa_fcle_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2234 uint32_t ws, uint32_t wt)
2235 {
2236 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2237 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2238 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2239 compare_le(env, pwd, pws, pwt, df, 1, GETPC());
2240 }
2241
2242 void helper_msa_fcule_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2243 uint32_t ws, uint32_t wt)
2244 {
2245 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2246 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2247 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2248 compare_ule(env, pwd, pws, pwt, df, 1, GETPC());
2249 }
2250
2251 void helper_msa_fsaf_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2252 uint32_t ws, uint32_t wt)
2253 {
2254 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2255 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2256 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2257 compare_af(env, pwd, pws, pwt, df, 0, GETPC());
2258 }
2259
2260 void helper_msa_fsun_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2261 uint32_t ws, uint32_t wt)
2262 {
2263 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2264 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2265 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2266 compare_un(env, pwd, pws, pwt, df, 0, GETPC());
2267 }
2268
2269 void helper_msa_fseq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2270 uint32_t ws, uint32_t wt)
2271 {
2272 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2273 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2274 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2275 compare_eq(env, pwd, pws, pwt, df, 0, GETPC());
2276 }
2277
2278 void helper_msa_fsueq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2279 uint32_t ws, uint32_t wt)
2280 {
2281 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2282 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2283 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2284 compare_ueq(env, pwd, pws, pwt, df, 0, GETPC());
2285 }
2286
2287 void helper_msa_fslt_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2288 uint32_t ws, uint32_t wt)
2289 {
2290 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2291 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2292 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2293 compare_lt(env, pwd, pws, pwt, df, 0, GETPC());
2294 }
2295
2296 void helper_msa_fsult_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2297 uint32_t ws, uint32_t wt)
2298 {
2299 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2300 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2301 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2302 compare_ult(env, pwd, pws, pwt, df, 0, GETPC());
2303 }
2304
2305 void helper_msa_fsle_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2306 uint32_t ws, uint32_t wt)
2307 {
2308 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2309 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2310 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2311 compare_le(env, pwd, pws, pwt, df, 0, GETPC());
2312 }
2313
2314 void helper_msa_fsule_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2315 uint32_t ws, uint32_t wt)
2316 {
2317 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2318 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2319 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2320 compare_ule(env, pwd, pws, pwt, df, 0, GETPC());
2321 }
2322
2323 void helper_msa_fcor_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2324 uint32_t ws, uint32_t wt)
2325 {
2326 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2327 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2328 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2329 compare_or(env, pwd, pws, pwt, df, 1, GETPC());
2330 }
2331
2332 void helper_msa_fcune_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2333 uint32_t ws, uint32_t wt)
2334 {
2335 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2336 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2337 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2338 compare_une(env, pwd, pws, pwt, df, 1, GETPC());
2339 }
2340
2341 void helper_msa_fcne_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2342 uint32_t ws, uint32_t wt)
2343 {
2344 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2345 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2346 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2347 compare_ne(env, pwd, pws, pwt, df, 1, GETPC());
2348 }
2349
2350 void helper_msa_fsor_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2351 uint32_t ws, uint32_t wt)
2352 {
2353 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2354 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2355 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2356 compare_or(env, pwd, pws, pwt, df, 0, GETPC());
2357 }
2358
2359 void helper_msa_fsune_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2360 uint32_t ws, uint32_t wt)
2361 {
2362 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2363 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2364 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2365 compare_une(env, pwd, pws, pwt, df, 0, GETPC());
2366 }
2367
2368 void helper_msa_fsne_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2369 uint32_t ws, uint32_t wt)
2370 {
2371 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2372 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2373 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2374 compare_ne(env, pwd, pws, pwt, df, 0, GETPC());
2375 }
2376
2377 #define float16_is_zero(ARG) 0
2378 #define float16_is_zero_or_denormal(ARG) 0
2379
2380 #define IS_DENORMAL(ARG, BITS) \
2381 (!float ## BITS ## _is_zero(ARG) \
2382 && float ## BITS ## _is_zero_or_denormal(ARG))
2383
2384 #define MSA_FLOAT_BINOP(DEST, OP, ARG1, ARG2, BITS) \
2385 do { \
2386 float_status *status = &env->active_tc.msa_fp_status; \
2387 int c; \
2388 \
2389 set_float_exception_flags(0, status); \
2390 DEST = float ## BITS ## _ ## OP(ARG1, ARG2, status); \
2391 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
2392 \
2393 if (get_enabled_exceptions(env, c)) { \
2394 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
2395 } \
2396 } while (0)
2397
2398 void helper_msa_fadd_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2399 uint32_t ws, uint32_t wt)
2400 {
2401 wr_t wx, *pwx = &wx;
2402 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2403 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2404 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2405 uint32_t i;
2406
2407 clear_msacsr_cause(env);
2408
2409 switch (df) {
2410 case DF_WORD:
2411 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2412 MSA_FLOAT_BINOP(pwx->w[i], add, pws->w[i], pwt->w[i], 32);
2413 }
2414 break;
2415 case DF_DOUBLE:
2416 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2417 MSA_FLOAT_BINOP(pwx->d[i], add, pws->d[i], pwt->d[i], 64);
2418 }
2419 break;
2420 default:
2421 assert(0);
2422 }
2423
2424 check_msacsr_cause(env, GETPC());
2425 msa_move_v(pwd, pwx);
2426 }
2427
2428 void helper_msa_fsub_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2429 uint32_t ws, uint32_t wt)
2430 {
2431 wr_t wx, *pwx = &wx;
2432 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2433 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2434 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2435 uint32_t i;
2436
2437 clear_msacsr_cause(env);
2438
2439 switch (df) {
2440 case DF_WORD:
2441 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2442 MSA_FLOAT_BINOP(pwx->w[i], sub, pws->w[i], pwt->w[i], 32);
2443 }
2444 break;
2445 case DF_DOUBLE:
2446 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2447 MSA_FLOAT_BINOP(pwx->d[i], sub, pws->d[i], pwt->d[i], 64);
2448 }
2449 break;
2450 default:
2451 assert(0);
2452 }
2453
2454 check_msacsr_cause(env, GETPC());
2455 msa_move_v(pwd, pwx);
2456 }
2457
2458 void helper_msa_fmul_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2459 uint32_t ws, uint32_t wt)
2460 {
2461 wr_t wx, *pwx = &wx;
2462 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2463 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2464 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2465 uint32_t i;
2466
2467 clear_msacsr_cause(env);
2468
2469 switch (df) {
2470 case DF_WORD:
2471 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2472 MSA_FLOAT_BINOP(pwx->w[i], mul, pws->w[i], pwt->w[i], 32);
2473 }
2474 break;
2475 case DF_DOUBLE:
2476 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2477 MSA_FLOAT_BINOP(pwx->d[i], mul, pws->d[i], pwt->d[i], 64);
2478 }
2479 break;
2480 default:
2481 assert(0);
2482 }
2483
2484 check_msacsr_cause(env, GETPC());
2485
2486 msa_move_v(pwd, pwx);
2487 }
2488
2489 void helper_msa_fdiv_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2490 uint32_t ws, uint32_t wt)
2491 {
2492 wr_t wx, *pwx = &wx;
2493 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2494 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2495 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2496 uint32_t i;
2497
2498 clear_msacsr_cause(env);
2499
2500 switch (df) {
2501 case DF_WORD:
2502 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2503 MSA_FLOAT_BINOP(pwx->w[i], div, pws->w[i], pwt->w[i], 32);
2504 }
2505 break;
2506 case DF_DOUBLE:
2507 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2508 MSA_FLOAT_BINOP(pwx->d[i], div, pws->d[i], pwt->d[i], 64);
2509 }
2510 break;
2511 default:
2512 assert(0);
2513 }
2514
2515 check_msacsr_cause(env, GETPC());
2516
2517 msa_move_v(pwd, pwx);
2518 }
2519
2520 #define MSA_FLOAT_MULADD(DEST, ARG1, ARG2, ARG3, NEGATE, BITS) \
2521 do { \
2522 float_status *status = &env->active_tc.msa_fp_status; \
2523 int c; \
2524 \
2525 set_float_exception_flags(0, status); \
2526 DEST = float ## BITS ## _muladd(ARG2, ARG3, ARG1, NEGATE, status); \
2527 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
2528 \
2529 if (get_enabled_exceptions(env, c)) { \
2530 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
2531 } \
2532 } while (0)
2533
2534 void helper_msa_fmadd_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2535 uint32_t ws, uint32_t wt)
2536 {
2537 wr_t wx, *pwx = &wx;
2538 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2539 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2540 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2541 uint32_t i;
2542
2543 clear_msacsr_cause(env);
2544
2545 switch (df) {
2546 case DF_WORD:
2547 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2548 MSA_FLOAT_MULADD(pwx->w[i], pwd->w[i],
2549 pws->w[i], pwt->w[i], 0, 32);
2550 }
2551 break;
2552 case DF_DOUBLE:
2553 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2554 MSA_FLOAT_MULADD(pwx->d[i], pwd->d[i],
2555 pws->d[i], pwt->d[i], 0, 64);
2556 }
2557 break;
2558 default:
2559 assert(0);
2560 }
2561
2562 check_msacsr_cause(env, GETPC());
2563
2564 msa_move_v(pwd, pwx);
2565 }
2566
2567 void helper_msa_fmsub_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2568 uint32_t ws, uint32_t wt)
2569 {
2570 wr_t wx, *pwx = &wx;
2571 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2572 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2573 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2574 uint32_t i;
2575
2576 clear_msacsr_cause(env);
2577
2578 switch (df) {
2579 case DF_WORD:
2580 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2581 MSA_FLOAT_MULADD(pwx->w[i], pwd->w[i],
2582 pws->w[i], pwt->w[i],
2583 float_muladd_negate_product, 32);
2584 }
2585 break;
2586 case DF_DOUBLE:
2587 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2588 MSA_FLOAT_MULADD(pwx->d[i], pwd->d[i],
2589 pws->d[i], pwt->d[i],
2590 float_muladd_negate_product, 64);
2591 }
2592 break;
2593 default:
2594 assert(0);
2595 }
2596
2597 check_msacsr_cause(env, GETPC());
2598
2599 msa_move_v(pwd, pwx);
2600 }
2601
2602 void helper_msa_fexp2_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2603 uint32_t ws, uint32_t wt)
2604 {
2605 wr_t wx, *pwx = &wx;
2606 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2607 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2608 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2609 uint32_t i;
2610
2611 clear_msacsr_cause(env);
2612
2613 switch (df) {
2614 case DF_WORD:
2615 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2616 MSA_FLOAT_BINOP(pwx->w[i], scalbn, pws->w[i],
2617 pwt->w[i] > 0x200 ? 0x200 :
2618 pwt->w[i] < -0x200 ? -0x200 : pwt->w[i],
2619 32);
2620 }
2621 break;
2622 case DF_DOUBLE:
2623 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2624 MSA_FLOAT_BINOP(pwx->d[i], scalbn, pws->d[i],
2625 pwt->d[i] > 0x1000 ? 0x1000 :
2626 pwt->d[i] < -0x1000 ? -0x1000 : pwt->d[i],
2627 64);
2628 }
2629 break;
2630 default:
2631 assert(0);
2632 }
2633
2634 check_msacsr_cause(env, GETPC());
2635
2636 msa_move_v(pwd, pwx);
2637 }
2638
2639 #define MSA_FLOAT_UNOP(DEST, OP, ARG, BITS) \
2640 do { \
2641 float_status *status = &env->active_tc.msa_fp_status; \
2642 int c; \
2643 \
2644 set_float_exception_flags(0, status); \
2645 DEST = float ## BITS ## _ ## OP(ARG, status); \
2646 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
2647 \
2648 if (get_enabled_exceptions(env, c)) { \
2649 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
2650 } \
2651 } while (0)
2652
2653 void helper_msa_fexdo_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2654 uint32_t ws, uint32_t wt)
2655 {
2656 wr_t wx, *pwx = &wx;
2657 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2658 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2659 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2660 uint32_t i;
2661
2662 clear_msacsr_cause(env);
2663
2664 switch (df) {
2665 case DF_WORD:
2666 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2667 /* Half precision floats come in two formats: standard
2668 IEEE and "ARM" format. The latter gains extra exponent
2669 range by omitting the NaN/Inf encodings. */
2670 flag ieee = 1;
2671
2672 MSA_FLOAT_BINOP(Lh(pwx, i), from_float32, pws->w[i], ieee, 16);
2673 MSA_FLOAT_BINOP(Rh(pwx, i), from_float32, pwt->w[i], ieee, 16);
2674 }
2675 break;
2676 case DF_DOUBLE:
2677 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2678 MSA_FLOAT_UNOP(Lw(pwx, i), from_float64, pws->d[i], 32);
2679 MSA_FLOAT_UNOP(Rw(pwx, i), from_float64, pwt->d[i], 32);
2680 }
2681 break;
2682 default:
2683 assert(0);
2684 }
2685
2686 check_msacsr_cause(env, GETPC());
2687 msa_move_v(pwd, pwx);
2688 }
2689
2690 #define MSA_FLOAT_UNOP_XD(DEST, OP, ARG, BITS, XBITS) \
2691 do { \
2692 float_status *status = &env->active_tc.msa_fp_status; \
2693 int c; \
2694 \
2695 set_float_exception_flags(0, status); \
2696 DEST = float ## BITS ## _ ## OP(ARG, status); \
2697 c = update_msacsr(env, CLEAR_FS_UNDERFLOW, 0); \
2698 \
2699 if (get_enabled_exceptions(env, c)) { \
2700 DEST = ((FLOAT_SNAN ## XBITS(status) >> 6) << 6) | c; \
2701 } \
2702 } while (0)
2703
2704 void helper_msa_ftq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2705 uint32_t ws, uint32_t wt)
2706 {
2707 wr_t wx, *pwx = &wx;
2708 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2709 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2710 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2711 uint32_t i;
2712
2713 clear_msacsr_cause(env);
2714
2715 switch (df) {
2716 case DF_WORD:
2717 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2718 MSA_FLOAT_UNOP_XD(Lh(pwx, i), to_q16, pws->w[i], 32, 16);
2719 MSA_FLOAT_UNOP_XD(Rh(pwx, i), to_q16, pwt->w[i], 32, 16);
2720 }
2721 break;
2722 case DF_DOUBLE:
2723 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2724 MSA_FLOAT_UNOP_XD(Lw(pwx, i), to_q32, pws->d[i], 64, 32);
2725 MSA_FLOAT_UNOP_XD(Rw(pwx, i), to_q32, pwt->d[i], 64, 32);
2726 }
2727 break;
2728 default:
2729 assert(0);
2730 }
2731
2732 check_msacsr_cause(env, GETPC());
2733
2734 msa_move_v(pwd, pwx);
2735 }
2736
2737 #define NUMBER_QNAN_PAIR(ARG1, ARG2, BITS, STATUS) \
2738 !float ## BITS ## _is_any_nan(ARG1) \
2739 && float ## BITS ## _is_quiet_nan(ARG2, STATUS)
2740
2741 #define MSA_FLOAT_MAXOP(DEST, OP, ARG1, ARG2, BITS) \
2742 do { \
2743 float_status *status = &env->active_tc.msa_fp_status; \
2744 int c; \
2745 \
2746 set_float_exception_flags(0, status); \
2747 DEST = float ## BITS ## _ ## OP(ARG1, ARG2, status); \
2748 c = update_msacsr(env, 0, 0); \
2749 \
2750 if (get_enabled_exceptions(env, c)) { \
2751 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
2752 } \
2753 } while (0)
2754
2755 #define FMAXMIN_A(F, G, X, _S, _T, BITS, STATUS) \
2756 do { \
2757 uint## BITS ##_t S = _S, T = _T; \
2758 uint## BITS ##_t as, at, xs, xt, xd; \
2759 if (NUMBER_QNAN_PAIR(S, T, BITS, STATUS)) { \
2760 T = S; \
2761 } \
2762 else if (NUMBER_QNAN_PAIR(T, S, BITS, STATUS)) { \
2763 S = T; \
2764 } \
2765 as = float## BITS ##_abs(S); \
2766 at = float## BITS ##_abs(T); \
2767 MSA_FLOAT_MAXOP(xs, F, S, T, BITS); \
2768 MSA_FLOAT_MAXOP(xt, G, S, T, BITS); \
2769 MSA_FLOAT_MAXOP(xd, F, as, at, BITS); \
2770 X = (as == at || xd == float## BITS ##_abs(xs)) ? xs : xt; \
2771 } while (0)
2772
2773 void helper_msa_fmin_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2774 uint32_t ws, uint32_t wt)
2775 {
2776 float_status *status = &env->active_tc.msa_fp_status;
2777 wr_t wx, *pwx = &wx;
2778 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2779 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2780 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2781 uint32_t i;
2782
2783 clear_msacsr_cause(env);
2784
2785 switch (df) {
2786 case DF_WORD:
2787 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2788 if (NUMBER_QNAN_PAIR(pws->w[i], pwt->w[i], 32, status)) {
2789 MSA_FLOAT_MAXOP(pwx->w[i], min, pws->w[i], pws->w[i], 32);
2790 } else if (NUMBER_QNAN_PAIR(pwt->w[i], pws->w[i], 32, status)) {
2791 MSA_FLOAT_MAXOP(pwx->w[i], min, pwt->w[i], pwt->w[i], 32);
2792 } else {
2793 MSA_FLOAT_MAXOP(pwx->w[i], min, pws->w[i], pwt->w[i], 32);
2794 }
2795 }
2796 break;
2797 case DF_DOUBLE:
2798 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2799 if (NUMBER_QNAN_PAIR(pws->d[i], pwt->d[i], 64, status)) {
2800 MSA_FLOAT_MAXOP(pwx->d[i], min, pws->d[i], pws->d[i], 64);
2801 } else if (NUMBER_QNAN_PAIR(pwt->d[i], pws->d[i], 64, status)) {
2802 MSA_FLOAT_MAXOP(pwx->d[i], min, pwt->d[i], pwt->d[i], 64);
2803 } else {
2804 MSA_FLOAT_MAXOP(pwx->d[i], min, pws->d[i], pwt->d[i], 64);
2805 }
2806 }
2807 break;
2808 default:
2809 assert(0);
2810 }
2811
2812 check_msacsr_cause(env, GETPC());
2813
2814 msa_move_v(pwd, pwx);
2815 }
2816
2817 void helper_msa_fmin_a_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2818 uint32_t ws, uint32_t wt)
2819 {
2820 float_status *status = &env->active_tc.msa_fp_status;
2821 wr_t wx, *pwx = &wx;
2822 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2823 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2824 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2825 uint32_t i;
2826
2827 clear_msacsr_cause(env);
2828
2829 switch (df) {
2830 case DF_WORD:
2831 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2832 FMAXMIN_A(min, max, pwx->w[i], pws->w[i], pwt->w[i], 32, status);
2833 }
2834 break;
2835 case DF_DOUBLE:
2836 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2837 FMAXMIN_A(min, max, pwx->d[i], pws->d[i], pwt->d[i], 64, status);
2838 }
2839 break;
2840 default:
2841 assert(0);
2842 }
2843
2844 check_msacsr_cause(env, GETPC());
2845
2846 msa_move_v(pwd, pwx);
2847 }
2848
2849 void helper_msa_fmax_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2850 uint32_t ws, uint32_t wt)
2851 {
2852 float_status *status = &env->active_tc.msa_fp_status;
2853 wr_t wx, *pwx = &wx;
2854 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2855 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2856 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2857 uint32_t i;
2858
2859 clear_msacsr_cause(env);
2860
2861 switch (df) {
2862 case DF_WORD:
2863 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2864 if (NUMBER_QNAN_PAIR(pws->w[i], pwt->w[i], 32, status)) {
2865 MSA_FLOAT_MAXOP(pwx->w[i], max, pws->w[i], pws->w[i], 32);
2866 } else if (NUMBER_QNAN_PAIR(pwt->w[i], pws->w[i], 32, status)) {
2867 MSA_FLOAT_MAXOP(pwx->w[i], max, pwt->w[i], pwt->w[i], 32);
2868 } else {
2869 MSA_FLOAT_MAXOP(pwx->w[i], max, pws->w[i], pwt->w[i], 32);
2870 }
2871 }
2872 break;
2873 case DF_DOUBLE:
2874 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2875 if (NUMBER_QNAN_PAIR(pws->d[i], pwt->d[i], 64, status)) {
2876 MSA_FLOAT_MAXOP(pwx->d[i], max, pws->d[i], pws->d[i], 64);
2877 } else if (NUMBER_QNAN_PAIR(pwt->d[i], pws->d[i], 64, status)) {
2878 MSA_FLOAT_MAXOP(pwx->d[i], max, pwt->d[i], pwt->d[i], 64);
2879 } else {
2880 MSA_FLOAT_MAXOP(pwx->d[i], max, pws->d[i], pwt->d[i], 64);
2881 }
2882 }
2883 break;
2884 default:
2885 assert(0);
2886 }
2887
2888 check_msacsr_cause(env, GETPC());
2889
2890 msa_move_v(pwd, pwx);
2891 }
2892
2893 void helper_msa_fmax_a_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2894 uint32_t ws, uint32_t wt)
2895 {
2896 float_status *status = &env->active_tc.msa_fp_status;
2897 wr_t wx, *pwx = &wx;
2898 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2899 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2900 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2901 uint32_t i;
2902
2903 clear_msacsr_cause(env);
2904
2905 switch (df) {
2906 case DF_WORD:
2907 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2908 FMAXMIN_A(max, min, pwx->w[i], pws->w[i], pwt->w[i], 32, status);
2909 }
2910 break;
2911 case DF_DOUBLE:
2912 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2913 FMAXMIN_A(max, min, pwx->d[i], pws->d[i], pwt->d[i], 64, status);
2914 }
2915 break;
2916 default:
2917 assert(0);
2918 }
2919
2920 check_msacsr_cause(env, GETPC());
2921
2922 msa_move_v(pwd, pwx);
2923 }
2924
2925 void helper_msa_fclass_df(CPUMIPSState *env, uint32_t df,
2926 uint32_t wd, uint32_t ws)
2927 {
2928 float_status* status = &env->active_tc.msa_fp_status;
2929
2930 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2931 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2932 if (df == DF_WORD) {
2933 pwd->w[0] = float_class_s(pws->w[0], status);
2934 pwd->w[1] = float_class_s(pws->w[1], status);
2935 pwd->w[2] = float_class_s(pws->w[2], status);
2936 pwd->w[3] = float_class_s(pws->w[3], status);
2937 } else {
2938 pwd->d[0] = float_class_d(pws->d[0], status);
2939 pwd->d[1] = float_class_d(pws->d[1], status);
2940 }
2941 }
2942
2943 #define MSA_FLOAT_UNOP0(DEST, OP, ARG, BITS) \
2944 do { \
2945 float_status *status = &env->active_tc.msa_fp_status; \
2946 int c; \
2947 \
2948 set_float_exception_flags(0, status); \
2949 DEST = float ## BITS ## _ ## OP(ARG, status); \
2950 c = update_msacsr(env, CLEAR_FS_UNDERFLOW, 0); \
2951 \
2952 if (get_enabled_exceptions(env, c)) { \
2953 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
2954 } else if (float ## BITS ## _is_any_nan(ARG)) { \
2955 DEST = 0; \
2956 } \
2957 } while (0)
2958
2959 void helper_msa_ftrunc_s_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2960 uint32_t ws)
2961 {
2962 wr_t wx, *pwx = &wx;
2963 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2964 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2965 uint32_t i;
2966
2967 clear_msacsr_cause(env);
2968
2969 switch (df) {
2970 case DF_WORD:
2971 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2972 MSA_FLOAT_UNOP0(pwx->w[i], to_int32_round_to_zero, pws->w[i], 32);
2973 }
2974 break;
2975 case DF_DOUBLE:
2976 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2977 MSA_FLOAT_UNOP0(pwx->d[i], to_int64_round_to_zero, pws->d[i], 64);
2978 }
2979 break;
2980 default:
2981 assert(0);
2982 }
2983
2984 check_msacsr_cause(env, GETPC());
2985
2986 msa_move_v(pwd, pwx);
2987 }
2988
2989 void helper_msa_ftrunc_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2990 uint32_t ws)
2991 {
2992 wr_t wx, *pwx = &wx;
2993 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2994 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2995 uint32_t i;
2996
2997 clear_msacsr_cause(env);
2998
2999 switch (df) {
3000 case DF_WORD:
3001 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3002 MSA_FLOAT_UNOP0(pwx->w[i], to_uint32_round_to_zero, pws->w[i], 32);
3003 }
3004 break;
3005 case DF_DOUBLE:
3006 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3007 MSA_FLOAT_UNOP0(pwx->d[i], to_uint64_round_to_zero, pws->d[i], 64);
3008 }
3009 break;
3010 default:
3011 assert(0);
3012 }
3013
3014 check_msacsr_cause(env, GETPC());
3015
3016 msa_move_v(pwd, pwx);
3017 }
3018
3019 void helper_msa_fsqrt_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3020 uint32_t ws)
3021 {
3022 wr_t wx, *pwx = &wx;
3023 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3024 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3025 uint32_t i;
3026
3027 clear_msacsr_cause(env);
3028
3029 switch (df) {
3030 case DF_WORD:
3031 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3032 MSA_FLOAT_UNOP(pwx->w[i], sqrt, pws->w[i], 32);
3033 }
3034 break;
3035 case DF_DOUBLE:
3036 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3037 MSA_FLOAT_UNOP(pwx->d[i], sqrt, pws->d[i], 64);
3038 }
3039 break;
3040 default:
3041 assert(0);
3042 }
3043
3044 check_msacsr_cause(env, GETPC());
3045
3046 msa_move_v(pwd, pwx);
3047 }
3048
3049 #define MSA_FLOAT_RECIPROCAL(DEST, ARG, BITS) \
3050 do { \
3051 float_status *status = &env->active_tc.msa_fp_status; \
3052 int c; \
3053 \
3054 set_float_exception_flags(0, status); \
3055 DEST = float ## BITS ## _ ## div(FLOAT_ONE ## BITS, ARG, status); \
3056 c = update_msacsr(env, float ## BITS ## _is_infinity(ARG) || \
3057 float ## BITS ## _is_quiet_nan(DEST, status) ? \
3058 0 : RECIPROCAL_INEXACT, \
3059 IS_DENORMAL(DEST, BITS)); \
3060 \
3061 if (get_enabled_exceptions(env, c)) { \
3062 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
3063 } \
3064 } while (0)
3065
3066 void helper_msa_frsqrt_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3067 uint32_t ws)
3068 {
3069 wr_t wx, *pwx = &wx;
3070 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3071 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3072 uint32_t i;
3073
3074 clear_msacsr_cause(env);
3075
3076 switch (df) {
3077 case DF_WORD:
3078 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3079 MSA_FLOAT_RECIPROCAL(pwx->w[i], float32_sqrt(pws->w[i],
3080 &env->active_tc.msa_fp_status), 32);
3081 }
3082 break;
3083 case DF_DOUBLE:
3084 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3085 MSA_FLOAT_RECIPROCAL(pwx->d[i], float64_sqrt(pws->d[i],
3086 &env->active_tc.msa_fp_status), 64);
3087 }
3088 break;
3089 default:
3090 assert(0);
3091 }
3092
3093 check_msacsr_cause(env, GETPC());
3094
3095 msa_move_v(pwd, pwx);
3096 }
3097
3098 void helper_msa_frcp_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3099 uint32_t ws)
3100 {
3101 wr_t wx, *pwx = &wx;
3102 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3103 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3104 uint32_t i;
3105
3106 clear_msacsr_cause(env);
3107
3108 switch (df) {
3109 case DF_WORD:
3110 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3111 MSA_FLOAT_RECIPROCAL(pwx->w[i], pws->w[i], 32);
3112 }
3113 break;
3114 case DF_DOUBLE:
3115 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3116 MSA_FLOAT_RECIPROCAL(pwx->d[i], pws->d[i], 64);
3117 }
3118 break;
3119 default:
3120 assert(0);
3121 }
3122
3123 check_msacsr_cause(env, GETPC());
3124
3125 msa_move_v(pwd, pwx);
3126 }
3127
3128 void helper_msa_frint_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3129 uint32_t ws)
3130 {
3131 wr_t wx, *pwx = &wx;
3132 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3133 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3134 uint32_t i;
3135
3136 clear_msacsr_cause(env);
3137
3138 switch (df) {
3139 case DF_WORD:
3140 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3141 MSA_FLOAT_UNOP(pwx->w[i], round_to_int, pws->w[i], 32);
3142 }
3143 break;
3144 case DF_DOUBLE:
3145 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3146 MSA_FLOAT_UNOP(pwx->d[i], round_to_int, pws->d[i], 64);
3147 }
3148 break;
3149 default:
3150 assert(0);
3151 }
3152
3153 check_msacsr_cause(env, GETPC());
3154
3155 msa_move_v(pwd, pwx);
3156 }
3157
3158 #define MSA_FLOAT_LOGB(DEST, ARG, BITS) \
3159 do { \
3160 float_status *status = &env->active_tc.msa_fp_status; \
3161 int c; \
3162 \
3163 set_float_exception_flags(0, status); \
3164 set_float_rounding_mode(float_round_down, status); \
3165 DEST = float ## BITS ## _ ## log2(ARG, status); \
3166 DEST = float ## BITS ## _ ## round_to_int(DEST, status); \
3167 set_float_rounding_mode(ieee_rm[(env->active_tc.msacsr & \
3168 MSACSR_RM_MASK) >> MSACSR_RM], \
3169 status); \
3170 \
3171 set_float_exception_flags(get_float_exception_flags(status) & \
3172 (~float_flag_inexact), \
3173 status); \
3174 \
3175 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
3176 \
3177 if (get_enabled_exceptions(env, c)) { \
3178 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
3179 } \
3180 } while (0)
3181
3182 void helper_msa_flog2_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3183 uint32_t ws)
3184 {
3185 wr_t wx, *pwx = &wx;
3186 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3187 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3188 uint32_t i;
3189
3190 clear_msacsr_cause(env);
3191
3192 switch (df) {
3193 case DF_WORD:
3194 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3195 MSA_FLOAT_LOGB(pwx->w[i], pws->w[i], 32);
3196 }
3197 break;
3198 case DF_DOUBLE:
3199 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3200 MSA_FLOAT_LOGB(pwx->d[i], pws->d[i], 64);
3201 }
3202 break;
3203 default:
3204 assert(0);
3205 }
3206
3207 check_msacsr_cause(env, GETPC());
3208
3209 msa_move_v(pwd, pwx);
3210 }
3211
3212 void helper_msa_fexupl_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3213 uint32_t ws)
3214 {
3215 wr_t wx, *pwx = &wx;
3216 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3217 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3218 uint32_t i;
3219
3220 clear_msacsr_cause(env);
3221
3222 switch (df) {
3223 case DF_WORD:
3224 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3225 /* Half precision floats come in two formats: standard
3226 IEEE and "ARM" format. The latter gains extra exponent
3227 range by omitting the NaN/Inf encodings. */
3228 flag ieee = 1;
3229
3230 MSA_FLOAT_BINOP(pwx->w[i], from_float16, Lh(pws, i), ieee, 32);
3231 }
3232 break;
3233 case DF_DOUBLE:
3234 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3235 MSA_FLOAT_UNOP(pwx->d[i], from_float32, Lw(pws, i), 64);
3236 }
3237 break;
3238 default:
3239 assert(0);
3240 }
3241
3242 check_msacsr_cause(env, GETPC());
3243 msa_move_v(pwd, pwx);
3244 }
3245
3246 void helper_msa_fexupr_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3247 uint32_t ws)
3248 {
3249 wr_t wx, *pwx = &wx;
3250 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3251 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3252 uint32_t i;
3253
3254 clear_msacsr_cause(env);
3255
3256 switch (df) {
3257 case DF_WORD:
3258 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3259 /* Half precision floats come in two formats: standard
3260 IEEE and "ARM" format. The latter gains extra exponent
3261 range by omitting the NaN/Inf encodings. */
3262 flag ieee = 1;
3263
3264 MSA_FLOAT_BINOP(pwx->w[i], from_float16, Rh(pws, i), ieee, 32);
3265 }
3266 break;
3267 case DF_DOUBLE:
3268 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3269 MSA_FLOAT_UNOP(pwx->d[i], from_float32, Rw(pws, i), 64);
3270 }
3271 break;
3272 default:
3273 assert(0);
3274 }
3275
3276 check_msacsr_cause(env, GETPC());
3277 msa_move_v(pwd, pwx);
3278 }
3279
3280 void helper_msa_ffql_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3281 uint32_t ws)
3282 {
3283 wr_t wx, *pwx = &wx;
3284 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3285 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3286 uint32_t i;
3287
3288 switch (df) {
3289 case DF_WORD:
3290 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3291 MSA_FLOAT_UNOP(pwx->w[i], from_q16, Lh(pws, i), 32);
3292 }
3293 break;
3294 case DF_DOUBLE:
3295 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3296 MSA_FLOAT_UNOP(pwx->d[i], from_q32, Lw(pws, i), 64);
3297 }
3298 break;
3299 default:
3300 assert(0);
3301 }
3302
3303 msa_move_v(pwd, pwx);
3304 }
3305
3306 void helper_msa_ffqr_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3307 uint32_t ws)
3308 {
3309 wr_t wx, *pwx = &wx;
3310 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3311 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3312 uint32_t i;
3313
3314 switch (df) {
3315 case DF_WORD:
3316 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3317 MSA_FLOAT_UNOP(pwx->w[i], from_q16, Rh(pws, i), 32);
3318 }
3319 break;
3320 case DF_DOUBLE:
3321 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3322 MSA_FLOAT_UNOP(pwx->d[i], from_q32, Rw(pws, i), 64);
3323 }
3324 break;
3325 default:
3326 assert(0);
3327 }
3328
3329 msa_move_v(pwd, pwx);
3330 }
3331
3332 void helper_msa_ftint_s_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3333 uint32_t ws)
3334 {
3335 wr_t wx, *pwx = &wx;
3336 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3337 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3338 uint32_t i;
3339
3340 clear_msacsr_cause(env);
3341
3342 switch (df) {
3343 case DF_WORD:
3344 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3345 MSA_FLOAT_UNOP0(pwx->w[i], to_int32, pws->w[i], 32);
3346 }
3347 break;
3348 case DF_DOUBLE:
3349 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3350 MSA_FLOAT_UNOP0(pwx->d[i], to_int64, pws->d[i], 64);
3351 }
3352 break;
3353 default:
3354 assert(0);
3355 }
3356
3357 check_msacsr_cause(env, GETPC());
3358
3359 msa_move_v(pwd, pwx);
3360 }
3361
3362 void helper_msa_ftint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3363 uint32_t ws)
3364 {
3365 wr_t wx, *pwx = &wx;
3366 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3367 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3368 uint32_t i;
3369
3370 clear_msacsr_cause(env);
3371
3372 switch (df) {
3373 case DF_WORD:
3374 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3375 MSA_FLOAT_UNOP0(pwx->w[i], to_uint32, pws->w[i], 32);
3376 }
3377 break;
3378 case DF_DOUBLE:
3379 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3380 MSA_FLOAT_UNOP0(pwx->d[i], to_uint64, pws->d[i], 64);
3381 }
3382 break;
3383 default:
3384 assert(0);
3385 }
3386
3387 check_msacsr_cause(env, GETPC());
3388
3389 msa_move_v(pwd, pwx);
3390 }
3391
3392 #define float32_from_int32 int32_to_float32
3393 #define float32_from_uint32 uint32_to_float32
3394
3395 #define float64_from_int64 int64_to_float64
3396 #define float64_from_uint64 uint64_to_float64
3397
3398 void helper_msa_ffint_s_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3399 uint32_t ws)
3400 {
3401 wr_t wx, *pwx = &wx;
3402 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3403 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3404 uint32_t i;
3405
3406 clear_msacsr_cause(env);
3407
3408 switch (df) {
3409 case DF_WORD:
3410 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3411 MSA_FLOAT_UNOP(pwx->w[i], from_int32, pws->w[i], 32);
3412 }
3413 break;
3414 case DF_DOUBLE:
3415 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3416 MSA_FLOAT_UNOP(pwx->d[i], from_int64, pws->d[i], 64);
3417 }
3418 break;
3419 default:
3420 assert(0);
3421 }
3422
3423 check_msacsr_cause(env, GETPC());
3424
3425 msa_move_v(pwd, pwx);
3426 }
3427
3428 void helper_msa_ffint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3429 uint32_t ws)
3430 {
3431 wr_t wx, *pwx = &wx;
3432 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3433 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3434 uint32_t i;
3435
3436 clear_msacsr_cause(env);
3437
3438 switch (df) {
3439 case DF_WORD:
3440 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3441 MSA_FLOAT_UNOP(pwx->w[i], from_uint32, pws->w[i], 32);
3442 }
3443 break;
3444 case DF_DOUBLE:
3445 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3446 MSA_FLOAT_UNOP(pwx->d[i], from_uint64, pws->d[i], 64);
3447 }
3448 break;
3449 default:
3450 assert(0);
3451 }
3452
3453 check_msacsr_cause(env, GETPC());
3454
3455 msa_move_v(pwd, pwx);
3456 }
AR7 emulation for QEMU