target/riscv/cpu.c

   1 /*
   2  * QEMU RISC-V CPU
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2017-2018 SiFive, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2 or later, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu/qemu-print.h"
  22 #include "qemu/ctype.h"
  23 #include "qemu/log.h"
  24 #include "cpu.h"
  25 #include "exec/exec-all.h"
  26 #include "qapi/error.h"
  27 #include "qemu/error-report.h"
  28 #include "hw/qdev-properties.h"
  29 #include "migration/vmstate.h"
  30 #include "fpu/softfloat-helpers.h"
  31
  32 /* RISC-V CPU definitions */
  33
  34 static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
  35
  36 const char * const riscv_int_regnames[] = {
  37   "x0/zero", "x1/ra",  "x2/sp",  "x3/gp",  "x4/tp",  "x5/t0",   "x6/t1",
  38   "x7/t2",   "x8/s0",  "x9/s1",  "x10/a0", "x11/a1", "x12/a2",  "x13/a3",
  39   "x14/a4",  "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3",  "x20/s4",
  40   "x21/s5",  "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11",
  41   "x28/t3",  "x29/t4", "x30/t5", "x31/t6"
  42 };
  43
  44 const char * const riscv_fpr_regnames[] = {
  45   "f0/ft0",   "f1/ft1",  "f2/ft2",   "f3/ft3",   "f4/ft4",  "f5/ft5",
  46   "f6/ft6",   "f7/ft7",  "f8/fs0",   "f9/fs1",   "f10/fa0", "f11/fa1",
  47   "f12/fa2",  "f13/fa3", "f14/fa4",  "f15/fa5",  "f16/fa6", "f17/fa7",
  48   "f18/fs2",  "f19/fs3", "f20/fs4",  "f21/fs5",  "f22/fs6", "f23/fs7",
  49   "f24/fs8",  "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9",
  50   "f30/ft10", "f31/ft11"
  51 };
  52
  53 const char * const riscv_excp_names[] = {
  54     "misaligned_fetch",
  55     "fault_fetch",
  56     "illegal_instruction",
  57     "breakpoint",
  58     "misaligned_load",
  59     "fault_load",
  60     "misaligned_store",
  61     "fault_store",
  62     "user_ecall",
  63     "supervisor_ecall",
  64     "hypervisor_ecall",
  65     "machine_ecall",
  66     "exec_page_fault",
  67     "load_page_fault",
  68     "reserved",
  69     "store_page_fault",
  70     "reserved",
  71     "reserved",
  72     "reserved",
  73     "reserved",
  74     "guest_exec_page_fault",
  75     "guest_load_page_fault",
  76     "reserved",
  77     "guest_store_page_fault",
  78 };
  79
  80 const char * const riscv_intr_names[] = {
  81     "u_software",
  82     "s_software",
  83     "vs_software",
  84     "m_software",
  85     "u_timer",
  86     "s_timer",
  87     "vs_timer",
  88     "m_timer",
  89     "u_external",
  90     "vs_external",
  91     "h_external",
  92     "m_external",
  93     "reserved",
  94     "reserved",
  95     "reserved",
  96     "reserved"
  97 };
  98
  99 static void set_misa(CPURISCVState *env, target_ulong misa)
 100 {
 101     env->misa_mask = env->misa = misa;
 102 }
 103
 104 static void set_priv_version(CPURISCVState *env, int priv_ver)
 105 {
 106     env->priv_ver = priv_ver;
 107 }
 108
 109 static void set_feature(CPURISCVState *env, int feature)
 110 {
 111     env->features |= (1ULL << feature);
 112 }
 113
 114 static void set_resetvec(CPURISCVState *env, int resetvec)
 115 {
 116 #ifndef CONFIG_USER_ONLY
 117     env->resetvec = resetvec;
 118 #endif
 119 }
 120
 121 static void riscv_any_cpu_init(Object *obj)
 122 {
 123     CPURISCVState *env = &RISCV_CPU(obj)->env;
 124     set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
 125     set_priv_version(env, PRIV_VERSION_1_11_0);
 126     set_resetvec(env, DEFAULT_RSTVEC);
 127 }
 128
 129 #if defined(TARGET_RISCV32)
 130
 131 static void riscv_base32_cpu_init(Object *obj)
 132 {
 133     CPURISCVState *env = &RISCV_CPU(obj)->env;
 134     /* We set this in the realise function */
 135     set_misa(env, 0);
 136     set_resetvec(env, DEFAULT_RSTVEC);
 137 }
 138
 139 static void rv32gcsu_priv1_10_0_cpu_init(Object *obj)
 140 {
 141     CPURISCVState *env = &RISCV_CPU(obj)->env;
 142     set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
 143     set_priv_version(env, PRIV_VERSION_1_10_0);
 144     set_resetvec(env, DEFAULT_RSTVEC);
 145 }
 146
 147 static void rv32imacu_nommu_cpu_init(Object *obj)
 148 {
 149     CPURISCVState *env = &RISCV_CPU(obj)->env;
 150     set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU);
 151     set_priv_version(env, PRIV_VERSION_1_10_0);
 152     set_resetvec(env, DEFAULT_RSTVEC);
 153     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 154 }
 155
 156 static void rv32imafcu_nommu_cpu_init(Object *obj)
 157 {
 158     CPURISCVState *env = &RISCV_CPU(obj)->env;
 159     set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU);
 160     set_priv_version(env, PRIV_VERSION_1_10_0);
 161     set_resetvec(env, DEFAULT_RSTVEC);
 162     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 163 }
 164
 165 #elif defined(TARGET_RISCV64)
 166
 167 static void riscv_base64_cpu_init(Object *obj)
 168 {
 169     CPURISCVState *env = &RISCV_CPU(obj)->env;
 170     /* We set this in the realise function */
 171     set_misa(env, 0);
 172     set_resetvec(env, DEFAULT_RSTVEC);
 173 }
 174
 175 static void rv64gcsu_priv1_10_0_cpu_init(Object *obj)
 176 {
 177     CPURISCVState *env = &RISCV_CPU(obj)->env;
 178     set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
 179     set_priv_version(env, PRIV_VERSION_1_10_0);
 180     set_resetvec(env, DEFAULT_RSTVEC);
 181 }
 182
 183 static void rv64imacu_nommu_cpu_init(Object *obj)
 184 {
 185     CPURISCVState *env = &RISCV_CPU(obj)->env;
 186     set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);
 187     set_priv_version(env, PRIV_VERSION_1_10_0);
 188     set_resetvec(env, DEFAULT_RSTVEC);
 189     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 190 }
 191
 192 #endif
 193
 194 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
 195 {
 196     ObjectClass *oc;
 197     char *typename;
 198     char **cpuname;
 199
 200     cpuname = g_strsplit(cpu_model, ",", 1);
 201     typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]);
 202     oc = object_class_by_name(typename);
 203     g_strfreev(cpuname);
 204     g_free(typename);
 205     if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) ||
 206         object_class_is_abstract(oc)) {
 207         return NULL;
 208     }
 209     return oc;
 210 }
 211
 212 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 213 {
 214     RISCVCPU *cpu = RISCV_CPU(cs);
 215     CPURISCVState *env = &cpu->env;
 216     int i;
 217
 218 #if !defined(CONFIG_USER_ONLY)
 219     if (riscv_has_ext(env, RVH)) {
 220         qemu_fprintf(f, " %s %d\n", "V      =  ", riscv_cpu_virt_enabled(env));
 221     }
 222 #endif
 223     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc      ", env->pc);
 224 #ifndef CONFIG_USER_ONLY
 225     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
 226     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus);
 227 #ifdef TARGET_RISCV32
 228     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", env->mstatush);
 229 #endif
 230     if (riscv_has_ext(env, RVH)) {
 231         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus);
 232         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ", env->vsstatus);
 233     }
 234     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip     ", env->mip);
 235     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie     ", env->mie);
 236     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg);
 237     if (riscv_has_ext(env, RVH)) {
 238         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg);
 239     }
 240     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg);
 241     if (riscv_has_ext(env, RVH)) {
 242         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hedeleg ", env->hedeleg);
 243     }
 244     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec   ", env->mtvec);
 245     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec   ", env->stvec);
 246     if (riscv_has_ext(env, RVH)) {
 247         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vstvec  ", env->vstvec);
 248     }
 249     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc    ", env->mepc);
 250     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sepc    ", env->sepc);
 251     if (riscv_has_ext(env, RVH)) {
 252         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsepc   ", env->vsepc);
 253     }
 254     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause  ", env->mcause);
 255     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scause  ", env->scause);
 256     if (riscv_has_ext(env, RVH)) {
 257         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause);
 258     }
 259     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval);
 260     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->sbadaddr);
 261     if (riscv_has_ext(env, RVH)) {
 262         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval);
 263         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2);
 264     }
 265 #endif
 266
 267     for (i = 0; i < 32; i++) {
 268         qemu_fprintf(f, " %s " TARGET_FMT_lx,
 269                      riscv_int_regnames[i], env->gpr[i]);
 270         if ((i & 3) == 3) {
 271             qemu_fprintf(f, "\n");
 272         }
 273     }
 274     if (flags & CPU_DUMP_FPU) {
 275         for (i = 0; i < 32; i++) {
 276             qemu_fprintf(f, " %s %016" PRIx64,
 277                          riscv_fpr_regnames[i], env->fpr[i]);
 278             if ((i & 3) == 3) {
 279                 qemu_fprintf(f, "\n");
 280             }
 281         }
 282     }
 283 }
 284
 285 static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
 286 {
 287     RISCVCPU *cpu = RISCV_CPU(cs);
 288     CPURISCVState *env = &cpu->env;
 289     env->pc = value;
 290 }
 291
 292 static void riscv_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
 293 {
 294     RISCVCPU *cpu = RISCV_CPU(cs);
 295     CPURISCVState *env = &cpu->env;
 296     env->pc = tb->pc;
 297 }
 298
 299 static bool riscv_cpu_has_work(CPUState *cs)
 300 {
 301 #ifndef CONFIG_USER_ONLY
 302     RISCVCPU *cpu = RISCV_CPU(cs);
 303     CPURISCVState *env = &cpu->env;
 304     /*
 305      * Definition of the WFI instruction requires it to ignore the privilege
 306      * mode and delegation registers, but respect individual enables
 307      */
 308     return (env->mip & env->mie) != 0;
 309 #else
 310     return true;
 311 #endif
 312 }
 313
 314 void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb,
 315                           target_ulong *data)
 316 {
 317     env->pc = data[0];
 318 }
 319
 320 static void riscv_cpu_reset(DeviceState *dev)
 321 {
 322     CPUState *cs = CPU(dev);
 323     RISCVCPU *cpu = RISCV_CPU(cs);
 324     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
 325     CPURISCVState *env = &cpu->env;
 326
 327     mcc->parent_reset(dev);
 328 #ifndef CONFIG_USER_ONLY
 329     env->priv = PRV_M;
 330     env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
 331     env->mcause = 0;
 332     env->pc = env->resetvec;
 333 #endif
 334     cs->exception_index = EXCP_NONE;
 335     env->load_res = -1;
 336     set_default_nan_mode(1, &env->fp_status);
 337 }
 338
 339 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
 340 {
 341 #if defined(TARGET_RISCV32)
 342     info->print_insn = print_insn_riscv32;
 343 #elif defined(TARGET_RISCV64)
 344     info->print_insn = print_insn_riscv64;
 345 #endif
 346 }
 347
 348 static void riscv_cpu_realize(DeviceState *dev, Error **errp)
 349 {
 350     CPUState *cs = CPU(dev);
 351     RISCVCPU *cpu = RISCV_CPU(dev);
 352     CPURISCVState *env = &cpu->env;
 353     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
 354     int priv_version = PRIV_VERSION_1_11_0;
 355     target_ulong target_misa = 0;
 356     Error *local_err = NULL;
 357
 358     cpu_exec_realizefn(cs, &local_err);
 359     if (local_err != NULL) {
 360         error_propagate(errp, local_err);
 361         return;
 362     }
 363
 364     if (cpu->cfg.priv_spec) {
 365         if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
 366             priv_version = PRIV_VERSION_1_11_0;
 367         } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
 368             priv_version = PRIV_VERSION_1_10_0;
 369         } else {
 370             error_setg(errp,
 371                        "Unsupported privilege spec version '%s'",
 372                        cpu->cfg.priv_spec);
 373             return;
 374         }
 375     }
 376
 377     set_priv_version(env, priv_version);
 378
 379     if (cpu->cfg.mmu) {
 380         set_feature(env, RISCV_FEATURE_MMU);
 381     }
 382
 383     if (cpu->cfg.pmp) {
 384         set_feature(env, RISCV_FEATURE_PMP);
 385     }
 386
 387     /* If misa isn't set (rv32 and rv64 machines) set it here */
 388     if (!env->misa) {
 389         /* Do some ISA extension error checking */
 390         if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
 391             error_setg(errp,
 392                        "I and E extensions are incompatible");
 393                        return;
 394        }
 395
 396         if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
 397             error_setg(errp,
 398                        "Either I or E extension must be set");
 399                        return;
 400        }
 401
 402        if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
 403                                cpu->cfg.ext_a & cpu->cfg.ext_f &
 404                                cpu->cfg.ext_d)) {
 405             warn_report("Setting G will also set IMAFD");
 406             cpu->cfg.ext_i = true;
 407             cpu->cfg.ext_m = true;
 408             cpu->cfg.ext_a = true;
 409             cpu->cfg.ext_f = true;
 410             cpu->cfg.ext_d = true;
 411         }
 412
 413         /* Set the ISA extensions, checks should have happened above */
 414         if (cpu->cfg.ext_i) {
 415             target_misa |= RVI;
 416         }
 417         if (cpu->cfg.ext_e) {
 418             target_misa |= RVE;
 419         }
 420         if (cpu->cfg.ext_m) {
 421             target_misa |= RVM;
 422         }
 423         if (cpu->cfg.ext_a) {
 424             target_misa |= RVA;
 425         }
 426         if (cpu->cfg.ext_f) {
 427             target_misa |= RVF;
 428         }
 429         if (cpu->cfg.ext_d) {
 430             target_misa |= RVD;
 431         }
 432         if (cpu->cfg.ext_c) {
 433             target_misa |= RVC;
 434         }
 435         if (cpu->cfg.ext_s) {
 436             target_misa |= RVS;
 437         }
 438         if (cpu->cfg.ext_u) {
 439             target_misa |= RVU;
 440         }
 441         if (cpu->cfg.ext_h) {
 442             target_misa |= RVH;
 443         }
 444
 445         set_misa(env, RVXLEN | target_misa);
 446     }
 447
 448     riscv_cpu_register_gdb_regs_for_features(cs);
 449
 450     qemu_init_vcpu(cs);
 451     cpu_reset(cs);
 452
 453     mcc->parent_realize(dev, errp);
 454 }
 455
 456 static void riscv_cpu_init(Object *obj)
 457 {
 458     RISCVCPU *cpu = RISCV_CPU(obj);
 459
 460     cpu_set_cpustate_pointers(cpu);
 461 }
 462
 463 static const VMStateDescription vmstate_riscv_cpu = {
 464     .name = "cpu",
 465     .unmigratable = 1,
 466 };
 467
 468 static Property riscv_cpu_properties[] = {
 469     DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
 470     DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
 471     DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true),
 472     DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
 473     DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true),
 474     DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true),
 475     DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true),
 476     DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
 477     DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
 478     DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
 479     /* This is experimental so mark with 'x-' */
 480     DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
 481     DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
 482     DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
 483     DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
 484     DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
 485     DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
 486     DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
 487     DEFINE_PROP_END_OF_LIST(),
 488 };
 489
 490 static void riscv_cpu_class_init(ObjectClass *c, void *data)
 491 {
 492     RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
 493     CPUClass *cc = CPU_CLASS(c);
 494     DeviceClass *dc = DEVICE_CLASS(c);
 495
 496     device_class_set_parent_realize(dc, riscv_cpu_realize,
 497                                     &mcc->parent_realize);
 498
 499     device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset);
 500
 501     cc->class_by_name = riscv_cpu_class_by_name;
 502     cc->has_work = riscv_cpu_has_work;
 503     cc->do_interrupt = riscv_cpu_do_interrupt;
 504     cc->cpu_exec_interrupt = riscv_cpu_exec_interrupt;
 505     cc->dump_state = riscv_cpu_dump_state;
 506     cc->set_pc = riscv_cpu_set_pc;
 507     cc->synchronize_from_tb = riscv_cpu_synchronize_from_tb;
 508     cc->gdb_read_register = riscv_cpu_gdb_read_register;
 509     cc->gdb_write_register = riscv_cpu_gdb_write_register;
 510     cc->gdb_num_core_regs = 33;
 511 #if defined(TARGET_RISCV32)
 512     cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
 513 #elif defined(TARGET_RISCV64)
 514     cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
 515 #endif
 516     cc->gdb_stop_before_watchpoint = true;
 517     cc->disas_set_info = riscv_cpu_disas_set_info;
 518 #ifndef CONFIG_USER_ONLY
 519     cc->do_transaction_failed = riscv_cpu_do_transaction_failed;
 520     cc->do_unaligned_access = riscv_cpu_do_unaligned_access;
 521     cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
 522 #endif
 523 #ifdef CONFIG_TCG
 524     cc->tcg_initialize = riscv_translate_init;
 525     cc->tlb_fill = riscv_cpu_tlb_fill;
 526 #endif
 527     /* For now, mark unmigratable: */
 528     cc->vmsd = &vmstate_riscv_cpu;
 529     device_class_set_props(dc, riscv_cpu_properties);
 530 }
 531
 532 char *riscv_isa_string(RISCVCPU *cpu)
 533 {
 534     int i;
 535     const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1;
 536     char *isa_str = g_new(char, maxlen);
 537     char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
 538     for (i = 0; i < sizeof(riscv_exts); i++) {
 539         if (cpu->env.misa & RV(riscv_exts[i])) {
 540             *p++ = qemu_tolower(riscv_exts[i]);
 541         }
 542     }
 543     *p = '\0';
 544     return isa_str;
 545 }
 546
 547 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b)
 548 {
 549     ObjectClass *class_a = (ObjectClass *)a;
 550     ObjectClass *class_b = (ObjectClass *)b;
 551     const char *name_a, *name_b;
 552
 553     name_a = object_class_get_name(class_a);
 554     name_b = object_class_get_name(class_b);
 555     return strcmp(name_a, name_b);
 556 }
 557
 558 static void riscv_cpu_list_entry(gpointer data, gpointer user_data)
 559 {
 560     const char *typename = object_class_get_name(OBJECT_CLASS(data));
 561     int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX);
 562
 563     qemu_printf("%.*s\n", len, typename);
 564 }
 565
 566 void riscv_cpu_list(void)
 567 {
 568     GSList *list;
 569
 570     list = object_class_get_list(TYPE_RISCV_CPU, false);
 571     list = g_slist_sort(list, riscv_cpu_list_compare);
 572     g_slist_foreach(list, riscv_cpu_list_entry, NULL);
 573     g_slist_free(list);
 574 }
 575
 576 #define DEFINE_CPU(type_name, initfn)      \
 577     {                                      \
 578         .name = type_name,                 \
 579         .parent = TYPE_RISCV_CPU,          \
 580         .instance_init = initfn            \
 581     }
 582
 583 static const TypeInfo riscv_cpu_type_infos[] = {
 584     {
 585         .name = TYPE_RISCV_CPU,
 586         .parent = TYPE_CPU,
 587         .instance_size = sizeof(RISCVCPU),
 588         .instance_init = riscv_cpu_init,
 589         .abstract = true,
 590         .class_size = sizeof(RISCVCPUClass),
 591         .class_init = riscv_cpu_class_init,
 592     },
 593     DEFINE_CPU(TYPE_RISCV_CPU_ANY,              riscv_any_cpu_init),
 594 #if defined(TARGET_RISCV32)
 595     DEFINE_CPU(TYPE_RISCV_CPU_BASE32,           riscv_base32_cpu_init),
 596     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31,       rv32imacu_nommu_cpu_init),
 597     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34,       rv32imafcu_nommu_cpu_init),
 598     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34,       rv32gcsu_priv1_10_0_cpu_init),
 599 #elif defined(TARGET_RISCV64)
 600     DEFINE_CPU(TYPE_RISCV_CPU_BASE64,           riscv_base64_cpu_init),
 601     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51,       rv64imacu_nommu_cpu_init),
 602     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,       rv64gcsu_priv1_10_0_cpu_init),
 603 #endif
 604 };
 605
 606 DEFINE_TYPES(riscv_cpu_type_infos)