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s390x/tcg: Implement VECTOR COMPARE *
[qemu/ar7.git] / tcg / ppc / tcg-target.inc.c
blob30c095d3d53b8cdcd385f16677594a881236afa1
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "elf.h"
26 #include "tcg-pool.inc.c"
27
28 #if defined _CALL_DARWIN || defined __APPLE__
29 #define TCG_TARGET_CALL_DARWIN
30 #endif
31 #ifdef _CALL_SYSV
32 # define TCG_TARGET_CALL_ALIGN_ARGS 1
33 #endif
34
35 /* For some memory operations, we need a scratch that isn't R0. For the AIX
36 calling convention, we can re-use the TOC register since we'll be reloading
37 it at every call. Otherwise R12 will do nicely as neither a call-saved
38 register nor a parameter register. */
39 #ifdef _CALL_AIX
40 # define TCG_REG_TMP1 TCG_REG_R2
41 #else
42 # define TCG_REG_TMP1 TCG_REG_R12
43 #endif
44
45 #define TCG_REG_TB TCG_REG_R31
46 #define USE_REG_TB (TCG_TARGET_REG_BITS == 64)
47
48 /* Shorthand for size of a pointer. Avoid promotion to unsigned. */
49 #define SZP ((int)sizeof(void *))
50
51 /* Shorthand for size of a register. */
52 #define SZR (TCG_TARGET_REG_BITS / 8)
53
54 #define TCG_CT_CONST_S16 0x100
55 #define TCG_CT_CONST_U16 0x200
56 #define TCG_CT_CONST_S32 0x400
57 #define TCG_CT_CONST_U32 0x800
58 #define TCG_CT_CONST_ZERO 0x1000
59 #define TCG_CT_CONST_MONE 0x2000
60 #define TCG_CT_CONST_WSZ 0x4000
61
62 static tcg_insn_unit *tb_ret_addr;
63
64 bool have_isa_2_06;
65 bool have_isa_3_00;
66
67 #define HAVE_ISA_2_06 have_isa_2_06
68 #define HAVE_ISEL have_isa_2_06
69
70 #ifndef CONFIG_SOFTMMU
71 #define TCG_GUEST_BASE_REG 30
72 #endif
73
74 #ifdef CONFIG_DEBUG_TCG
75 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
76 "r0",
77 "r1",
78 "r2",
79 "r3",
80 "r4",
81 "r5",
82 "r6",
83 "r7",
84 "r8",
85 "r9",
86 "r10",
87 "r11",
88 "r12",
89 "r13",
90 "r14",
91 "r15",
92 "r16",
93 "r17",
94 "r18",
95 "r19",
96 "r20",
97 "r21",
98 "r22",
99 "r23",
100 "r24",
101 "r25",
102 "r26",
103 "r27",
104 "r28",
105 "r29",
106 "r30",
107 "r31"
108 };
109 #endif
110
111 static const int tcg_target_reg_alloc_order[] = {
112 TCG_REG_R14, /* call saved registers */
113 TCG_REG_R15,
114 TCG_REG_R16,
115 TCG_REG_R17,
116 TCG_REG_R18,
117 TCG_REG_R19,
118 TCG_REG_R20,
119 TCG_REG_R21,
120 TCG_REG_R22,
121 TCG_REG_R23,
122 TCG_REG_R24,
123 TCG_REG_R25,
124 TCG_REG_R26,
125 TCG_REG_R27,
126 TCG_REG_R28,
127 TCG_REG_R29,
128 TCG_REG_R30,
129 TCG_REG_R31,
130 TCG_REG_R12, /* call clobbered, non-arguments */
131 TCG_REG_R11,
132 TCG_REG_R2,
133 TCG_REG_R13,
134 TCG_REG_R10, /* call clobbered, arguments */
135 TCG_REG_R9,
136 TCG_REG_R8,
137 TCG_REG_R7,
138 TCG_REG_R6,
139 TCG_REG_R5,
140 TCG_REG_R4,
141 TCG_REG_R3,
142 };
143
144 static const int tcg_target_call_iarg_regs[] = {
145 TCG_REG_R3,
146 TCG_REG_R4,
147 TCG_REG_R5,
148 TCG_REG_R6,
149 TCG_REG_R7,
150 TCG_REG_R8,
151 TCG_REG_R9,
152 TCG_REG_R10
153 };
154
155 static const int tcg_target_call_oarg_regs[] = {
156 TCG_REG_R3,
157 TCG_REG_R4
158 };
159
160 static const int tcg_target_callee_save_regs[] = {
161 #ifdef TCG_TARGET_CALL_DARWIN
162 TCG_REG_R11,
163 #endif
164 TCG_REG_R14,
165 TCG_REG_R15,
166 TCG_REG_R16,
167 TCG_REG_R17,
168 TCG_REG_R18,
169 TCG_REG_R19,
170 TCG_REG_R20,
171 TCG_REG_R21,
172 TCG_REG_R22,
173 TCG_REG_R23,
174 TCG_REG_R24,
175 TCG_REG_R25,
176 TCG_REG_R26,
177 TCG_REG_R27, /* currently used for the global env */
178 TCG_REG_R28,
179 TCG_REG_R29,
180 TCG_REG_R30,
181 TCG_REG_R31
182 };
183
184 static inline bool in_range_b(tcg_target_long target)
185 {
186 return target == sextract64(target, 0, 26);
187 }
188
189 static uint32_t reloc_pc24_val(tcg_insn_unit *pc, tcg_insn_unit *target)
190 {
191 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
192 tcg_debug_assert(in_range_b(disp));
193 return disp & 0x3fffffc;
194 }
195
196 static bool reloc_pc24(tcg_insn_unit *pc, tcg_insn_unit *target)
197 {
198 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
199 if (in_range_b(disp)) {
200 *pc = (*pc & ~0x3fffffc) | (disp & 0x3fffffc);
201 return true;
202 }
203 return false;
204 }
205
206 static uint16_t reloc_pc14_val(tcg_insn_unit *pc, tcg_insn_unit *target)
207 {
208 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
209 tcg_debug_assert(disp == (int16_t) disp);
210 return disp & 0xfffc;
211 }
212
213 static bool reloc_pc14(tcg_insn_unit *pc, tcg_insn_unit *target)
214 {
215 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
216 if (disp == (int16_t) disp) {
217 *pc = (*pc & ~0xfffc) | (disp & 0xfffc);
218 return true;
219 }
220 return false;
221 }
222
223 /* parse target specific constraints */
224 static const char *target_parse_constraint(TCGArgConstraint *ct,
225 const char *ct_str, TCGType type)
226 {
227 switch (*ct_str++) {
228 case 'A': case 'B': case 'C': case 'D':
229 ct->ct |= TCG_CT_REG;
230 tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');
231 break;
232 case 'r':
233 ct->ct |= TCG_CT_REG;
234 ct->u.regs = 0xffffffff;
235 break;
236 case 'L': /* qemu_ld constraint */
237 ct->ct |= TCG_CT_REG;
238 ct->u.regs = 0xffffffff;
239 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
240 #ifdef CONFIG_SOFTMMU
241 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
242 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
243 #endif
244 break;
245 case 'S': /* qemu_st constraint */
246 ct->ct |= TCG_CT_REG;
247 ct->u.regs = 0xffffffff;
248 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
249 #ifdef CONFIG_SOFTMMU
250 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
251 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
252 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
253 #endif
254 break;
255 case 'I':
256 ct->ct |= TCG_CT_CONST_S16;
257 break;
258 case 'J':
259 ct->ct |= TCG_CT_CONST_U16;
260 break;
261 case 'M':
262 ct->ct |= TCG_CT_CONST_MONE;
263 break;
264 case 'T':
265 ct->ct |= TCG_CT_CONST_S32;
266 break;
267 case 'U':
268 ct->ct |= TCG_CT_CONST_U32;
269 break;
270 case 'W':
271 ct->ct |= TCG_CT_CONST_WSZ;
272 break;
273 case 'Z':
274 ct->ct |= TCG_CT_CONST_ZERO;
275 break;
276 default:
277 return NULL;
278 }
279 return ct_str;
280 }
281
282 /* test if a constant matches the constraint */
283 static int tcg_target_const_match(tcg_target_long val, TCGType type,
284 const TCGArgConstraint *arg_ct)
285 {
286 int ct = arg_ct->ct;
287 if (ct & TCG_CT_CONST) {
288 return 1;
289 }
290
291 /* The only 32-bit constraint we use aside from
292 TCG_CT_CONST is TCG_CT_CONST_S16. */
293 if (type == TCG_TYPE_I32) {
294 val = (int32_t)val;
295 }
296
297 if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) {
298 return 1;
299 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) {
300 return 1;
301 } else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
302 return 1;
303 } else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) {
304 return 1;
305 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
306 return 1;
307 } else if ((ct & TCG_CT_CONST_MONE) && val == -1) {
308 return 1;
309 } else if ((ct & TCG_CT_CONST_WSZ)
310 && val == (type == TCG_TYPE_I32 ? 32 : 64)) {
311 return 1;
312 }
313 return 0;
314 }
315
316 #define OPCD(opc) ((opc)<<26)
317 #define XO19(opc) (OPCD(19)|((opc)<<1))
318 #define MD30(opc) (OPCD(30)|((opc)<<2))
319 #define MDS30(opc) (OPCD(30)|((opc)<<1))
320 #define XO31(opc) (OPCD(31)|((opc)<<1))
321 #define XO58(opc) (OPCD(58)|(opc))
322 #define XO62(opc) (OPCD(62)|(opc))
323
324 #define B OPCD( 18)
325 #define BC OPCD( 16)
326 #define LBZ OPCD( 34)
327 #define LHZ OPCD( 40)
328 #define LHA OPCD( 42)
329 #define LWZ OPCD( 32)
330 #define LWZUX XO31( 55)
331 #define STB OPCD( 38)
332 #define STH OPCD( 44)
333 #define STW OPCD( 36)
334
335 #define STD XO62( 0)
336 #define STDU XO62( 1)
337 #define STDX XO31(149)
338
339 #define LD XO58( 0)
340 #define LDX XO31( 21)
341 #define LDU XO58( 1)
342 #define LDUX XO31( 53)
343 #define LWA XO58( 2)
344 #define LWAX XO31(341)
345
346 #define ADDIC OPCD( 12)
347 #define ADDI OPCD( 14)
348 #define ADDIS OPCD( 15)
349 #define ORI OPCD( 24)
350 #define ORIS OPCD( 25)
351 #define XORI OPCD( 26)
352 #define XORIS OPCD( 27)
353 #define ANDI OPCD( 28)
354 #define ANDIS OPCD( 29)
355 #define MULLI OPCD( 7)
356 #define CMPLI OPCD( 10)
357 #define CMPI OPCD( 11)
358 #define SUBFIC OPCD( 8)
359
360 #define LWZU OPCD( 33)
361 #define STWU OPCD( 37)
362
363 #define RLWIMI OPCD( 20)
364 #define RLWINM OPCD( 21)
365 #define RLWNM OPCD( 23)
366
367 #define RLDICL MD30( 0)
368 #define RLDICR MD30( 1)
369 #define RLDIMI MD30( 3)
370 #define RLDCL MDS30( 8)
371
372 #define BCLR XO19( 16)
373 #define BCCTR XO19(528)
374 #define CRAND XO19(257)
375 #define CRANDC XO19(129)
376 #define CRNAND XO19(225)
377 #define CROR XO19(449)
378 #define CRNOR XO19( 33)
379
380 #define EXTSB XO31(954)
381 #define EXTSH XO31(922)
382 #define EXTSW XO31(986)
383 #define ADD XO31(266)
384 #define ADDE XO31(138)
385 #define ADDME XO31(234)
386 #define ADDZE XO31(202)
387 #define ADDC XO31( 10)
388 #define AND XO31( 28)
389 #define SUBF XO31( 40)
390 #define SUBFC XO31( 8)
391 #define SUBFE XO31(136)
392 #define SUBFME XO31(232)
393 #define SUBFZE XO31(200)
394 #define OR XO31(444)
395 #define XOR XO31(316)
396 #define MULLW XO31(235)
397 #define MULHW XO31( 75)
398 #define MULHWU XO31( 11)
399 #define DIVW XO31(491)
400 #define DIVWU XO31(459)
401 #define CMP XO31( 0)
402 #define CMPL XO31( 32)
403 #define LHBRX XO31(790)
404 #define LWBRX XO31(534)
405 #define LDBRX XO31(532)
406 #define STHBRX XO31(918)
407 #define STWBRX XO31(662)
408 #define STDBRX XO31(660)
409 #define MFSPR XO31(339)
410 #define MTSPR XO31(467)
411 #define SRAWI XO31(824)
412 #define NEG XO31(104)
413 #define MFCR XO31( 19)
414 #define MFOCRF (MFCR | (1u << 20))
415 #define NOR XO31(124)
416 #define CNTLZW XO31( 26)
417 #define CNTLZD XO31( 58)
418 #define CNTTZW XO31(538)
419 #define CNTTZD XO31(570)
420 #define CNTPOPW XO31(378)
421 #define CNTPOPD XO31(506)
422 #define ANDC XO31( 60)
423 #define ORC XO31(412)
424 #define EQV XO31(284)
425 #define NAND XO31(476)
426 #define ISEL XO31( 15)
427
428 #define MULLD XO31(233)
429 #define MULHD XO31( 73)
430 #define MULHDU XO31( 9)
431 #define DIVD XO31(489)
432 #define DIVDU XO31(457)
433
434 #define LBZX XO31( 87)
435 #define LHZX XO31(279)
436 #define LHAX XO31(343)
437 #define LWZX XO31( 23)
438 #define STBX XO31(215)
439 #define STHX XO31(407)
440 #define STWX XO31(151)
441
442 #define EIEIO XO31(854)
443 #define HWSYNC XO31(598)
444 #define LWSYNC (HWSYNC | (1u << 21))
445
446 #define SPR(a, b) ((((a)<<5)|(b))<<11)
447 #define LR SPR(8, 0)
448 #define CTR SPR(9, 0)
449
450 #define SLW XO31( 24)
451 #define SRW XO31(536)
452 #define SRAW XO31(792)
453
454 #define SLD XO31( 27)
455 #define SRD XO31(539)
456 #define SRAD XO31(794)
457 #define SRADI XO31(413<<1)
458
459 #define TW XO31( 4)
460 #define TRAP (TW | TO(31))
461
462 #define NOP ORI /* ori 0,0,0 */
463
464 #define RT(r) ((r)<<21)
465 #define RS(r) ((r)<<21)
466 #define RA(r) ((r)<<16)
467 #define RB(r) ((r)<<11)
468 #define TO(t) ((t)<<21)
469 #define SH(s) ((s)<<11)
470 #define MB(b) ((b)<<6)
471 #define ME(e) ((e)<<1)
472 #define BO(o) ((o)<<21)
473 #define MB64(b) ((b)<<5)
474 #define FXM(b) (1 << (19 - (b)))
475
476 #define LK 1
477
478 #define TAB(t, a, b) (RT(t) | RA(a) | RB(b))
479 #define SAB(s, a, b) (RS(s) | RA(a) | RB(b))
480 #define TAI(s, a, i) (RT(s) | RA(a) | ((i) & 0xffff))
481 #define SAI(s, a, i) (RS(s) | RA(a) | ((i) & 0xffff))
482
483 #define BF(n) ((n)<<23)
484 #define BI(n, c) (((c)+((n)*4))<<16)
485 #define BT(n, c) (((c)+((n)*4))<<21)
486 #define BA(n, c) (((c)+((n)*4))<<16)
487 #define BB(n, c) (((c)+((n)*4))<<11)
488 #define BC_(n, c) (((c)+((n)*4))<<6)
489
490 #define BO_COND_TRUE BO(12)
491 #define BO_COND_FALSE BO( 4)
492 #define BO_ALWAYS BO(20)
493
494 enum {
495 CR_LT,
496 CR_GT,
497 CR_EQ,
498 CR_SO
499 };
500
501 static const uint32_t tcg_to_bc[] = {
502 [TCG_COND_EQ] = BC | BI(7, CR_EQ) | BO_COND_TRUE,
503 [TCG_COND_NE] = BC | BI(7, CR_EQ) | BO_COND_FALSE,
504 [TCG_COND_LT] = BC | BI(7, CR_LT) | BO_COND_TRUE,
505 [TCG_COND_GE] = BC | BI(7, CR_LT) | BO_COND_FALSE,
506 [TCG_COND_LE] = BC | BI(7, CR_GT) | BO_COND_FALSE,
507 [TCG_COND_GT] = BC | BI(7, CR_GT) | BO_COND_TRUE,
508 [TCG_COND_LTU] = BC | BI(7, CR_LT) | BO_COND_TRUE,
509 [TCG_COND_GEU] = BC | BI(7, CR_LT) | BO_COND_FALSE,
510 [TCG_COND_LEU] = BC | BI(7, CR_GT) | BO_COND_FALSE,
511 [TCG_COND_GTU] = BC | BI(7, CR_GT) | BO_COND_TRUE,
512 };
513
514 /* The low bit here is set if the RA and RB fields must be inverted. */
515 static const uint32_t tcg_to_isel[] = {
516 [TCG_COND_EQ] = ISEL | BC_(7, CR_EQ),
517 [TCG_COND_NE] = ISEL | BC_(7, CR_EQ) | 1,
518 [TCG_COND_LT] = ISEL | BC_(7, CR_LT),
519 [TCG_COND_GE] = ISEL | BC_(7, CR_LT) | 1,
520 [TCG_COND_LE] = ISEL | BC_(7, CR_GT) | 1,
521 [TCG_COND_GT] = ISEL | BC_(7, CR_GT),
522 [TCG_COND_LTU] = ISEL | BC_(7, CR_LT),
523 [TCG_COND_GEU] = ISEL | BC_(7, CR_LT) | 1,
524 [TCG_COND_LEU] = ISEL | BC_(7, CR_GT) | 1,
525 [TCG_COND_GTU] = ISEL | BC_(7, CR_GT),
526 };
527
528 static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
529 intptr_t value, intptr_t addend)
530 {
531 tcg_insn_unit *target;
532
533 value += addend;
534 target = (tcg_insn_unit *)value;
535
536 switch (type) {
537 case R_PPC_REL14:
538 return reloc_pc14(code_ptr, target);
539 case R_PPC_REL24:
540 return reloc_pc24(code_ptr, target);
541 case R_PPC_ADDR16:
542 /*
543 * We are (slightly) abusing this relocation type. In particular,
544 * assert that the low 2 bits are zero, and do not modify them.
545 * That way we can use this with LD et al that have opcode bits
546 * in the low 2 bits of the insn.
547 */
548 if ((value & 3) || value != (int16_t)value) {
549 return false;
550 }
551 *code_ptr = (*code_ptr & ~0xfffc) | (value & 0xfffc);
552 break;
553 default:
554 g_assert_not_reached();
555 }
556 return true;
557 }
558
559 static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
560 TCGReg base, tcg_target_long offset);
561
562 static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
563 {
564 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
565 if (ret != arg) {
566 tcg_out32(s, OR | SAB(arg, ret, arg));
567 }
568 return true;
569 }
570
571 static inline void tcg_out_rld(TCGContext *s, int op, TCGReg ra, TCGReg rs,
572 int sh, int mb)
573 {
574 tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
575 sh = SH(sh & 0x1f) | (((sh >> 5) & 1) << 1);
576 mb = MB64((mb >> 5) | ((mb << 1) & 0x3f));
577 tcg_out32(s, op | RA(ra) | RS(rs) | sh | mb);
578 }
579
580 static inline void tcg_out_rlw(TCGContext *s, int op, TCGReg ra, TCGReg rs,
581 int sh, int mb, int me)
582 {
583 tcg_out32(s, op | RA(ra) | RS(rs) | SH(sh) | MB(mb) | ME(me));
584 }
585
586 static inline void tcg_out_ext32u(TCGContext *s, TCGReg dst, TCGReg src)
587 {
588 tcg_out_rld(s, RLDICL, dst, src, 0, 32);
589 }
590
591 static inline void tcg_out_shli32(TCGContext *s, TCGReg dst, TCGReg src, int c)
592 {
593 tcg_out_rlw(s, RLWINM, dst, src, c, 0, 31 - c);
594 }
595
596 static inline void tcg_out_shli64(TCGContext *s, TCGReg dst, TCGReg src, int c)
597 {
598 tcg_out_rld(s, RLDICR, dst, src, c, 63 - c);
599 }
600
601 static inline void tcg_out_shri32(TCGContext *s, TCGReg dst, TCGReg src, int c)
602 {
603 tcg_out_rlw(s, RLWINM, dst, src, 32 - c, c, 31);
604 }
605
606 static inline void tcg_out_shri64(TCGContext *s, TCGReg dst, TCGReg src, int c)
607 {
608 tcg_out_rld(s, RLDICL, dst, src, 64 - c, c);
609 }
610
611 /* Emit a move into ret of arg, if it can be done in one insn. */
612 static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg)
613 {
614 if (arg == (int16_t)arg) {
615 tcg_out32(s, ADDI | TAI(ret, 0, arg));
616 return true;
617 }
618 if (arg == (int32_t)arg && (arg & 0xffff) == 0) {
619 tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16));
620 return true;
621 }
622 return false;
623 }
624
625 static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
626 tcg_target_long arg, bool in_prologue)
627 {
628 intptr_t tb_diff;
629 tcg_target_long tmp;
630 int shift;
631
632 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
633
634 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
635 arg = (int32_t)arg;
636 }
637
638 /* Load 16-bit immediates with one insn. */
639 if (tcg_out_movi_one(s, ret, arg)) {
640 return;
641 }
642
643 /* Load addresses within the TB with one insn. */
644 tb_diff = arg - (intptr_t)s->code_gen_ptr;
645 if (!in_prologue && USE_REG_TB && tb_diff == (int16_t)tb_diff) {
646 tcg_out32(s, ADDI | TAI(ret, TCG_REG_TB, tb_diff));
647 return;
648 }
649
650 /* Load 32-bit immediates with two insns. Note that we've already
651 eliminated bare ADDIS, so we know both insns are required. */
652 if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) {
653 tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16));
654 tcg_out32(s, ORI | SAI(ret, ret, arg));
655 return;
656 }
657 if (arg == (uint32_t)arg && !(arg & 0x8000)) {
658 tcg_out32(s, ADDI | TAI(ret, 0, arg));
659 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
660 return;
661 }
662
663 /* Load masked 16-bit value. */
664 if (arg > 0 && (arg & 0x8000)) {
665 tmp = arg | 0x7fff;
666 if ((tmp & (tmp + 1)) == 0) {
667 int mb = clz64(tmp + 1) + 1;
668 tcg_out32(s, ADDI | TAI(ret, 0, arg));
669 tcg_out_rld(s, RLDICL, ret, ret, 0, mb);
670 return;
671 }
672 }
673
674 /* Load common masks with 2 insns. */
675 shift = ctz64(arg);
676 tmp = arg >> shift;
677 if (tmp == (int16_t)tmp) {
678 tcg_out32(s, ADDI | TAI(ret, 0, tmp));
679 tcg_out_shli64(s, ret, ret, shift);
680 return;
681 }
682 shift = clz64(arg);
683 if (tcg_out_movi_one(s, ret, arg << shift)) {
684 tcg_out_shri64(s, ret, ret, shift);
685 return;
686 }
687
688 /* Load addresses within 2GB of TB with 2 (or rarely 3) insns. */
689 if (!in_prologue && USE_REG_TB && tb_diff == (int32_t)tb_diff) {
690 tcg_out_mem_long(s, ADDI, ADD, ret, TCG_REG_TB, tb_diff);
691 return;
692 }
693
694 /* Use the constant pool, if possible. */
695 if (!in_prologue && USE_REG_TB) {
696 new_pool_label(s, arg, R_PPC_ADDR16, s->code_ptr,
697 -(intptr_t)s->code_gen_ptr);
698 tcg_out32(s, LD | TAI(ret, TCG_REG_TB, 0));
699 return;
700 }
701
702 tmp = arg >> 31 >> 1;
703 tcg_out_movi(s, TCG_TYPE_I32, ret, tmp);
704 if (tmp) {
705 tcg_out_shli64(s, ret, ret, 32);
706 }
707 if (arg & 0xffff0000) {
708 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
709 }
710 if (arg & 0xffff) {
711 tcg_out32(s, ORI | SAI(ret, ret, arg));
712 }
713 }
714
715 static inline void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret,
716 tcg_target_long arg)
717 {
718 tcg_out_movi_int(s, type, ret, arg, false);
719 }
720
721 static bool mask_operand(uint32_t c, int *mb, int *me)
722 {
723 uint32_t lsb, test;
724
725 /* Accept a bit pattern like:
726 0....01....1
727 1....10....0
728 0..01..10..0
729 Keep track of the transitions. */
730 if (c == 0 || c == -1) {
731 return false;
732 }
733 test = c;
734 lsb = test & -test;
735 test += lsb;
736 if (test & (test - 1)) {
737 return false;
738 }
739
740 *me = clz32(lsb);
741 *mb = test ? clz32(test & -test) + 1 : 0;
742 return true;
743 }
744
745 static bool mask64_operand(uint64_t c, int *mb, int *me)
746 {
747 uint64_t lsb;
748
749 if (c == 0) {
750 return false;
751 }
752
753 lsb = c & -c;
754 /* Accept 1..10..0. */
755 if (c == -lsb) {
756 *mb = 0;
757 *me = clz64(lsb);
758 return true;
759 }
760 /* Accept 0..01..1. */
761 if (lsb == 1 && (c & (c + 1)) == 0) {
762 *mb = clz64(c + 1) + 1;
763 *me = 63;
764 return true;
765 }
766 return false;
767 }
768
769 static void tcg_out_andi32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
770 {
771 int mb, me;
772
773 if (mask_operand(c, &mb, &me)) {
774 tcg_out_rlw(s, RLWINM, dst, src, 0, mb, me);
775 } else if ((c & 0xffff) == c) {
776 tcg_out32(s, ANDI | SAI(src, dst, c));
777 return;
778 } else if ((c & 0xffff0000) == c) {
779 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
780 return;
781 } else {
782 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R0, c);
783 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0));
784 }
785 }
786
787 static void tcg_out_andi64(TCGContext *s, TCGReg dst, TCGReg src, uint64_t c)
788 {
789 int mb, me;
790
791 tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
792 if (mask64_operand(c, &mb, &me)) {
793 if (mb == 0) {
794 tcg_out_rld(s, RLDICR, dst, src, 0, me);
795 } else {
796 tcg_out_rld(s, RLDICL, dst, src, 0, mb);
797 }
798 } else if ((c & 0xffff) == c) {
799 tcg_out32(s, ANDI | SAI(src, dst, c));
800 return;
801 } else if ((c & 0xffff0000) == c) {
802 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
803 return;
804 } else {
805 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, c);
806 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0));
807 }
808 }
809
810 static void tcg_out_zori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c,
811 int op_lo, int op_hi)
812 {
813 if (c >> 16) {
814 tcg_out32(s, op_hi | SAI(src, dst, c >> 16));
815 src = dst;
816 }
817 if (c & 0xffff) {
818 tcg_out32(s, op_lo | SAI(src, dst, c));
819 src = dst;
820 }
821 }
822
823 static void tcg_out_ori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
824 {
825 tcg_out_zori32(s, dst, src, c, ORI, ORIS);
826 }
827
828 static void tcg_out_xori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
829 {
830 tcg_out_zori32(s, dst, src, c, XORI, XORIS);
831 }
832
833 static void tcg_out_b(TCGContext *s, int mask, tcg_insn_unit *target)
834 {
835 ptrdiff_t disp = tcg_pcrel_diff(s, target);
836 if (in_range_b(disp)) {
837 tcg_out32(s, B | (disp & 0x3fffffc) | mask);
838 } else {
839 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, (uintptr_t)target);
840 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | CTR);
841 tcg_out32(s, BCCTR | BO_ALWAYS | mask);
842 }
843 }
844
845 static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
846 TCGReg base, tcg_target_long offset)
847 {
848 tcg_target_long orig = offset, l0, l1, extra = 0, align = 0;
849 bool is_store = false;
850 TCGReg rs = TCG_REG_TMP1;
851
852 switch (opi) {
853 case LD: case LWA:
854 align = 3;
855 /* FALLTHRU */
856 default:
857 if (rt != TCG_REG_R0) {
858 rs = rt;
859 break;
860 }
861 break;
862 case STD:
863 align = 3;
864 /* FALLTHRU */
865 case STB: case STH: case STW:
866 is_store = true;
867 break;
868 }
869
870 /* For unaligned, or very large offsets, use the indexed form. */
871 if (offset & align || offset != (int32_t)offset) {
872 if (rs == base) {
873 rs = TCG_REG_R0;
874 }
875 tcg_debug_assert(!is_store || rs != rt);
876 tcg_out_movi(s, TCG_TYPE_PTR, rs, orig);
877 tcg_out32(s, opx | TAB(rt, base, rs));
878 return;
879 }
880
881 l0 = (int16_t)offset;
882 offset = (offset - l0) >> 16;
883 l1 = (int16_t)offset;
884
885 if (l1 < 0 && orig >= 0) {
886 extra = 0x4000;
887 l1 = (int16_t)(offset - 0x4000);
888 }
889 if (l1) {
890 tcg_out32(s, ADDIS | TAI(rs, base, l1));
891 base = rs;
892 }
893 if (extra) {
894 tcg_out32(s, ADDIS | TAI(rs, base, extra));
895 base = rs;
896 }
897 if (opi != ADDI || base != rt || l0 != 0) {
898 tcg_out32(s, opi | TAI(rt, base, l0));
899 }
900 }
901
902 static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
903 TCGReg arg1, intptr_t arg2)
904 {
905 int opi, opx;
906
907 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
908 if (type == TCG_TYPE_I32) {
909 opi = LWZ, opx = LWZX;
910 } else {
911 opi = LD, opx = LDX;
912 }
913 tcg_out_mem_long(s, opi, opx, ret, arg1, arg2);
914 }
915
916 static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
917 TCGReg arg1, intptr_t arg2)
918 {
919 int opi, opx;
920
921 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
922 if (type == TCG_TYPE_I32) {
923 opi = STW, opx = STWX;
924 } else {
925 opi = STD, opx = STDX;
926 }
927 tcg_out_mem_long(s, opi, opx, arg, arg1, arg2);
928 }
929
930 static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
931 TCGReg base, intptr_t ofs)
932 {
933 return false;
934 }
935
936 static void tcg_out_cmp(TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
937 int const_arg2, int cr, TCGType type)
938 {
939 int imm;
940 uint32_t op;
941
942 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
943
944 /* Simplify the comparisons below wrt CMPI. */
945 if (type == TCG_TYPE_I32) {
946 arg2 = (int32_t)arg2;
947 }
948
949 switch (cond) {
950 case TCG_COND_EQ:
951 case TCG_COND_NE:
952 if (const_arg2) {
953 if ((int16_t) arg2 == arg2) {
954 op = CMPI;
955 imm = 1;
956 break;
957 } else if ((uint16_t) arg2 == arg2) {
958 op = CMPLI;
959 imm = 1;
960 break;
961 }
962 }
963 op = CMPL;
964 imm = 0;
965 break;
966
967 case TCG_COND_LT:
968 case TCG_COND_GE:
969 case TCG_COND_LE:
970 case TCG_COND_GT:
971 if (const_arg2) {
972 if ((int16_t) arg2 == arg2) {
973 op = CMPI;
974 imm = 1;
975 break;
976 }
977 }
978 op = CMP;
979 imm = 0;
980 break;
981
982 case TCG_COND_LTU:
983 case TCG_COND_GEU:
984 case TCG_COND_LEU:
985 case TCG_COND_GTU:
986 if (const_arg2) {
987 if ((uint16_t) arg2 == arg2) {
988 op = CMPLI;
989 imm = 1;
990 break;
991 }
992 }
993 op = CMPL;
994 imm = 0;
995 break;
996
997 default:
998 tcg_abort();
999 }
1000 op |= BF(cr) | ((type == TCG_TYPE_I64) << 21);
1001
1002 if (imm) {
1003 tcg_out32(s, op | RA(arg1) | (arg2 & 0xffff));
1004 } else {
1005 if (const_arg2) {
1006 tcg_out_movi(s, type, TCG_REG_R0, arg2);
1007 arg2 = TCG_REG_R0;
1008 }
1009 tcg_out32(s, op | RA(arg1) | RB(arg2));
1010 }
1011 }
1012
1013 static void tcg_out_setcond_eq0(TCGContext *s, TCGType type,
1014 TCGReg dst, TCGReg src)
1015 {
1016 if (type == TCG_TYPE_I32) {
1017 tcg_out32(s, CNTLZW | RS(src) | RA(dst));
1018 tcg_out_shri32(s, dst, dst, 5);
1019 } else {
1020 tcg_out32(s, CNTLZD | RS(src) | RA(dst));
1021 tcg_out_shri64(s, dst, dst, 6);
1022 }
1023 }
1024
1025 static void tcg_out_setcond_ne0(TCGContext *s, TCGReg dst, TCGReg src)
1026 {
1027 /* X != 0 implies X + -1 generates a carry. Extra addition
1028 trickery means: R = X-1 + ~X + C = X-1 + (-X+1) + C = C. */
1029 if (dst != src) {
1030 tcg_out32(s, ADDIC | TAI(dst, src, -1));
1031 tcg_out32(s, SUBFE | TAB(dst, dst, src));
1032 } else {
1033 tcg_out32(s, ADDIC | TAI(TCG_REG_R0, src, -1));
1034 tcg_out32(s, SUBFE | TAB(dst, TCG_REG_R0, src));
1035 }
1036 }
1037
1038 static TCGReg tcg_gen_setcond_xor(TCGContext *s, TCGReg arg1, TCGArg arg2,
1039 bool const_arg2)
1040 {
1041 if (const_arg2) {
1042 if ((uint32_t)arg2 == arg2) {
1043 tcg_out_xori32(s, TCG_REG_R0, arg1, arg2);
1044 } else {
1045 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, arg2);
1046 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, TCG_REG_R0));
1047 }
1048 } else {
1049 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, arg2));
1050 }
1051 return TCG_REG_R0;
1052 }
1053
1054 static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond,
1055 TCGArg arg0, TCGArg arg1, TCGArg arg2,
1056 int const_arg2)
1057 {
1058 int crop, sh;
1059
1060 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
1061
1062 /* Ignore high bits of a potential constant arg2. */
1063 if (type == TCG_TYPE_I32) {
1064 arg2 = (uint32_t)arg2;
1065 }
1066
1067 /* Handle common and trivial cases before handling anything else. */
1068 if (arg2 == 0) {
1069 switch (cond) {
1070 case TCG_COND_EQ:
1071 tcg_out_setcond_eq0(s, type, arg0, arg1);
1072 return;
1073 case TCG_COND_NE:
1074 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
1075 tcg_out_ext32u(s, TCG_REG_R0, arg1);
1076 arg1 = TCG_REG_R0;
1077 }
1078 tcg_out_setcond_ne0(s, arg0, arg1);
1079 return;
1080 case TCG_COND_GE:
1081 tcg_out32(s, NOR | SAB(arg1, arg0, arg1));
1082 arg1 = arg0;
1083 /* FALLTHRU */
1084 case TCG_COND_LT:
1085 /* Extract the sign bit. */
1086 if (type == TCG_TYPE_I32) {
1087 tcg_out_shri32(s, arg0, arg1, 31);
1088 } else {
1089 tcg_out_shri64(s, arg0, arg1, 63);
1090 }
1091 return;
1092 default:
1093 break;
1094 }
1095 }
1096
1097 /* If we have ISEL, we can implement everything with 3 or 4 insns.
1098 All other cases below are also at least 3 insns, so speed up the
1099 code generator by not considering them and always using ISEL. */
1100 if (HAVE_ISEL) {
1101 int isel, tab;
1102
1103 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1104
1105 isel = tcg_to_isel[cond];
1106
1107 tcg_out_movi(s, type, arg0, 1);
1108 if (isel & 1) {
1109 /* arg0 = (bc ? 0 : 1) */
1110 tab = TAB(arg0, 0, arg0);
1111 isel &= ~1;
1112 } else {
1113 /* arg0 = (bc ? 1 : 0) */
1114 tcg_out_movi(s, type, TCG_REG_R0, 0);
1115 tab = TAB(arg0, arg0, TCG_REG_R0);
1116 }
1117 tcg_out32(s, isel | tab);
1118 return;
1119 }
1120
1121 switch (cond) {
1122 case TCG_COND_EQ:
1123 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
1124 tcg_out_setcond_eq0(s, type, arg0, arg1);
1125 return;
1126
1127 case TCG_COND_NE:
1128 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
1129 /* Discard the high bits only once, rather than both inputs. */
1130 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
1131 tcg_out_ext32u(s, TCG_REG_R0, arg1);
1132 arg1 = TCG_REG_R0;
1133 }
1134 tcg_out_setcond_ne0(s, arg0, arg1);
1135 return;
1136
1137 case TCG_COND_GT:
1138 case TCG_COND_GTU:
1139 sh = 30;
1140 crop = 0;
1141 goto crtest;
1142
1143 case TCG_COND_LT:
1144 case TCG_COND_LTU:
1145 sh = 29;
1146 crop = 0;
1147 goto crtest;
1148
1149 case TCG_COND_GE:
1150 case TCG_COND_GEU:
1151 sh = 31;
1152 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_LT) | BB(7, CR_LT);
1153 goto crtest;
1154
1155 case TCG_COND_LE:
1156 case TCG_COND_LEU:
1157 sh = 31;
1158 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_GT) | BB(7, CR_GT);
1159 crtest:
1160 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1161 if (crop) {
1162 tcg_out32(s, crop);
1163 }
1164 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7));
1165 tcg_out_rlw(s, RLWINM, arg0, TCG_REG_R0, sh, 31, 31);
1166 break;
1167
1168 default:
1169 tcg_abort();
1170 }
1171 }
1172
1173 static void tcg_out_bc(TCGContext *s, int bc, TCGLabel *l)
1174 {
1175 if (l->has_value) {
1176 bc |= reloc_pc14_val(s->code_ptr, l->u.value_ptr);
1177 } else {
1178 tcg_out_reloc(s, s->code_ptr, R_PPC_REL14, l, 0);
1179 }
1180 tcg_out32(s, bc);
1181 }
1182
1183 static void tcg_out_brcond(TCGContext *s, TCGCond cond,
1184 TCGArg arg1, TCGArg arg2, int const_arg2,
1185 TCGLabel *l, TCGType type)
1186 {
1187 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1188 tcg_out_bc(s, tcg_to_bc[cond], l);
1189 }
1190
1191 static void tcg_out_movcond(TCGContext *s, TCGType type, TCGCond cond,
1192 TCGArg dest, TCGArg c1, TCGArg c2, TCGArg v1,
1193 TCGArg v2, bool const_c2)
1194 {
1195 /* If for some reason both inputs are zero, don't produce bad code. */
1196 if (v1 == 0 && v2 == 0) {
1197 tcg_out_movi(s, type, dest, 0);
1198 return;
1199 }
1200
1201 tcg_out_cmp(s, cond, c1, c2, const_c2, 7, type);
1202
1203 if (HAVE_ISEL) {
1204 int isel = tcg_to_isel[cond];
1205
1206 /* Swap the V operands if the operation indicates inversion. */
1207 if (isel & 1) {
1208 int t = v1;
1209 v1 = v2;
1210 v2 = t;
1211 isel &= ~1;
1212 }
1213 /* V1 == 0 is handled by isel; V2 == 0 must be handled by hand. */
1214 if (v2 == 0) {
1215 tcg_out_movi(s, type, TCG_REG_R0, 0);
1216 }
1217 tcg_out32(s, isel | TAB(dest, v1, v2));
1218 } else {
1219 if (dest == v2) {
1220 cond = tcg_invert_cond(cond);
1221 v2 = v1;
1222 } else if (dest != v1) {
1223 if (v1 == 0) {
1224 tcg_out_movi(s, type, dest, 0);
1225 } else {
1226 tcg_out_mov(s, type, dest, v1);
1227 }
1228 }
1229 /* Branch forward over one insn */
1230 tcg_out32(s, tcg_to_bc[cond] | 8);
1231 if (v2 == 0) {
1232 tcg_out_movi(s, type, dest, 0);
1233 } else {
1234 tcg_out_mov(s, type, dest, v2);
1235 }
1236 }
1237 }
1238
1239 static void tcg_out_cntxz(TCGContext *s, TCGType type, uint32_t opc,
1240 TCGArg a0, TCGArg a1, TCGArg a2, bool const_a2)
1241 {
1242 if (const_a2 && a2 == (type == TCG_TYPE_I32 ? 32 : 64)) {
1243 tcg_out32(s, opc | RA(a0) | RS(a1));
1244 } else {
1245 tcg_out_cmp(s, TCG_COND_EQ, a1, 0, 1, 7, type);
1246 /* Note that the only other valid constant for a2 is 0. */
1247 if (HAVE_ISEL) {
1248 tcg_out32(s, opc | RA(TCG_REG_R0) | RS(a1));
1249 tcg_out32(s, tcg_to_isel[TCG_COND_EQ] | TAB(a0, a2, TCG_REG_R0));
1250 } else if (!const_a2 && a0 == a2) {
1251 tcg_out32(s, tcg_to_bc[TCG_COND_EQ] | 8);
1252 tcg_out32(s, opc | RA(a0) | RS(a1));
1253 } else {
1254 tcg_out32(s, opc | RA(a0) | RS(a1));
1255 tcg_out32(s, tcg_to_bc[TCG_COND_NE] | 8);
1256 if (const_a2) {
1257 tcg_out_movi(s, type, a0, 0);
1258 } else {
1259 tcg_out_mov(s, type, a0, a2);
1260 }
1261 }
1262 }
1263 }
1264
1265 static void tcg_out_cmp2(TCGContext *s, const TCGArg *args,
1266 const int *const_args)
1267 {
1268 static const struct { uint8_t bit1, bit2; } bits[] = {
1269 [TCG_COND_LT ] = { CR_LT, CR_LT },
1270 [TCG_COND_LE ] = { CR_LT, CR_GT },
1271 [TCG_COND_GT ] = { CR_GT, CR_GT },
1272 [TCG_COND_GE ] = { CR_GT, CR_LT },
1273 [TCG_COND_LTU] = { CR_LT, CR_LT },
1274 [TCG_COND_LEU] = { CR_LT, CR_GT },
1275 [TCG_COND_GTU] = { CR_GT, CR_GT },
1276 [TCG_COND_GEU] = { CR_GT, CR_LT },
1277 };
1278
1279 TCGCond cond = args[4], cond2;
1280 TCGArg al, ah, bl, bh;
1281 int blconst, bhconst;
1282 int op, bit1, bit2;
1283
1284 al = args[0];
1285 ah = args[1];
1286 bl = args[2];
1287 bh = args[3];
1288 blconst = const_args[2];
1289 bhconst = const_args[3];
1290
1291 switch (cond) {
1292 case TCG_COND_EQ:
1293 op = CRAND;
1294 goto do_equality;
1295 case TCG_COND_NE:
1296 op = CRNAND;
1297 do_equality:
1298 tcg_out_cmp(s, cond, al, bl, blconst, 6, TCG_TYPE_I32);
1299 tcg_out_cmp(s, cond, ah, bh, bhconst, 7, TCG_TYPE_I32);
1300 tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
1301 break;
1302
1303 case TCG_COND_LT:
1304 case TCG_COND_LE:
1305 case TCG_COND_GT:
1306 case TCG_COND_GE:
1307 case TCG_COND_LTU:
1308 case TCG_COND_LEU:
1309 case TCG_COND_GTU:
1310 case TCG_COND_GEU:
1311 bit1 = bits[cond].bit1;
1312 bit2 = bits[cond].bit2;
1313 op = (bit1 != bit2 ? CRANDC : CRAND);
1314 cond2 = tcg_unsigned_cond(cond);
1315
1316 tcg_out_cmp(s, cond, ah, bh, bhconst, 6, TCG_TYPE_I32);
1317 tcg_out_cmp(s, cond2, al, bl, blconst, 7, TCG_TYPE_I32);
1318 tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, bit2));
1319 tcg_out32(s, CROR | BT(7, CR_EQ) | BA(6, bit1) | BB(7, CR_EQ));
1320 break;
1321
1322 default:
1323 tcg_abort();
1324 }
1325 }
1326
1327 static void tcg_out_setcond2(TCGContext *s, const TCGArg *args,
1328 const int *const_args)
1329 {
1330 tcg_out_cmp2(s, args + 1, const_args + 1);
1331 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7));
1332 tcg_out_rlw(s, RLWINM, args[0], TCG_REG_R0, 31, 31, 31);
1333 }
1334
1335 static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args,
1336 const int *const_args)
1337 {
1338 tcg_out_cmp2(s, args, const_args);
1339 tcg_out_bc(s, BC | BI(7, CR_EQ) | BO_COND_TRUE, arg_label(args[5]));
1340 }
1341
1342 static void tcg_out_mb(TCGContext *s, TCGArg a0)
1343 {
1344 uint32_t insn = HWSYNC;
1345 a0 &= TCG_MO_ALL;
1346 if (a0 == TCG_MO_LD_LD) {
1347 insn = LWSYNC;
1348 } else if (a0 == TCG_MO_ST_ST) {
1349 insn = EIEIO;
1350 }
1351 tcg_out32(s, insn);
1352 }
1353
1354 void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr,
1355 uintptr_t addr)
1356 {
1357 if (TCG_TARGET_REG_BITS == 64) {
1358 tcg_insn_unit i1, i2;
1359 intptr_t tb_diff = addr - tc_ptr;
1360 intptr_t br_diff = addr - (jmp_addr + 4);
1361 uint64_t pair;
1362
1363 /* This does not exercise the range of the branch, but we do
1364 still need to be able to load the new value of TCG_REG_TB.
1365 But this does still happen quite often. */
1366 if (tb_diff == (int16_t)tb_diff) {
1367 i1 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, tb_diff);
1368 i2 = B | (br_diff & 0x3fffffc);
1369 } else {
1370 intptr_t lo = (int16_t)tb_diff;
1371 intptr_t hi = (int32_t)(tb_diff - lo);
1372 assert(tb_diff == hi + lo);
1373 i1 = ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, hi >> 16);
1374 i2 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, lo);
1375 }
1376 #ifdef HOST_WORDS_BIGENDIAN
1377 pair = (uint64_t)i1 << 32 | i2;
1378 #else
1379 pair = (uint64_t)i2 << 32 | i1;
1380 #endif
1381
1382 /* As per the enclosing if, this is ppc64. Avoid the _Static_assert
1383 within atomic_set that would fail to build a ppc32 host. */
1384 atomic_set__nocheck((uint64_t *)jmp_addr, pair);
1385 flush_icache_range(jmp_addr, jmp_addr + 8);
1386 } else {
1387 intptr_t diff = addr - jmp_addr;
1388 tcg_debug_assert(in_range_b(diff));
1389 atomic_set((uint32_t *)jmp_addr, B | (diff & 0x3fffffc));
1390 flush_icache_range(jmp_addr, jmp_addr + 4);
1391 }
1392 }
1393
1394 static void tcg_out_call(TCGContext *s, tcg_insn_unit *target)
1395 {
1396 #ifdef _CALL_AIX
1397 /* Look through the descriptor. If the branch is in range, and we
1398 don't have to spend too much effort on building the toc. */
1399 void *tgt = ((void **)target)[0];
1400 uintptr_t toc = ((uintptr_t *)target)[1];
1401 intptr_t diff = tcg_pcrel_diff(s, tgt);
1402
1403 if (in_range_b(diff) && toc == (uint32_t)toc) {
1404 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, toc);
1405 tcg_out_b(s, LK, tgt);
1406 } else {
1407 /* Fold the low bits of the constant into the addresses below. */
1408 intptr_t arg = (intptr_t)target;
1409 int ofs = (int16_t)arg;
1410
1411 if (ofs + 8 < 0x8000) {
1412 arg -= ofs;
1413 } else {
1414 ofs = 0;
1415 }
1416 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, arg);
1417 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_TMP1, ofs);
1418 tcg_out32(s, MTSPR | RA(TCG_REG_R0) | CTR);
1419 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_REG_TMP1, ofs + SZP);
1420 tcg_out32(s, BCCTR | BO_ALWAYS | LK);
1421 }
1422 #elif defined(_CALL_ELF) && _CALL_ELF == 2
1423 intptr_t diff;
1424
1425 /* In the ELFv2 ABI, we have to set up r12 to contain the destination
1426 address, which the callee uses to compute its TOC address. */
1427 /* FIXME: when the branch is in range, we could avoid r12 load if we
1428 knew that the destination uses the same TOC, and what its local
1429 entry point offset is. */
1430 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R12, (intptr_t)target);
1431
1432 diff = tcg_pcrel_diff(s, target);
1433 if (in_range_b(diff)) {
1434 tcg_out_b(s, LK, target);
1435 } else {
1436 tcg_out32(s, MTSPR | RS(TCG_REG_R12) | CTR);
1437 tcg_out32(s, BCCTR | BO_ALWAYS | LK);
1438 }
1439 #else
1440 tcg_out_b(s, LK, target);
1441 #endif
1442 }
1443
1444 static const uint32_t qemu_ldx_opc[16] = {
1445 [MO_UB] = LBZX,
1446 [MO_UW] = LHZX,
1447 [MO_UL] = LWZX,
1448 [MO_Q] = LDX,
1449 [MO_SW] = LHAX,
1450 [MO_SL] = LWAX,
1451 [MO_BSWAP | MO_UB] = LBZX,
1452 [MO_BSWAP | MO_UW] = LHBRX,
1453 [MO_BSWAP | MO_UL] = LWBRX,
1454 [MO_BSWAP | MO_Q] = LDBRX,
1455 };
1456
1457 static const uint32_t qemu_stx_opc[16] = {
1458 [MO_UB] = STBX,
1459 [MO_UW] = STHX,
1460 [MO_UL] = STWX,
1461 [MO_Q] = STDX,
1462 [MO_BSWAP | MO_UB] = STBX,
1463 [MO_BSWAP | MO_UW] = STHBRX,
1464 [MO_BSWAP | MO_UL] = STWBRX,
1465 [MO_BSWAP | MO_Q] = STDBRX,
1466 };
1467
1468 static const uint32_t qemu_exts_opc[4] = {
1469 EXTSB, EXTSH, EXTSW, 0
1470 };
1471
1472 #if defined (CONFIG_SOFTMMU)
1473 #include "tcg-ldst.inc.c"
1474
1475 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
1476 * int mmu_idx, uintptr_t ra)
1477 */
1478 static void * const qemu_ld_helpers[16] = {
1479 [MO_UB] = helper_ret_ldub_mmu,
1480 [MO_LEUW] = helper_le_lduw_mmu,
1481 [MO_LEUL] = helper_le_ldul_mmu,
1482 [MO_LEQ] = helper_le_ldq_mmu,
1483 [MO_BEUW] = helper_be_lduw_mmu,
1484 [MO_BEUL] = helper_be_ldul_mmu,
1485 [MO_BEQ] = helper_be_ldq_mmu,
1486 };
1487
1488 /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
1489 * uintxx_t val, int mmu_idx, uintptr_t ra)
1490 */
1491 static void * const qemu_st_helpers[16] = {
1492 [MO_UB] = helper_ret_stb_mmu,
1493 [MO_LEUW] = helper_le_stw_mmu,
1494 [MO_LEUL] = helper_le_stl_mmu,
1495 [MO_LEQ] = helper_le_stq_mmu,
1496 [MO_BEUW] = helper_be_stw_mmu,
1497 [MO_BEUL] = helper_be_stl_mmu,
1498 [MO_BEQ] = helper_be_stq_mmu,
1499 };
1500
1501 /* We expect tlb_mask to be before tlb_table. */
1502 QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) <
1503 offsetof(CPUArchState, tlb_mask));
1504
1505 /* Perform the TLB load and compare. Places the result of the comparison
1506 in CR7, loads the addend of the TLB into R3, and returns the register
1507 containing the guest address (zero-extended into R4). Clobbers R0 and R2. */
1508
1509 static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp opc,
1510 TCGReg addrlo, TCGReg addrhi,
1511 int mem_index, bool is_read)
1512 {
1513 int cmp_off
1514 = (is_read
1515 ? offsetof(CPUTLBEntry, addr_read)
1516 : offsetof(CPUTLBEntry, addr_write));
1517 int mask_off = offsetof(CPUArchState, tlb_mask[mem_index]);
1518 int table_off = offsetof(CPUArchState, tlb_table[mem_index]);
1519 TCGReg mask_base = TCG_AREG0, table_base = TCG_AREG0;
1520 unsigned s_bits = opc & MO_SIZE;
1521 unsigned a_bits = get_alignment_bits(opc);
1522
1523 if (table_off > 0x7fff) {
1524 int mask_hi = mask_off - (int16_t)mask_off;
1525 int table_hi = table_off - (int16_t)table_off;
1526
1527 table_base = TCG_REG_R4;
1528 if (mask_hi == table_hi) {
1529 mask_base = table_base;
1530 } else if (mask_hi) {
1531 mask_base = TCG_REG_R3;
1532 tcg_out32(s, ADDIS | TAI(mask_base, TCG_AREG0, mask_hi >> 16));
1533 }
1534 tcg_out32(s, ADDIS | TAI(table_base, TCG_AREG0, table_hi >> 16));
1535 mask_off -= mask_hi;
1536 table_off -= table_hi;
1537 }
1538
1539 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
1540 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, mask_base, mask_off);
1541 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R4, table_base, table_off);
1542
1543 /* Extract the page index, shifted into place for tlb index. */
1544 if (TCG_TARGET_REG_BITS == 32) {
1545 tcg_out_shri32(s, TCG_REG_TMP1, addrlo,
1546 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
1547 } else {
1548 tcg_out_shri64(s, TCG_REG_TMP1, addrlo,
1549 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
1550 }
1551 tcg_out32(s, AND | SAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_TMP1));
1552
1553 /* Load the TLB comparator. */
1554 if (cmp_off == 0 && TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) {
1555 uint32_t lxu = (TCG_TARGET_REG_BITS == 32 || TARGET_LONG_BITS == 32
1556 ? LWZUX : LDUX);
1557 tcg_out32(s, lxu | TAB(TCG_REG_TMP1, TCG_REG_R3, TCG_REG_R4));
1558 } else {
1559 tcg_out32(s, ADD | TAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_R4));
1560 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1561 tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP1, TCG_REG_R3, cmp_off + 4);
1562 tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R4, TCG_REG_R3, cmp_off);
1563 } else {
1564 tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP1, TCG_REG_R3, cmp_off);
1565 }
1566 }
1567
1568 /* Load the TLB addend for use on the fast path. Do this asap
1569 to minimize any load use delay. */
1570 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_REG_R3,
1571 offsetof(CPUTLBEntry, addend));
1572
1573 /* Clear the non-page, non-alignment bits from the address */
1574 if (TCG_TARGET_REG_BITS == 32) {
1575 /* We don't support unaligned accesses on 32-bits.
1576 * Preserve the bottom bits and thus trigger a comparison
1577 * failure on unaligned accesses.
1578 */
1579 if (a_bits < s_bits) {
1580 a_bits = s_bits;
1581 }
1582 tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0,
1583 (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS);
1584 } else {
1585 TCGReg t = addrlo;
1586
1587 /* If the access is unaligned, we need to make sure we fail if we
1588 * cross a page boundary. The trick is to add the access size-1
1589 * to the address before masking the low bits. That will make the
1590 * address overflow to the next page if we cross a page boundary,
1591 * which will then force a mismatch of the TLB compare.
1592 */
1593 if (a_bits < s_bits) {
1594 unsigned a_mask = (1 << a_bits) - 1;
1595 unsigned s_mask = (1 << s_bits) - 1;
1596 tcg_out32(s, ADDI | TAI(TCG_REG_R0, t, s_mask - a_mask));
1597 t = TCG_REG_R0;
1598 }
1599
1600 /* Mask the address for the requested alignment. */
1601 if (TARGET_LONG_BITS == 32) {
1602 tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0,
1603 (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS);
1604 /* Zero-extend the address for use in the final address. */
1605 tcg_out_ext32u(s, TCG_REG_R4, addrlo);
1606 addrlo = TCG_REG_R4;
1607 } else if (a_bits == 0) {
1608 tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - TARGET_PAGE_BITS);
1609 } else {
1610 tcg_out_rld(s, RLDICL, TCG_REG_R0, t,
1611 64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - a_bits);
1612 tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BITS, 0);
1613 }
1614 }
1615
1616 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1617 tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1,
1618 0, 7, TCG_TYPE_I32);
1619 tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_R4, 0, 6, TCG_TYPE_I32);
1620 tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
1621 } else {
1622 tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1,
1623 0, 7, TCG_TYPE_TL);
1624 }
1625
1626 return addrlo;
1627 }
1628
1629 /* Record the context of a call to the out of line helper code for the slow
1630 path for a load or store, so that we can later generate the correct
1631 helper code. */
1632 static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
1633 TCGReg datalo_reg, TCGReg datahi_reg,
1634 TCGReg addrlo_reg, TCGReg addrhi_reg,
1635 tcg_insn_unit *raddr, tcg_insn_unit *lptr)
1636 {
1637 TCGLabelQemuLdst *label = new_ldst_label(s);
1638
1639 label->is_ld = is_ld;
1640 label->oi = oi;
1641 label->datalo_reg = datalo_reg;
1642 label->datahi_reg = datahi_reg;
1643 label->addrlo_reg = addrlo_reg;
1644 label->addrhi_reg = addrhi_reg;
1645 label->raddr = raddr;
1646 label->label_ptr[0] = lptr;
1647 }
1648
1649 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
1650 {
1651 TCGMemOpIdx oi = lb->oi;
1652 TCGMemOp opc = get_memop(oi);
1653 TCGReg hi, lo, arg = TCG_REG_R3;
1654
1655 if (!reloc_pc14(lb->label_ptr[0], s->code_ptr)) {
1656 return false;
1657 }
1658
1659 tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0);
1660
1661 lo = lb->addrlo_reg;
1662 hi = lb->addrhi_reg;
1663 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1664 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
1665 arg |= 1;
1666 #endif
1667 tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
1668 tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
1669 } else {
1670 /* If the address needed to be zero-extended, we'll have already
1671 placed it in R4. The only remaining case is 64-bit guest. */
1672 tcg_out_mov(s, TCG_TYPE_TL, arg++, lo);
1673 }
1674
1675 tcg_out_movi(s, TCG_TYPE_I32, arg++, oi);
1676 tcg_out32(s, MFSPR | RT(arg) | LR);
1677
1678 tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]);
1679
1680 lo = lb->datalo_reg;
1681 hi = lb->datahi_reg;
1682 if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) {
1683 tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_REG_R4);
1684 tcg_out_mov(s, TCG_TYPE_I32, hi, TCG_REG_R3);
1685 } else if (opc & MO_SIGN) {
1686 uint32_t insn = qemu_exts_opc[opc & MO_SIZE];
1687 tcg_out32(s, insn | RA(lo) | RS(TCG_REG_R3));
1688 } else {
1689 tcg_out_mov(s, TCG_TYPE_REG, lo, TCG_REG_R3);
1690 }
1691
1692 tcg_out_b(s, 0, lb->raddr);
1693 return true;
1694 }
1695
1696 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
1697 {
1698 TCGMemOpIdx oi = lb->oi;
1699 TCGMemOp opc = get_memop(oi);
1700 TCGMemOp s_bits = opc & MO_SIZE;
1701 TCGReg hi, lo, arg = TCG_REG_R3;
1702
1703 if (!reloc_pc14(lb->label_ptr[0], s->code_ptr)) {
1704 return false;
1705 }
1706
1707 tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0);
1708
1709 lo = lb->addrlo_reg;
1710 hi = lb->addrhi_reg;
1711 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1712 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
1713 arg |= 1;
1714 #endif
1715 tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
1716 tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
1717 } else {
1718 /* If the address needed to be zero-extended, we'll have already
1719 placed it in R4. The only remaining case is 64-bit guest. */
1720 tcg_out_mov(s, TCG_TYPE_TL, arg++, lo);
1721 }
1722
1723 lo = lb->datalo_reg;
1724 hi = lb->datahi_reg;
1725 if (TCG_TARGET_REG_BITS == 32) {
1726 switch (s_bits) {
1727 case MO_64:
1728 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
1729 arg |= 1;
1730 #endif
1731 tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
1732 /* FALLTHRU */
1733 case MO_32:
1734 tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
1735 break;
1736 default:
1737 tcg_out_rlw(s, RLWINM, arg++, lo, 0, 32 - (8 << s_bits), 31);
1738 break;
1739 }
1740 } else {
1741 if (s_bits == MO_64) {
1742 tcg_out_mov(s, TCG_TYPE_I64, arg++, lo);
1743 } else {
1744 tcg_out_rld(s, RLDICL, arg++, lo, 0, 64 - (8 << s_bits));
1745 }
1746 }
1747
1748 tcg_out_movi(s, TCG_TYPE_I32, arg++, oi);
1749 tcg_out32(s, MFSPR | RT(arg) | LR);
1750
1751 tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
1752
1753 tcg_out_b(s, 0, lb->raddr);
1754 return true;
1755 }
1756 #endif /* SOFTMMU */
1757
1758 static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
1759 {
1760 TCGReg datalo, datahi, addrlo, rbase;
1761 TCGReg addrhi __attribute__((unused));
1762 TCGMemOpIdx oi;
1763 TCGMemOp opc, s_bits;
1764 #ifdef CONFIG_SOFTMMU
1765 int mem_index;
1766 tcg_insn_unit *label_ptr;
1767 #endif
1768
1769 datalo = *args++;
1770 datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
1771 addrlo = *args++;
1772 addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
1773 oi = *args++;
1774 opc = get_memop(oi);
1775 s_bits = opc & MO_SIZE;
1776
1777 #ifdef CONFIG_SOFTMMU
1778 mem_index = get_mmuidx(oi);
1779 addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, true);
1780
1781 /* Load a pointer into the current opcode w/conditional branch-link. */
1782 label_ptr = s->code_ptr;
1783 tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
1784
1785 rbase = TCG_REG_R3;
1786 #else /* !CONFIG_SOFTMMU */
1787 rbase = guest_base ? TCG_GUEST_BASE_REG : 0;
1788 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1789 tcg_out_ext32u(s, TCG_REG_TMP1, addrlo);
1790 addrlo = TCG_REG_TMP1;
1791 }
1792 #endif
1793
1794 if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {
1795 if (opc & MO_BSWAP) {
1796 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
1797 tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo));
1798 tcg_out32(s, LWBRX | TAB(datahi, rbase, TCG_REG_R0));
1799 } else if (rbase != 0) {
1800 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
1801 tcg_out32(s, LWZX | TAB(datahi, rbase, addrlo));
1802 tcg_out32(s, LWZX | TAB(datalo, rbase, TCG_REG_R0));
1803 } else if (addrlo == datahi) {
1804 tcg_out32(s, LWZ | TAI(datalo, addrlo, 4));
1805 tcg_out32(s, LWZ | TAI(datahi, addrlo, 0));
1806 } else {
1807 tcg_out32(s, LWZ | TAI(datahi, addrlo, 0));
1808 tcg_out32(s, LWZ | TAI(datalo, addrlo, 4));
1809 }
1810 } else {
1811 uint32_t insn = qemu_ldx_opc[opc & (MO_BSWAP | MO_SSIZE)];
1812 if (!HAVE_ISA_2_06 && insn == LDBRX) {
1813 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
1814 tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo));
1815 tcg_out32(s, LWBRX | TAB(TCG_REG_R0, rbase, TCG_REG_R0));
1816 tcg_out_rld(s, RLDIMI, datalo, TCG_REG_R0, 32, 0);
1817 } else if (insn) {
1818 tcg_out32(s, insn | TAB(datalo, rbase, addrlo));
1819 } else {
1820 insn = qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)];
1821 tcg_out32(s, insn | TAB(datalo, rbase, addrlo));
1822 insn = qemu_exts_opc[s_bits];
1823 tcg_out32(s, insn | RA(datalo) | RS(datalo));
1824 }
1825 }
1826
1827 #ifdef CONFIG_SOFTMMU
1828 add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi,
1829 s->code_ptr, label_ptr);
1830 #endif
1831 }
1832
1833 static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
1834 {
1835 TCGReg datalo, datahi, addrlo, rbase;
1836 TCGReg addrhi __attribute__((unused));
1837 TCGMemOpIdx oi;
1838 TCGMemOp opc, s_bits;
1839 #ifdef CONFIG_SOFTMMU
1840 int mem_index;
1841 tcg_insn_unit *label_ptr;
1842 #endif
1843
1844 datalo = *args++;
1845 datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
1846 addrlo = *args++;
1847 addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
1848 oi = *args++;
1849 opc = get_memop(oi);
1850 s_bits = opc & MO_SIZE;
1851
1852 #ifdef CONFIG_SOFTMMU
1853 mem_index = get_mmuidx(oi);
1854 addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, false);
1855
1856 /* Load a pointer into the current opcode w/conditional branch-link. */
1857 label_ptr = s->code_ptr;
1858 tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
1859
1860 rbase = TCG_REG_R3;
1861 #else /* !CONFIG_SOFTMMU */
1862 rbase = guest_base ? TCG_GUEST_BASE_REG : 0;
1863 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1864 tcg_out_ext32u(s, TCG_REG_TMP1, addrlo);
1865 addrlo = TCG_REG_TMP1;
1866 }
1867 #endif
1868
1869 if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {
1870 if (opc & MO_BSWAP) {
1871 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
1872 tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo));
1873 tcg_out32(s, STWBRX | SAB(datahi, rbase, TCG_REG_R0));
1874 } else if (rbase != 0) {
1875 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
1876 tcg_out32(s, STWX | SAB(datahi, rbase, addrlo));
1877 tcg_out32(s, STWX | SAB(datalo, rbase, TCG_REG_R0));
1878 } else {
1879 tcg_out32(s, STW | TAI(datahi, addrlo, 0));
1880 tcg_out32(s, STW | TAI(datalo, addrlo, 4));
1881 }
1882 } else {
1883 uint32_t insn = qemu_stx_opc[opc & (MO_BSWAP | MO_SIZE)];
1884 if (!HAVE_ISA_2_06 && insn == STDBRX) {
1885 tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo));
1886 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, addrlo, 4));
1887 tcg_out_shri64(s, TCG_REG_R0, datalo, 32);
1888 tcg_out32(s, STWBRX | SAB(TCG_REG_R0, rbase, TCG_REG_TMP1));
1889 } else {
1890 tcg_out32(s, insn | SAB(datalo, rbase, addrlo));
1891 }
1892 }
1893
1894 #ifdef CONFIG_SOFTMMU
1895 add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi,
1896 s->code_ptr, label_ptr);
1897 #endif
1898 }
1899
1900 static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
1901 {
1902 int i;
1903 for (i = 0; i < count; ++i) {
1904 p[i] = NOP;
1905 }
1906 }
1907
1908 /* Parameters for function call generation, used in tcg.c. */
1909 #define TCG_TARGET_STACK_ALIGN 16
1910 #define TCG_TARGET_EXTEND_ARGS 1
1911
1912 #ifdef _CALL_AIX
1913 # define LINK_AREA_SIZE (6 * SZR)
1914 # define LR_OFFSET (1 * SZR)
1915 # define TCG_TARGET_CALL_STACK_OFFSET (LINK_AREA_SIZE + 8 * SZR)
1916 #elif defined(TCG_TARGET_CALL_DARWIN)
1917 # define LINK_AREA_SIZE (6 * SZR)
1918 # define LR_OFFSET (2 * SZR)
1919 #elif TCG_TARGET_REG_BITS == 64
1920 # if defined(_CALL_ELF) && _CALL_ELF == 2
1921 # define LINK_AREA_SIZE (4 * SZR)
1922 # define LR_OFFSET (1 * SZR)
1923 # endif
1924 #else /* TCG_TARGET_REG_BITS == 32 */
1925 # if defined(_CALL_SYSV)
1926 # define LINK_AREA_SIZE (2 * SZR)
1927 # define LR_OFFSET (1 * SZR)
1928 # endif
1929 #endif
1930 #ifndef LR_OFFSET
1931 # error "Unhandled abi"
1932 #endif
1933 #ifndef TCG_TARGET_CALL_STACK_OFFSET
1934 # define TCG_TARGET_CALL_STACK_OFFSET LINK_AREA_SIZE
1935 #endif
1936
1937 #define CPU_TEMP_BUF_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
1938 #define REG_SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * SZR)
1939
1940 #define FRAME_SIZE ((TCG_TARGET_CALL_STACK_OFFSET \
1941 + TCG_STATIC_CALL_ARGS_SIZE \
1942 + CPU_TEMP_BUF_SIZE \
1943 + REG_SAVE_SIZE \
1944 + TCG_TARGET_STACK_ALIGN - 1) \
1945 & -TCG_TARGET_STACK_ALIGN)
1946
1947 #define REG_SAVE_BOT (FRAME_SIZE - REG_SAVE_SIZE)
1948
1949 static void tcg_target_qemu_prologue(TCGContext *s)
1950 {
1951 int i;
1952
1953 #ifdef _CALL_AIX
1954 void **desc = (void **)s->code_ptr;
1955 desc[0] = desc + 2; /* entry point */
1956 desc[1] = 0; /* environment pointer */
1957 s->code_ptr = (void *)(desc + 2); /* skip over descriptor */
1958 #endif
1959
1960 tcg_set_frame(s, TCG_REG_CALL_STACK, REG_SAVE_BOT - CPU_TEMP_BUF_SIZE,
1961 CPU_TEMP_BUF_SIZE);
1962
1963 /* Prologue */
1964 tcg_out32(s, MFSPR | RT(TCG_REG_R0) | LR);
1965 tcg_out32(s, (SZR == 8 ? STDU : STWU)
1966 | SAI(TCG_REG_R1, TCG_REG_R1, -FRAME_SIZE));
1967
1968 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
1969 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
1970 TCG_REG_R1, REG_SAVE_BOT + i * SZR);
1971 }
1972 tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET);
1973
1974 #ifndef CONFIG_SOFTMMU
1975 if (guest_base) {
1976 tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, true);
1977 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
1978 }
1979 #endif
1980
1981 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
1982 tcg_out32(s, MTSPR | RS(tcg_target_call_iarg_regs[1]) | CTR);
1983 if (USE_REG_TB) {
1984 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]);
1985 }
1986 tcg_out32(s, BCCTR | BO_ALWAYS);
1987
1988 /* Epilogue */
1989 s->code_gen_epilogue = tb_ret_addr = s->code_ptr;
1990
1991 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET);
1992 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
1993 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
1994 TCG_REG_R1, REG_SAVE_BOT + i * SZR);
1995 }
1996 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | LR);
1997 tcg_out32(s, ADDI | TAI(TCG_REG_R1, TCG_REG_R1, FRAME_SIZE));
1998 tcg_out32(s, BCLR | BO_ALWAYS);
1999 }
2000
2001 static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
2002 const int *const_args)
2003 {
2004 TCGArg a0, a1, a2;
2005 int c;
2006
2007 switch (opc) {
2008 case INDEX_op_exit_tb:
2009 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, args[0]);
2010 tcg_out_b(s, 0, tb_ret_addr);
2011 break;
2012 case INDEX_op_goto_tb:
2013 if (s->tb_jmp_insn_offset) {
2014 /* Direct jump. */
2015 if (TCG_TARGET_REG_BITS == 64) {
2016 /* Ensure the next insns are 8-byte aligned. */
2017 if ((uintptr_t)s->code_ptr & 7) {
2018 tcg_out32(s, NOP);
2019 }
2020 s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s);
2021 tcg_out32(s, ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, 0));
2022 tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, 0));
2023 } else {
2024 s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s);
2025 tcg_out32(s, B);
2026 s->tb_jmp_reset_offset[args[0]] = tcg_current_code_size(s);
2027 break;
2028 }
2029 } else {
2030 /* Indirect jump. */
2031 tcg_debug_assert(s->tb_jmp_insn_offset == NULL);
2032 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TB, 0,
2033 (intptr_t)(s->tb_jmp_insn_offset + args[0]));
2034 }
2035 tcg_out32(s, MTSPR | RS(TCG_REG_TB) | CTR);
2036 tcg_out32(s, BCCTR | BO_ALWAYS);
2037 set_jmp_reset_offset(s, args[0]);
2038 if (USE_REG_TB) {
2039 /* For the unlinked case, need to reset TCG_REG_TB. */
2040 c = -tcg_current_code_size(s);
2041 assert(c == (int16_t)c);
2042 tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, c));
2043 }
2044 break;
2045 case INDEX_op_goto_ptr:
2046 tcg_out32(s, MTSPR | RS(args[0]) | CTR);
2047 if (USE_REG_TB) {
2048 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, args[0]);
2049 }
2050 tcg_out32(s, ADDI | TAI(TCG_REG_R3, 0, 0));
2051 tcg_out32(s, BCCTR | BO_ALWAYS);
2052 break;
2053 case INDEX_op_br:
2054 {
2055 TCGLabel *l = arg_label(args[0]);
2056 uint32_t insn = B;
2057
2058 if (l->has_value) {
2059 insn |= reloc_pc24_val(s->code_ptr, l->u.value_ptr);
2060 } else {
2061 tcg_out_reloc(s, s->code_ptr, R_PPC_REL24, l, 0);
2062 }
2063 tcg_out32(s, insn);
2064 }
2065 break;
2066 case INDEX_op_ld8u_i32:
2067 case INDEX_op_ld8u_i64:
2068 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
2069 break;
2070 case INDEX_op_ld8s_i32:
2071 case INDEX_op_ld8s_i64:
2072 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
2073 tcg_out32(s, EXTSB | RS(args[0]) | RA(args[0]));
2074 break;
2075 case INDEX_op_ld16u_i32:
2076 case INDEX_op_ld16u_i64:
2077 tcg_out_mem_long(s, LHZ, LHZX, args[0], args[1], args[2]);
2078 break;
2079 case INDEX_op_ld16s_i32:
2080 case INDEX_op_ld16s_i64:
2081 tcg_out_mem_long(s, LHA, LHAX, args[0], args[1], args[2]);
2082 break;
2083 case INDEX_op_ld_i32:
2084 case INDEX_op_ld32u_i64:
2085 tcg_out_mem_long(s, LWZ, LWZX, args[0], args[1], args[2]);
2086 break;
2087 case INDEX_op_ld32s_i64:
2088 tcg_out_mem_long(s, LWA, LWAX, args[0], args[1], args[2]);
2089 break;
2090 case INDEX_op_ld_i64:
2091 tcg_out_mem_long(s, LD, LDX, args[0], args[1], args[2]);
2092 break;
2093 case INDEX_op_st8_i32:
2094 case INDEX_op_st8_i64:
2095 tcg_out_mem_long(s, STB, STBX, args[0], args[1], args[2]);
2096 break;
2097 case INDEX_op_st16_i32:
2098 case INDEX_op_st16_i64:
2099 tcg_out_mem_long(s, STH, STHX, args[0], args[1], args[2]);
2100 break;
2101 case INDEX_op_st_i32:
2102 case INDEX_op_st32_i64:
2103 tcg_out_mem_long(s, STW, STWX, args[0], args[1], args[2]);
2104 break;
2105 case INDEX_op_st_i64:
2106 tcg_out_mem_long(s, STD, STDX, args[0], args[1], args[2]);
2107 break;
2108
2109 case INDEX_op_add_i32:
2110 a0 = args[0], a1 = args[1], a2 = args[2];
2111 if (const_args[2]) {
2112 do_addi_32:
2113 tcg_out_mem_long(s, ADDI, ADD, a0, a1, (int32_t)a2);
2114 } else {
2115 tcg_out32(s, ADD | TAB(a0, a1, a2));
2116 }
2117 break;
2118 case INDEX_op_sub_i32:
2119 a0 = args[0], a1 = args[1], a2 = args[2];
2120 if (const_args[1]) {
2121 if (const_args[2]) {
2122 tcg_out_movi(s, TCG_TYPE_I32, a0, a1 - a2);
2123 } else {
2124 tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
2125 }
2126 } else if (const_args[2]) {
2127 a2 = -a2;
2128 goto do_addi_32;
2129 } else {
2130 tcg_out32(s, SUBF | TAB(a0, a2, a1));
2131 }
2132 break;
2133
2134 case INDEX_op_and_i32:
2135 a0 = args[0], a1 = args[1], a2 = args[2];
2136 if (const_args[2]) {
2137 tcg_out_andi32(s, a0, a1, a2);
2138 } else {
2139 tcg_out32(s, AND | SAB(a1, a0, a2));
2140 }
2141 break;
2142 case INDEX_op_and_i64:
2143 a0 = args[0], a1 = args[1], a2 = args[2];
2144 if (const_args[2]) {
2145 tcg_out_andi64(s, a0, a1, a2);
2146 } else {
2147 tcg_out32(s, AND | SAB(a1, a0, a2));
2148 }
2149 break;
2150 case INDEX_op_or_i64:
2151 case INDEX_op_or_i32:
2152 a0 = args[0], a1 = args[1], a2 = args[2];
2153 if (const_args[2]) {
2154 tcg_out_ori32(s, a0, a1, a2);
2155 } else {
2156 tcg_out32(s, OR | SAB(a1, a0, a2));
2157 }
2158 break;
2159 case INDEX_op_xor_i64:
2160 case INDEX_op_xor_i32:
2161 a0 = args[0], a1 = args[1], a2 = args[2];
2162 if (const_args[2]) {
2163 tcg_out_xori32(s, a0, a1, a2);
2164 } else {
2165 tcg_out32(s, XOR | SAB(a1, a0, a2));
2166 }
2167 break;
2168 case INDEX_op_andc_i32:
2169 a0 = args[0], a1 = args[1], a2 = args[2];
2170 if (const_args[2]) {
2171 tcg_out_andi32(s, a0, a1, ~a2);
2172 } else {
2173 tcg_out32(s, ANDC | SAB(a1, a0, a2));
2174 }
2175 break;
2176 case INDEX_op_andc_i64:
2177 a0 = args[0], a1 = args[1], a2 = args[2];
2178 if (const_args[2]) {
2179 tcg_out_andi64(s, a0, a1, ~a2);
2180 } else {
2181 tcg_out32(s, ANDC | SAB(a1, a0, a2));
2182 }
2183 break;
2184 case INDEX_op_orc_i32:
2185 if (const_args[2]) {
2186 tcg_out_ori32(s, args[0], args[1], ~args[2]);
2187 break;
2188 }
2189 /* FALLTHRU */
2190 case INDEX_op_orc_i64:
2191 tcg_out32(s, ORC | SAB(args[1], args[0], args[2]));
2192 break;
2193 case INDEX_op_eqv_i32:
2194 if (const_args[2]) {
2195 tcg_out_xori32(s, args[0], args[1], ~args[2]);
2196 break;
2197 }
2198 /* FALLTHRU */
2199 case INDEX_op_eqv_i64:
2200 tcg_out32(s, EQV | SAB(args[1], args[0], args[2]));
2201 break;
2202 case INDEX_op_nand_i32:
2203 case INDEX_op_nand_i64:
2204 tcg_out32(s, NAND | SAB(args[1], args[0], args[2]));
2205 break;
2206 case INDEX_op_nor_i32:
2207 case INDEX_op_nor_i64:
2208 tcg_out32(s, NOR | SAB(args[1], args[0], args[2]));
2209 break;
2210
2211 case INDEX_op_clz_i32:
2212 tcg_out_cntxz(s, TCG_TYPE_I32, CNTLZW, args[0], args[1],
2213 args[2], const_args[2]);
2214 break;
2215 case INDEX_op_ctz_i32:
2216 tcg_out_cntxz(s, TCG_TYPE_I32, CNTTZW, args[0], args[1],
2217 args[2], const_args[2]);
2218 break;
2219 case INDEX_op_ctpop_i32:
2220 tcg_out32(s, CNTPOPW | SAB(args[1], args[0], 0));
2221 break;
2222
2223 case INDEX_op_clz_i64:
2224 tcg_out_cntxz(s, TCG_TYPE_I64, CNTLZD, args[0], args[1],
2225 args[2], const_args[2]);
2226 break;
2227 case INDEX_op_ctz_i64:
2228 tcg_out_cntxz(s, TCG_TYPE_I64, CNTTZD, args[0], args[1],
2229 args[2], const_args[2]);
2230 break;
2231 case INDEX_op_ctpop_i64:
2232 tcg_out32(s, CNTPOPD | SAB(args[1], args[0], 0));
2233 break;
2234
2235 case INDEX_op_mul_i32:
2236 a0 = args[0], a1 = args[1], a2 = args[2];
2237 if (const_args[2]) {
2238 tcg_out32(s, MULLI | TAI(a0, a1, a2));
2239 } else {
2240 tcg_out32(s, MULLW | TAB(a0, a1, a2));
2241 }
2242 break;
2243
2244 case INDEX_op_div_i32:
2245 tcg_out32(s, DIVW | TAB(args[0], args[1], args[2]));
2246 break;
2247
2248 case INDEX_op_divu_i32:
2249 tcg_out32(s, DIVWU | TAB(args[0], args[1], args[2]));
2250 break;
2251
2252 case INDEX_op_shl_i32:
2253 if (const_args[2]) {
2254 tcg_out_shli32(s, args[0], args[1], args[2]);
2255 } else {
2256 tcg_out32(s, SLW | SAB(args[1], args[0], args[2]));
2257 }
2258 break;
2259 case INDEX_op_shr_i32:
2260 if (const_args[2]) {
2261 tcg_out_shri32(s, args[0], args[1], args[2]);
2262 } else {
2263 tcg_out32(s, SRW | SAB(args[1], args[0], args[2]));
2264 }
2265 break;
2266 case INDEX_op_sar_i32:
2267 if (const_args[2]) {
2268 tcg_out32(s, SRAWI | RS(args[1]) | RA(args[0]) | SH(args[2]));
2269 } else {
2270 tcg_out32(s, SRAW | SAB(args[1], args[0], args[2]));
2271 }
2272 break;
2273 case INDEX_op_rotl_i32:
2274 if (const_args[2]) {
2275 tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31);
2276 } else {
2277 tcg_out32(s, RLWNM | SAB(args[1], args[0], args[2])
2278 | MB(0) | ME(31));
2279 }
2280 break;
2281 case INDEX_op_rotr_i32:
2282 if (const_args[2]) {
2283 tcg_out_rlw(s, RLWINM, args[0], args[1], 32 - args[2], 0, 31);
2284 } else {
2285 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 32));
2286 tcg_out32(s, RLWNM | SAB(args[1], args[0], TCG_REG_R0)
2287 | MB(0) | ME(31));
2288 }
2289 break;
2290
2291 case INDEX_op_brcond_i32:
2292 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
2293 arg_label(args[3]), TCG_TYPE_I32);
2294 break;
2295 case INDEX_op_brcond_i64:
2296 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
2297 arg_label(args[3]), TCG_TYPE_I64);
2298 break;
2299 case INDEX_op_brcond2_i32:
2300 tcg_out_brcond2(s, args, const_args);
2301 break;
2302
2303 case INDEX_op_neg_i32:
2304 case INDEX_op_neg_i64:
2305 tcg_out32(s, NEG | RT(args[0]) | RA(args[1]));
2306 break;
2307
2308 case INDEX_op_not_i32:
2309 case INDEX_op_not_i64:
2310 tcg_out32(s, NOR | SAB(args[1], args[0], args[1]));
2311 break;
2312
2313 case INDEX_op_add_i64:
2314 a0 = args[0], a1 = args[1], a2 = args[2];
2315 if (const_args[2]) {
2316 do_addi_64:
2317 tcg_out_mem_long(s, ADDI, ADD, a0, a1, a2);
2318 } else {
2319 tcg_out32(s, ADD | TAB(a0, a1, a2));
2320 }
2321 break;
2322 case INDEX_op_sub_i64:
2323 a0 = args[0], a1 = args[1], a2 = args[2];
2324 if (const_args[1]) {
2325 if (const_args[2]) {
2326 tcg_out_movi(s, TCG_TYPE_I64, a0, a1 - a2);
2327 } else {
2328 tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
2329 }
2330 } else if (const_args[2]) {
2331 a2 = -a2;
2332 goto do_addi_64;
2333 } else {
2334 tcg_out32(s, SUBF | TAB(a0, a2, a1));
2335 }
2336 break;
2337
2338 case INDEX_op_shl_i64:
2339 if (const_args[2]) {
2340 tcg_out_shli64(s, args[0], args[1], args[2]);
2341 } else {
2342 tcg_out32(s, SLD | SAB(args[1], args[0], args[2]));
2343 }
2344 break;
2345 case INDEX_op_shr_i64:
2346 if (const_args[2]) {
2347 tcg_out_shri64(s, args[0], args[1], args[2]);
2348 } else {
2349 tcg_out32(s, SRD | SAB(args[1], args[0], args[2]));
2350 }
2351 break;
2352 case INDEX_op_sar_i64:
2353 if (const_args[2]) {
2354 int sh = SH(args[2] & 0x1f) | (((args[2] >> 5) & 1) << 1);
2355 tcg_out32(s, SRADI | RA(args[0]) | RS(args[1]) | sh);
2356 } else {
2357 tcg_out32(s, SRAD | SAB(args[1], args[0], args[2]));
2358 }
2359 break;
2360 case INDEX_op_rotl_i64:
2361 if (const_args[2]) {
2362 tcg_out_rld(s, RLDICL, args[0], args[1], args[2], 0);
2363 } else {
2364 tcg_out32(s, RLDCL | SAB(args[1], args[0], args[2]) | MB64(0));
2365 }
2366 break;
2367 case INDEX_op_rotr_i64:
2368 if (const_args[2]) {
2369 tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 0);
2370 } else {
2371 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 64));
2372 tcg_out32(s, RLDCL | SAB(args[1], args[0], TCG_REG_R0) | MB64(0));
2373 }
2374 break;
2375
2376 case INDEX_op_mul_i64:
2377 a0 = args[0], a1 = args[1], a2 = args[2];
2378 if (const_args[2]) {
2379 tcg_out32(s, MULLI | TAI(a0, a1, a2));
2380 } else {
2381 tcg_out32(s, MULLD | TAB(a0, a1, a2));
2382 }
2383 break;
2384 case INDEX_op_div_i64:
2385 tcg_out32(s, DIVD | TAB(args[0], args[1], args[2]));
2386 break;
2387 case INDEX_op_divu_i64:
2388 tcg_out32(s, DIVDU | TAB(args[0], args[1], args[2]));
2389 break;
2390
2391 case INDEX_op_qemu_ld_i32:
2392 tcg_out_qemu_ld(s, args, false);
2393 break;
2394 case INDEX_op_qemu_ld_i64:
2395 tcg_out_qemu_ld(s, args, true);
2396 break;
2397 case INDEX_op_qemu_st_i32:
2398 tcg_out_qemu_st(s, args, false);
2399 break;
2400 case INDEX_op_qemu_st_i64:
2401 tcg_out_qemu_st(s, args, true);
2402 break;
2403
2404 case INDEX_op_ext8s_i32:
2405 case INDEX_op_ext8s_i64:
2406 c = EXTSB;
2407 goto gen_ext;
2408 case INDEX_op_ext16s_i32:
2409 case INDEX_op_ext16s_i64:
2410 c = EXTSH;
2411 goto gen_ext;
2412 case INDEX_op_ext_i32_i64:
2413 case INDEX_op_ext32s_i64:
2414 c = EXTSW;
2415 goto gen_ext;
2416 gen_ext:
2417 tcg_out32(s, c | RS(args[1]) | RA(args[0]));
2418 break;
2419 case INDEX_op_extu_i32_i64:
2420 tcg_out_ext32u(s, args[0], args[1]);
2421 break;
2422
2423 case INDEX_op_setcond_i32:
2424 tcg_out_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], args[2],
2425 const_args[2]);
2426 break;
2427 case INDEX_op_setcond_i64:
2428 tcg_out_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], args[2],
2429 const_args[2]);
2430 break;
2431 case INDEX_op_setcond2_i32:
2432 tcg_out_setcond2(s, args, const_args);
2433 break;
2434
2435 case INDEX_op_bswap16_i32:
2436 case INDEX_op_bswap16_i64:
2437 a0 = args[0], a1 = args[1];
2438 /* a1 = abcd */
2439 if (a0 != a1) {
2440 /* a0 = (a1 r<< 24) & 0xff # 000c */
2441 tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
2442 /* a0 = (a0 & ~0xff00) | (a1 r<< 8) & 0xff00 # 00dc */
2443 tcg_out_rlw(s, RLWIMI, a0, a1, 8, 16, 23);
2444 } else {
2445 /* r0 = (a1 r<< 8) & 0xff00 # 00d0 */
2446 tcg_out_rlw(s, RLWINM, TCG_REG_R0, a1, 8, 16, 23);
2447 /* a0 = (a1 r<< 24) & 0xff # 000c */
2448 tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
2449 /* a0 = a0 | r0 # 00dc */
2450 tcg_out32(s, OR | SAB(TCG_REG_R0, a0, a0));
2451 }
2452 break;
2453
2454 case INDEX_op_bswap32_i32:
2455 case INDEX_op_bswap32_i64:
2456 /* Stolen from gcc's builtin_bswap32 */
2457 a1 = args[1];
2458 a0 = args[0] == a1 ? TCG_REG_R0 : args[0];
2459
2460 /* a1 = args[1] # abcd */
2461 /* a0 = rotate_left (a1, 8) # bcda */
2462 tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
2463 /* a0 = (a0 & ~0xff000000) | ((a1 r<< 24) & 0xff000000) # dcda */
2464 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
2465 /* a0 = (a0 & ~0x0000ff00) | ((a1 r<< 24) & 0x0000ff00) # dcba */
2466 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
2467
2468 if (a0 == TCG_REG_R0) {
2469 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
2470 }
2471 break;
2472
2473 case INDEX_op_bswap64_i64:
2474 a0 = args[0], a1 = args[1], a2 = TCG_REG_R0;
2475 if (a0 == a1) {
2476 a0 = TCG_REG_R0;
2477 a2 = a1;
2478 }
2479
2480 /* a1 = # abcd efgh */
2481 /* a0 = rl32(a1, 8) # 0000 fghe */
2482 tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
2483 /* a0 = dep(a0, rl32(a1, 24), 0xff000000) # 0000 hghe */
2484 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
2485 /* a0 = dep(a0, rl32(a1, 24), 0x0000ff00) # 0000 hgfe */
2486 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
2487
2488 /* a0 = rl64(a0, 32) # hgfe 0000 */
2489 /* a2 = rl64(a1, 32) # efgh abcd */
2490 tcg_out_rld(s, RLDICL, a0, a0, 32, 0);
2491 tcg_out_rld(s, RLDICL, a2, a1, 32, 0);
2492
2493 /* a0 = dep(a0, rl32(a2, 8), 0xffffffff) # hgfe bcda */
2494 tcg_out_rlw(s, RLWIMI, a0, a2, 8, 0, 31);
2495 /* a0 = dep(a0, rl32(a2, 24), 0xff000000) # hgfe dcda */
2496 tcg_out_rlw(s, RLWIMI, a0, a2, 24, 0, 7);
2497 /* a0 = dep(a0, rl32(a2, 24), 0x0000ff00) # hgfe dcba */
2498 tcg_out_rlw(s, RLWIMI, a0, a2, 24, 16, 23);
2499
2500 if (a0 == 0) {
2501 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
2502 }
2503 break;
2504
2505 case INDEX_op_deposit_i32:
2506 if (const_args[2]) {
2507 uint32_t mask = ((2u << (args[4] - 1)) - 1) << args[3];
2508 tcg_out_andi32(s, args[0], args[0], ~mask);
2509 } else {
2510 tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3],
2511 32 - args[3] - args[4], 31 - args[3]);
2512 }
2513 break;
2514 case INDEX_op_deposit_i64:
2515 if (const_args[2]) {
2516 uint64_t mask = ((2ull << (args[4] - 1)) - 1) << args[3];
2517 tcg_out_andi64(s, args[0], args[0], ~mask);
2518 } else {
2519 tcg_out_rld(s, RLDIMI, args[0], args[2], args[3],
2520 64 - args[3] - args[4]);
2521 }
2522 break;
2523
2524 case INDEX_op_extract_i32:
2525 tcg_out_rlw(s, RLWINM, args[0], args[1],
2526 32 - args[2], 32 - args[3], 31);
2527 break;
2528 case INDEX_op_extract_i64:
2529 tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 64 - args[3]);
2530 break;
2531
2532 case INDEX_op_movcond_i32:
2533 tcg_out_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], args[2],
2534 args[3], args[4], const_args[2]);
2535 break;
2536 case INDEX_op_movcond_i64:
2537 tcg_out_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], args[2],
2538 args[3], args[4], const_args[2]);
2539 break;
2540
2541 #if TCG_TARGET_REG_BITS == 64
2542 case INDEX_op_add2_i64:
2543 #else
2544 case INDEX_op_add2_i32:
2545 #endif
2546 /* Note that the CA bit is defined based on the word size of the
2547 environment. So in 64-bit mode it's always carry-out of bit 63.
2548 The fallback code using deposit works just as well for 32-bit. */
2549 a0 = args[0], a1 = args[1];
2550 if (a0 == args[3] || (!const_args[5] && a0 == args[5])) {
2551 a0 = TCG_REG_R0;
2552 }
2553 if (const_args[4]) {
2554 tcg_out32(s, ADDIC | TAI(a0, args[2], args[4]));
2555 } else {
2556 tcg_out32(s, ADDC | TAB(a0, args[2], args[4]));
2557 }
2558 if (const_args[5]) {
2559 tcg_out32(s, (args[5] ? ADDME : ADDZE) | RT(a1) | RA(args[3]));
2560 } else {
2561 tcg_out32(s, ADDE | TAB(a1, args[3], args[5]));
2562 }
2563 if (a0 != args[0]) {
2564 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
2565 }
2566 break;
2567
2568 #if TCG_TARGET_REG_BITS == 64
2569 case INDEX_op_sub2_i64:
2570 #else
2571 case INDEX_op_sub2_i32:
2572 #endif
2573 a0 = args[0], a1 = args[1];
2574 if (a0 == args[5] || (!const_args[3] && a0 == args[3])) {
2575 a0 = TCG_REG_R0;
2576 }
2577 if (const_args[2]) {
2578 tcg_out32(s, SUBFIC | TAI(a0, args[4], args[2]));
2579 } else {
2580 tcg_out32(s, SUBFC | TAB(a0, args[4], args[2]));
2581 }
2582 if (const_args[3]) {
2583 tcg_out32(s, (args[3] ? SUBFME : SUBFZE) | RT(a1) | RA(args[5]));
2584 } else {
2585 tcg_out32(s, SUBFE | TAB(a1, args[5], args[3]));
2586 }
2587 if (a0 != args[0]) {
2588 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
2589 }
2590 break;
2591
2592 case INDEX_op_muluh_i32:
2593 tcg_out32(s, MULHWU | TAB(args[0], args[1], args[2]));
2594 break;
2595 case INDEX_op_mulsh_i32:
2596 tcg_out32(s, MULHW | TAB(args[0], args[1], args[2]));
2597 break;
2598 case INDEX_op_muluh_i64:
2599 tcg_out32(s, MULHDU | TAB(args[0], args[1], args[2]));
2600 break;
2601 case INDEX_op_mulsh_i64:
2602 tcg_out32(s, MULHD | TAB(args[0], args[1], args[2]));
2603 break;
2604
2605 case INDEX_op_mb:
2606 tcg_out_mb(s, args[0]);
2607 break;
2608
2609 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
2610 case INDEX_op_mov_i64:
2611 case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
2612 case INDEX_op_movi_i64:
2613 case INDEX_op_call: /* Always emitted via tcg_out_call. */
2614 default:
2615 tcg_abort();
2616 }
2617 }
2618
2619 static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
2620 {
2621 static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
2622 static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
2623 static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
2624 static const TCGTargetOpDef S_S = { .args_ct_str = { "S", "S" } };
2625 static const TCGTargetOpDef r_ri = { .args_ct_str = { "r", "ri" } };
2626 static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } };
2627 static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } };
2628 static const TCGTargetOpDef L_L_L = { .args_ct_str = { "L", "L", "L" } };
2629 static const TCGTargetOpDef S_S_S = { .args_ct_str = { "S", "S", "S" } };
2630 static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
2631 static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } };
2632 static const TCGTargetOpDef r_r_rT = { .args_ct_str = { "r", "r", "rT" } };
2633 static const TCGTargetOpDef r_r_rU = { .args_ct_str = { "r", "r", "rU" } };
2634 static const TCGTargetOpDef r_rI_ri
2635 = { .args_ct_str = { "r", "rI", "ri" } };
2636 static const TCGTargetOpDef r_rI_rT
2637 = { .args_ct_str = { "r", "rI", "rT" } };
2638 static const TCGTargetOpDef r_r_rZW
2639 = { .args_ct_str = { "r", "r", "rZW" } };
2640 static const TCGTargetOpDef L_L_L_L
2641 = { .args_ct_str = { "L", "L", "L", "L" } };
2642 static const TCGTargetOpDef S_S_S_S
2643 = { .args_ct_str = { "S", "S", "S", "S" } };
2644 static const TCGTargetOpDef movc
2645 = { .args_ct_str = { "r", "r", "ri", "rZ", "rZ" } };
2646 static const TCGTargetOpDef dep
2647 = { .args_ct_str = { "r", "0", "rZ" } };
2648 static const TCGTargetOpDef br2
2649 = { .args_ct_str = { "r", "r", "ri", "ri" } };
2650 static const TCGTargetOpDef setc2
2651 = { .args_ct_str = { "r", "r", "r", "ri", "ri" } };
2652 static const TCGTargetOpDef add2
2653 = { .args_ct_str = { "r", "r", "r", "r", "rI", "rZM" } };
2654 static const TCGTargetOpDef sub2
2655 = { .args_ct_str = { "r", "r", "rI", "rZM", "r", "r" } };
2656
2657 switch (op) {
2658 case INDEX_op_goto_ptr:
2659 return &r;
2660
2661 case INDEX_op_ld8u_i32:
2662 case INDEX_op_ld8s_i32:
2663 case INDEX_op_ld16u_i32:
2664 case INDEX_op_ld16s_i32:
2665 case INDEX_op_ld_i32:
2666 case INDEX_op_st8_i32:
2667 case INDEX_op_st16_i32:
2668 case INDEX_op_st_i32:
2669 case INDEX_op_ctpop_i32:
2670 case INDEX_op_neg_i32:
2671 case INDEX_op_not_i32:
2672 case INDEX_op_ext8s_i32:
2673 case INDEX_op_ext16s_i32:
2674 case INDEX_op_bswap16_i32:
2675 case INDEX_op_bswap32_i32:
2676 case INDEX_op_extract_i32:
2677 case INDEX_op_ld8u_i64:
2678 case INDEX_op_ld8s_i64:
2679 case INDEX_op_ld16u_i64:
2680 case INDEX_op_ld16s_i64:
2681 case INDEX_op_ld32u_i64:
2682 case INDEX_op_ld32s_i64:
2683 case INDEX_op_ld_i64:
2684 case INDEX_op_st8_i64:
2685 case INDEX_op_st16_i64:
2686 case INDEX_op_st32_i64:
2687 case INDEX_op_st_i64:
2688 case INDEX_op_ctpop_i64:
2689 case INDEX_op_neg_i64:
2690 case INDEX_op_not_i64:
2691 case INDEX_op_ext8s_i64:
2692 case INDEX_op_ext16s_i64:
2693 case INDEX_op_ext32s_i64:
2694 case INDEX_op_ext_i32_i64:
2695 case INDEX_op_extu_i32_i64:
2696 case INDEX_op_bswap16_i64:
2697 case INDEX_op_bswap32_i64:
2698 case INDEX_op_bswap64_i64:
2699 case INDEX_op_extract_i64:
2700 return &r_r;
2701
2702 case INDEX_op_add_i32:
2703 case INDEX_op_and_i32:
2704 case INDEX_op_or_i32:
2705 case INDEX_op_xor_i32:
2706 case INDEX_op_andc_i32:
2707 case INDEX_op_orc_i32:
2708 case INDEX_op_eqv_i32:
2709 case INDEX_op_shl_i32:
2710 case INDEX_op_shr_i32:
2711 case INDEX_op_sar_i32:
2712 case INDEX_op_rotl_i32:
2713 case INDEX_op_rotr_i32:
2714 case INDEX_op_setcond_i32:
2715 case INDEX_op_and_i64:
2716 case INDEX_op_andc_i64:
2717 case INDEX_op_shl_i64:
2718 case INDEX_op_shr_i64:
2719 case INDEX_op_sar_i64:
2720 case INDEX_op_rotl_i64:
2721 case INDEX_op_rotr_i64:
2722 case INDEX_op_setcond_i64:
2723 return &r_r_ri;
2724 case INDEX_op_mul_i32:
2725 case INDEX_op_mul_i64:
2726 return &r_r_rI;
2727 case INDEX_op_div_i32:
2728 case INDEX_op_divu_i32:
2729 case INDEX_op_nand_i32:
2730 case INDEX_op_nor_i32:
2731 case INDEX_op_muluh_i32:
2732 case INDEX_op_mulsh_i32:
2733 case INDEX_op_orc_i64:
2734 case INDEX_op_eqv_i64:
2735 case INDEX_op_nand_i64:
2736 case INDEX_op_nor_i64:
2737 case INDEX_op_div_i64:
2738 case INDEX_op_divu_i64:
2739 case INDEX_op_mulsh_i64:
2740 case INDEX_op_muluh_i64:
2741 return &r_r_r;
2742 case INDEX_op_sub_i32:
2743 return &r_rI_ri;
2744 case INDEX_op_add_i64:
2745 return &r_r_rT;
2746 case INDEX_op_or_i64:
2747 case INDEX_op_xor_i64:
2748 return &r_r_rU;
2749 case INDEX_op_sub_i64:
2750 return &r_rI_rT;
2751 case INDEX_op_clz_i32:
2752 case INDEX_op_ctz_i32:
2753 case INDEX_op_clz_i64:
2754 case INDEX_op_ctz_i64:
2755 return &r_r_rZW;
2756
2757 case INDEX_op_brcond_i32:
2758 case INDEX_op_brcond_i64:
2759 return &r_ri;
2760
2761 case INDEX_op_movcond_i32:
2762 case INDEX_op_movcond_i64:
2763 return &movc;
2764 case INDEX_op_deposit_i32:
2765 case INDEX_op_deposit_i64:
2766 return &dep;
2767 case INDEX_op_brcond2_i32:
2768 return &br2;
2769 case INDEX_op_setcond2_i32:
2770 return &setc2;
2771 case INDEX_op_add2_i64:
2772 case INDEX_op_add2_i32:
2773 return &add2;
2774 case INDEX_op_sub2_i64:
2775 case INDEX_op_sub2_i32:
2776 return &sub2;
2777
2778 case INDEX_op_qemu_ld_i32:
2779 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
2780 ? &r_L : &r_L_L);
2781 case INDEX_op_qemu_st_i32:
2782 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
2783 ? &S_S : &S_S_S);
2784 case INDEX_op_qemu_ld_i64:
2785 return (TCG_TARGET_REG_BITS == 64 ? &r_L
2786 : TARGET_LONG_BITS == 32 ? &L_L_L : &L_L_L_L);
2787 case INDEX_op_qemu_st_i64:
2788 return (TCG_TARGET_REG_BITS == 64 ? &S_S
2789 : TARGET_LONG_BITS == 32 ? &S_S_S : &S_S_S_S);
2790
2791 default:
2792 return NULL;
2793 }
2794 }
2795
2796 static void tcg_target_init(TCGContext *s)
2797 {
2798 unsigned long hwcap = qemu_getauxval(AT_HWCAP);
2799 unsigned long hwcap2 = qemu_getauxval(AT_HWCAP2);
2800
2801 if (hwcap & PPC_FEATURE_ARCH_2_06) {
2802 have_isa_2_06 = true;
2803 }
2804 #ifdef PPC_FEATURE2_ARCH_3_00
2805 if (hwcap2 & PPC_FEATURE2_ARCH_3_00) {
2806 have_isa_3_00 = true;
2807 }
2808 #endif
2809
2810 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
2811 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
2812
2813 tcg_target_call_clobber_regs = 0;
2814 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0);
2815 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2);
2816 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3);
2817 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R4);
2818 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R5);
2819 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R6);
2820 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R7);
2821 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8);
2822 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9);
2823 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10);
2824 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11);
2825 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12);
2826
2827 s->reserved_regs = 0;
2828 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */
2829 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* stack pointer */
2830 #if defined(_CALL_SYSV)
2831 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* toc pointer */
2832 #endif
2833 #if defined(_CALL_SYSV) || TCG_TARGET_REG_BITS == 64
2834 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */
2835 #endif
2836 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); /* mem temp */
2837 if (USE_REG_TB) {
2838 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tb->tc_ptr */
2839 }
2840 }
2841
2842 #ifdef __ELF__
2843 typedef struct {
2844 DebugFrameCIE cie;
2845 DebugFrameFDEHeader fde;
2846 uint8_t fde_def_cfa[4];
2847 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2 + 3];
2848 } DebugFrame;
2849
2850 /* We're expecting a 2 byte uleb128 encoded value. */
2851 QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14));
2852
2853 #if TCG_TARGET_REG_BITS == 64
2854 # define ELF_HOST_MACHINE EM_PPC64
2855 #else
2856 # define ELF_HOST_MACHINE EM_PPC
2857 #endif
2858
2859 static DebugFrame debug_frame = {
2860 .cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
2861 .cie.id = -1,
2862 .cie.version = 1,
2863 .cie.code_align = 1,
2864 .cie.data_align = (-SZR & 0x7f), /* sleb128 -SZR */
2865 .cie.return_column = 65,
2866
2867 /* Total FDE size does not include the "len" member. */
2868 .fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, fde.cie_offset),
2869
2870 .fde_def_cfa = {
2871 12, TCG_REG_R1, /* DW_CFA_def_cfa r1, ... */
2872 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2873 (FRAME_SIZE >> 7)
2874 },
2875 .fde_reg_ofs = {
2876 /* DW_CFA_offset_extended_sf, lr, LR_OFFSET */
2877 0x11, 65, (LR_OFFSET / -SZR) & 0x7f,
2878 }
2879 };
2880
2881 void tcg_register_jit(void *buf, size_t buf_size)
2882 {
2883 uint8_t *p = &debug_frame.fde_reg_ofs[3];
2884 int i;
2885
2886 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i, p += 2) {
2887 p[0] = 0x80 + tcg_target_callee_save_regs[i];
2888 p[1] = (FRAME_SIZE - (REG_SAVE_BOT + i * SZR)) / SZR;
2889 }
2890
2891 debug_frame.fde.func_start = (uintptr_t)buf;
2892 debug_frame.fde.func_len = buf_size;
2893
2894 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
2895 }
2896 #endif /* __ELF__ */
2897
2898 void flush_icache_range(uintptr_t start, uintptr_t stop)
2899 {
2900 uintptr_t p, start1, stop1;
2901 size_t dsize = qemu_dcache_linesize;
2902 size_t isize = qemu_icache_linesize;
2903
2904 start1 = start & ~(dsize - 1);
2905 stop1 = (stop + dsize - 1) & ~(dsize - 1);
2906 for (p = start1; p < stop1; p += dsize) {
2907 asm volatile ("dcbst 0,%0" : : "r"(p) : "memory");
2908 }
2909 asm volatile ("sync" : : : "memory");
2910
2911 start &= start & ~(isize - 1);
2912 stop1 = (stop + isize - 1) & ~(isize - 1);
2913 for (p = start1; p < stop1; p += isize) {
2914 asm volatile ("icbi 0,%0" : : "r"(p) : "memory");
2915 }
2916 asm volatile ("sync" : : : "memory");
2917 asm volatile ("isync" : : : "memory");
2918 }
AR7 emulation for QEMU