vfio/pci: Cache vendor and device ID
[qemu/ar7.git] / target-arm / machine.c
blob32adfe792e3a87686417533a2cf49465d6d62587
1 #include "hw/hw.h"
2 #include "hw/boards.h"
3 #include "sysemu/kvm.h"
4 #include "kvm_arm.h"
5 #include "internals.h"
7 static bool vfp_needed(void *opaque)
9 ARMCPU *cpu = opaque;
10 CPUARMState *env = &cpu->env;
12 return arm_feature(env, ARM_FEATURE_VFP);
15 static int get_fpscr(QEMUFile *f, void *opaque, size_t size)
17 ARMCPU *cpu = opaque;
18 CPUARMState *env = &cpu->env;
19 uint32_t val = qemu_get_be32(f);
21 vfp_set_fpscr(env, val);
22 return 0;
25 static void put_fpscr(QEMUFile *f, void *opaque, size_t size)
27 ARMCPU *cpu = opaque;
28 CPUARMState *env = &cpu->env;
30 qemu_put_be32(f, vfp_get_fpscr(env));
33 static const VMStateInfo vmstate_fpscr = {
34 .name = "fpscr",
35 .get = get_fpscr,
36 .put = put_fpscr,
39 static const VMStateDescription vmstate_vfp = {
40 .name = "cpu/vfp",
41 .version_id = 3,
42 .minimum_version_id = 3,
43 .needed = vfp_needed,
44 .fields = (VMStateField[]) {
45 VMSTATE_FLOAT64_ARRAY(env.vfp.regs, ARMCPU, 64),
46 /* The xregs array is a little awkward because element 1 (FPSCR)
47 * requires a specific accessor, so we have to split it up in
48 * the vmstate:
50 VMSTATE_UINT32(env.vfp.xregs[0], ARMCPU),
51 VMSTATE_UINT32_SUB_ARRAY(env.vfp.xregs, ARMCPU, 2, 14),
53 .name = "fpscr",
54 .version_id = 0,
55 .size = sizeof(uint32_t),
56 .info = &vmstate_fpscr,
57 .flags = VMS_SINGLE,
58 .offset = 0,
60 VMSTATE_END_OF_LIST()
64 static bool iwmmxt_needed(void *opaque)
66 ARMCPU *cpu = opaque;
67 CPUARMState *env = &cpu->env;
69 return arm_feature(env, ARM_FEATURE_IWMMXT);
72 static const VMStateDescription vmstate_iwmmxt = {
73 .name = "cpu/iwmmxt",
74 .version_id = 1,
75 .minimum_version_id = 1,
76 .needed = iwmmxt_needed,
77 .fields = (VMStateField[]) {
78 VMSTATE_UINT64_ARRAY(env.iwmmxt.regs, ARMCPU, 16),
79 VMSTATE_UINT32_ARRAY(env.iwmmxt.cregs, ARMCPU, 16),
80 VMSTATE_END_OF_LIST()
84 static bool m_needed(void *opaque)
86 ARMCPU *cpu = opaque;
87 CPUARMState *env = &cpu->env;
89 return arm_feature(env, ARM_FEATURE_M);
92 static const VMStateDescription vmstate_m = {
93 .name = "cpu/m",
94 .version_id = 1,
95 .minimum_version_id = 1,
96 .needed = m_needed,
97 .fields = (VMStateField[]) {
98 VMSTATE_UINT32(env.v7m.other_sp, ARMCPU),
99 VMSTATE_UINT32(env.v7m.vecbase, ARMCPU),
100 VMSTATE_UINT32(env.v7m.basepri, ARMCPU),
101 VMSTATE_UINT32(env.v7m.control, ARMCPU),
102 VMSTATE_INT32(env.v7m.current_sp, ARMCPU),
103 VMSTATE_INT32(env.v7m.exception, ARMCPU),
104 VMSTATE_END_OF_LIST()
108 static bool thumb2ee_needed(void *opaque)
110 ARMCPU *cpu = opaque;
111 CPUARMState *env = &cpu->env;
113 return arm_feature(env, ARM_FEATURE_THUMB2EE);
116 static const VMStateDescription vmstate_thumb2ee = {
117 .name = "cpu/thumb2ee",
118 .version_id = 1,
119 .minimum_version_id = 1,
120 .needed = thumb2ee_needed,
121 .fields = (VMStateField[]) {
122 VMSTATE_UINT32(env.teecr, ARMCPU),
123 VMSTATE_UINT32(env.teehbr, ARMCPU),
124 VMSTATE_END_OF_LIST()
128 static bool pmsav7_needed(void *opaque)
130 ARMCPU *cpu = opaque;
131 CPUARMState *env = &cpu->env;
133 return arm_feature(env, ARM_FEATURE_MPU) &&
134 arm_feature(env, ARM_FEATURE_V7);
137 static bool pmsav7_rgnr_vmstate_validate(void *opaque, int version_id)
139 ARMCPU *cpu = opaque;
141 return cpu->env.cp15.c6_rgnr < cpu->pmsav7_dregion;
144 static const VMStateDescription vmstate_pmsav7 = {
145 .name = "cpu/pmsav7",
146 .version_id = 1,
147 .minimum_version_id = 1,
148 .needed = pmsav7_needed,
149 .fields = (VMStateField[]) {
150 VMSTATE_VARRAY_UINT32(env.pmsav7.drbar, ARMCPU, pmsav7_dregion, 0,
151 vmstate_info_uint32, uint32_t),
152 VMSTATE_VARRAY_UINT32(env.pmsav7.drsr, ARMCPU, pmsav7_dregion, 0,
153 vmstate_info_uint32, uint32_t),
154 VMSTATE_VARRAY_UINT32(env.pmsav7.dracr, ARMCPU, pmsav7_dregion, 0,
155 vmstate_info_uint32, uint32_t),
156 VMSTATE_VALIDATE("rgnr is valid", pmsav7_rgnr_vmstate_validate),
157 VMSTATE_END_OF_LIST()
161 static int get_cpsr(QEMUFile *f, void *opaque, size_t size)
163 ARMCPU *cpu = opaque;
164 CPUARMState *env = &cpu->env;
165 uint32_t val = qemu_get_be32(f);
167 env->aarch64 = ((val & PSTATE_nRW) == 0);
169 if (is_a64(env)) {
170 pstate_write(env, val);
171 return 0;
174 /* Avoid mode switch when restoring CPSR */
175 env->uncached_cpsr = val & CPSR_M;
176 cpsr_write(env, val, 0xffffffff);
177 return 0;
180 static void put_cpsr(QEMUFile *f, void *opaque, size_t size)
182 ARMCPU *cpu = opaque;
183 CPUARMState *env = &cpu->env;
184 uint32_t val;
186 if (is_a64(env)) {
187 val = pstate_read(env);
188 } else {
189 val = cpsr_read(env);
192 qemu_put_be32(f, val);
195 static const VMStateInfo vmstate_cpsr = {
196 .name = "cpsr",
197 .get = get_cpsr,
198 .put = put_cpsr,
201 static void cpu_pre_save(void *opaque)
203 ARMCPU *cpu = opaque;
205 if (kvm_enabled()) {
206 if (!write_kvmstate_to_list(cpu)) {
207 /* This should never fail */
208 abort();
210 } else {
211 if (!write_cpustate_to_list(cpu)) {
212 /* This should never fail. */
213 abort();
217 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
218 memcpy(cpu->cpreg_vmstate_indexes, cpu->cpreg_indexes,
219 cpu->cpreg_array_len * sizeof(uint64_t));
220 memcpy(cpu->cpreg_vmstate_values, cpu->cpreg_values,
221 cpu->cpreg_array_len * sizeof(uint64_t));
224 static int cpu_post_load(void *opaque, int version_id)
226 ARMCPU *cpu = opaque;
227 int i, v;
229 /* Update the values list from the incoming migration data.
230 * Anything in the incoming data which we don't know about is
231 * a migration failure; anything we know about but the incoming
232 * data doesn't specify retains its current (reset) value.
233 * The indexes list remains untouched -- we only inspect the
234 * incoming migration index list so we can match the values array
235 * entries with the right slots in our own values array.
238 for (i = 0, v = 0; i < cpu->cpreg_array_len
239 && v < cpu->cpreg_vmstate_array_len; i++) {
240 if (cpu->cpreg_vmstate_indexes[v] > cpu->cpreg_indexes[i]) {
241 /* register in our list but not incoming : skip it */
242 continue;
244 if (cpu->cpreg_vmstate_indexes[v] < cpu->cpreg_indexes[i]) {
245 /* register in their list but not ours: fail migration */
246 return -1;
248 /* matching register, copy the value over */
249 cpu->cpreg_values[i] = cpu->cpreg_vmstate_values[v];
250 v++;
253 if (kvm_enabled()) {
254 if (!write_list_to_kvmstate(cpu, KVM_PUT_FULL_STATE)) {
255 return -1;
257 /* Note that it's OK for the TCG side not to know about
258 * every register in the list; KVM is authoritative if
259 * we're using it.
261 write_list_to_cpustate(cpu);
262 } else {
263 if (!write_list_to_cpustate(cpu)) {
264 return -1;
268 hw_breakpoint_update_all(cpu);
269 hw_watchpoint_update_all(cpu);
271 return 0;
274 const VMStateDescription vmstate_arm_cpu = {
275 .name = "cpu",
276 .version_id = 22,
277 .minimum_version_id = 22,
278 .pre_save = cpu_pre_save,
279 .post_load = cpu_post_load,
280 .fields = (VMStateField[]) {
281 VMSTATE_UINT32_ARRAY(env.regs, ARMCPU, 16),
282 VMSTATE_UINT64_ARRAY(env.xregs, ARMCPU, 32),
283 VMSTATE_UINT64(env.pc, ARMCPU),
285 .name = "cpsr",
286 .version_id = 0,
287 .size = sizeof(uint32_t),
288 .info = &vmstate_cpsr,
289 .flags = VMS_SINGLE,
290 .offset = 0,
292 VMSTATE_UINT32(env.spsr, ARMCPU),
293 VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 8),
294 VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 8),
295 VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 8),
296 VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5),
297 VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5),
298 VMSTATE_UINT64_ARRAY(env.elr_el, ARMCPU, 4),
299 VMSTATE_UINT64_ARRAY(env.sp_el, ARMCPU, 4),
300 /* The length-check must come before the arrays to avoid
301 * incoming data possibly overflowing the array.
303 VMSTATE_INT32_POSITIVE_LE(cpreg_vmstate_array_len, ARMCPU),
304 VMSTATE_VARRAY_INT32(cpreg_vmstate_indexes, ARMCPU,
305 cpreg_vmstate_array_len,
306 0, vmstate_info_uint64, uint64_t),
307 VMSTATE_VARRAY_INT32(cpreg_vmstate_values, ARMCPU,
308 cpreg_vmstate_array_len,
309 0, vmstate_info_uint64, uint64_t),
310 VMSTATE_UINT64(env.exclusive_addr, ARMCPU),
311 VMSTATE_UINT64(env.exclusive_val, ARMCPU),
312 VMSTATE_UINT64(env.exclusive_high, ARMCPU),
313 VMSTATE_UINT64(env.features, ARMCPU),
314 VMSTATE_UINT32(env.exception.syndrome, ARMCPU),
315 VMSTATE_UINT32(env.exception.fsr, ARMCPU),
316 VMSTATE_UINT64(env.exception.vaddress, ARMCPU),
317 VMSTATE_TIMER_PTR(gt_timer[GTIMER_PHYS], ARMCPU),
318 VMSTATE_TIMER_PTR(gt_timer[GTIMER_VIRT], ARMCPU),
319 VMSTATE_BOOL(powered_off, ARMCPU),
320 VMSTATE_END_OF_LIST()
322 .subsections = (const VMStateDescription*[]) {
323 &vmstate_vfp,
324 &vmstate_iwmmxt,
325 &vmstate_m,
326 &vmstate_thumb2ee,
327 &vmstate_pmsav7,
328 NULL