hw/mips/cputimer.c

   1 /*
   2  * QEMU MIPS timer support
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a copy
   5  * of this software and associated documentation files (the "Software"), to deal
   6  * in the Software without restriction, including without limitation the rights
   7  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   8  * copies of the Software, and to permit persons to whom the Software is
   9  * furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  19  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  20  * THE SOFTWARE.
  21  */
  22
  23 #include "hw/hw.h"
  24 #include "hw/mips/cpudevs.h"
  25 #include "qemu/timer.h"
  26 #include "sysemu/kvm.h"
  27
  28 #define TIMER_FREQ      100 * 1000 * 1000
  29
  30 /* XXX: do not use a global */
  31 uint32_t cpu_mips_get_random (CPUMIPSState *env)
  32 {
  33     static uint32_t seed = 1;
  34     static uint32_t prev_idx = 0;
  35     uint32_t idx;
  36     uint32_t nb_rand_tlb = env->tlb->nb_tlb - env->CP0_Wired;
  37
  38     if (nb_rand_tlb == 1) {
  39         return env->tlb->nb_tlb - 1;
  40     }
  41
  42     /* Don't return same value twice, so get another value */
  43     do {
  44         /* Use a simple algorithm of Linear Congruential Generator
  45          * from ISO/IEC 9899 standard. */
  46         seed = 1103515245 * seed + 12345;
  47         idx = (seed >> 16) % nb_rand_tlb + env->CP0_Wired;
  48     } while (idx == prev_idx);
  49     prev_idx = idx;
  50     return idx;
  51 }
  52
  53 /* MIPS R4K timer */
  54 static void cpu_mips_timer_update(CPUMIPSState *env)
  55 {
  56     uint64_t now, next;
  57     uint32_t wait;
  58
  59     now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
  60     wait = env->CP0_Compare - env->CP0_Count -
  61             (uint32_t)muldiv64(now, TIMER_FREQ, get_ticks_per_sec());
  62     next = now + muldiv64(wait, get_ticks_per_sec(), TIMER_FREQ);
  63     timer_mod(env->timer, next);
  64 }
  65
  66 /* Expire the timer.  */
  67 static void cpu_mips_timer_expire(CPUMIPSState *env)
  68 {
  69     cpu_mips_timer_update(env);
  70     if (env->insn_flags & ISA_MIPS32R2) {
  71         env->CP0_Cause |= 1 << CP0Ca_TI;
  72     }
  73     qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
  74 }
  75
  76 uint32_t cpu_mips_get_count (CPUMIPSState *env)
  77 {
  78     if (env->CP0_Cause & (1 << CP0Ca_DC)) {
  79         return env->CP0_Count;
  80     } else {
  81         uint64_t now;
  82
  83         now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
  84         if (timer_pending(env->timer)
  85             && timer_expired(env->timer, now)) {
  86             /* The timer has already expired.  */
  87             cpu_mips_timer_expire(env);
  88         }
  89
  90         return env->CP0_Count +
  91             (uint32_t)muldiv64(now, TIMER_FREQ, get_ticks_per_sec());
  92     }
  93 }
  94
  95 void cpu_mips_store_count (CPUMIPSState *env, uint32_t count)
  96 {
  97     /*
  98      * This gets called from cpu_state_reset(), potentially before timer init.
  99      * So env->timer may be NULL, which is also the case with KVM enabled so
 100      * treat timer as disabled in that case.
 101      */
 102     if (env->CP0_Cause & (1 << CP0Ca_DC) || !env->timer)
 103         env->CP0_Count = count;
 104     else {
 105         /* Store new count register */
 106         env->CP0_Count =
 107             count - (uint32_t)muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
 108                                        TIMER_FREQ, get_ticks_per_sec());
 109         /* Update timer timer */
 110         cpu_mips_timer_update(env);
 111     }
 112 }
 113
 114 void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value)
 115 {
 116     env->CP0_Compare = value;
 117     if (!(env->CP0_Cause & (1 << CP0Ca_DC)))
 118         cpu_mips_timer_update(env);
 119     if (env->insn_flags & ISA_MIPS32R2)
 120         env->CP0_Cause &= ~(1 << CP0Ca_TI);
 121     qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
 122 }
 123
 124 void cpu_mips_start_count(CPUMIPSState *env)
 125 {
 126     cpu_mips_store_count(env, env->CP0_Count);
 127 }
 128
 129 void cpu_mips_stop_count(CPUMIPSState *env)
 130 {
 131     /* Store the current value */
 132     env->CP0_Count += (uint32_t)muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
 133                                          TIMER_FREQ, get_ticks_per_sec());
 134 }
 135
 136 static void mips_timer_cb (void *opaque)
 137 {
 138     CPUMIPSState *env;
 139
 140     env = opaque;
 141 #if 0
 142     qemu_log("%s\n", __func__);
 143 #endif
 144
 145     if (env->CP0_Cause & (1 << CP0Ca_DC))
 146         return;
 147
 148     /* ??? This callback should occur when the counter is exactly equal to
 149        the comparator value.  Offset the count by one to avoid immediately
 150        retriggering the callback before any virtual time has passed.  */
 151     env->CP0_Count++;
 152     cpu_mips_timer_expire(env);
 153     env->CP0_Count--;
 154 }
 155
 156 void cpu_mips_clock_init (CPUMIPSState *env)
 157 {
 158     /*
 159      * If we're in KVM mode, don't create the periodic timer, that is handled in
 160      * kernel.
 161      */
 162     if (!kvm_enabled()) {
 163         env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &mips_timer_cb, env);
 164     }
 165 }