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scsi: esp: check TI buffer index before read/write
[qemu/ar7.git] / tcg / ppc / tcg-target.inc.c
blobda100528ab6f236bf6ab51bcb3e7e0bcbf1c3014
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "tcg-be-ldst.h"
26
27 #if defined _CALL_DARWIN || defined __APPLE__
28 #define TCG_TARGET_CALL_DARWIN
29 #endif
30 #ifdef _CALL_SYSV
31 # define TCG_TARGET_CALL_ALIGN_ARGS 1
32 #endif
33
34 /* For some memory operations, we need a scratch that isn't R0. For the AIX
35 calling convention, we can re-use the TOC register since we'll be reloading
36 it at every call. Otherwise R12 will do nicely as neither a call-saved
37 register nor a parameter register. */
38 #ifdef _CALL_AIX
39 # define TCG_REG_TMP1 TCG_REG_R2
40 #else
41 # define TCG_REG_TMP1 TCG_REG_R12
42 #endif
43
44 /* For the 64-bit target, we don't like the 5 insn sequence needed to build
45 full 64-bit addresses. Better to have a base register to which we can
46 apply a 32-bit displacement.
47
48 There are generally three items of interest:
49 (1) helper functions in the main executable,
50 (2) TranslationBlock data structures,
51 (3) the return address in the epilogue.
52
53 For user-only, we USE_STATIC_CODE_GEN_BUFFER, so the code_gen_buffer
54 will be inside the main executable, and thus near enough to make a
55 pointer to the epilogue be within 2GB of all helper functions.
56
57 For softmmu, we'll let the kernel choose the address of code_gen_buffer,
58 and odds are it'll be somewhere close to the main malloc arena, and so
59 a pointer to the epilogue will be within 2GB of the TranslationBlocks.
60
61 For --enable-pie, everything will be kinda near everything else,
62 somewhere in high memory.
63
64 Thus we choose to keep the return address in a call-saved register. */
65 #define TCG_REG_RA TCG_REG_R31
66 #define USE_REG_RA (TCG_TARGET_REG_BITS == 64)
67
68 /* Shorthand for size of a pointer. Avoid promotion to unsigned. */
69 #define SZP ((int)sizeof(void *))
70
71 /* Shorthand for size of a register. */
72 #define SZR (TCG_TARGET_REG_BITS / 8)
73
74 #define TCG_CT_CONST_S16 0x100
75 #define TCG_CT_CONST_U16 0x200
76 #define TCG_CT_CONST_S32 0x400
77 #define TCG_CT_CONST_U32 0x800
78 #define TCG_CT_CONST_ZERO 0x1000
79 #define TCG_CT_CONST_MONE 0x2000
80
81 static tcg_insn_unit *tb_ret_addr;
82
83 #include "elf.h"
84 static bool have_isa_2_06;
85 #define HAVE_ISA_2_06 have_isa_2_06
86 #define HAVE_ISEL have_isa_2_06
87
88 #ifndef CONFIG_SOFTMMU
89 #define TCG_GUEST_BASE_REG 30
90 #endif
91
92 #ifdef CONFIG_DEBUG_TCG
93 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
94 "r0",
95 "r1",
96 "r2",
97 "r3",
98 "r4",
99 "r5",
100 "r6",
101 "r7",
102 "r8",
103 "r9",
104 "r10",
105 "r11",
106 "r12",
107 "r13",
108 "r14",
109 "r15",
110 "r16",
111 "r17",
112 "r18",
113 "r19",
114 "r20",
115 "r21",
116 "r22",
117 "r23",
118 "r24",
119 "r25",
120 "r26",
121 "r27",
122 "r28",
123 "r29",
124 "r30",
125 "r31"
126 };
127 #endif
128
129 static const int tcg_target_reg_alloc_order[] = {
130 TCG_REG_R14, /* call saved registers */
131 TCG_REG_R15,
132 TCG_REG_R16,
133 TCG_REG_R17,
134 TCG_REG_R18,
135 TCG_REG_R19,
136 TCG_REG_R20,
137 TCG_REG_R21,
138 TCG_REG_R22,
139 TCG_REG_R23,
140 TCG_REG_R24,
141 TCG_REG_R25,
142 TCG_REG_R26,
143 TCG_REG_R27,
144 TCG_REG_R28,
145 TCG_REG_R29,
146 TCG_REG_R30,
147 TCG_REG_R31,
148 TCG_REG_R12, /* call clobbered, non-arguments */
149 TCG_REG_R11,
150 TCG_REG_R2,
151 TCG_REG_R13,
152 TCG_REG_R10, /* call clobbered, arguments */
153 TCG_REG_R9,
154 TCG_REG_R8,
155 TCG_REG_R7,
156 TCG_REG_R6,
157 TCG_REG_R5,
158 TCG_REG_R4,
159 TCG_REG_R3,
160 };
161
162 static const int tcg_target_call_iarg_regs[] = {
163 TCG_REG_R3,
164 TCG_REG_R4,
165 TCG_REG_R5,
166 TCG_REG_R6,
167 TCG_REG_R7,
168 TCG_REG_R8,
169 TCG_REG_R9,
170 TCG_REG_R10
171 };
172
173 static const int tcg_target_call_oarg_regs[] = {
174 TCG_REG_R3,
175 TCG_REG_R4
176 };
177
178 static const int tcg_target_callee_save_regs[] = {
179 #ifdef TCG_TARGET_CALL_DARWIN
180 TCG_REG_R11,
181 #endif
182 TCG_REG_R14,
183 TCG_REG_R15,
184 TCG_REG_R16,
185 TCG_REG_R17,
186 TCG_REG_R18,
187 TCG_REG_R19,
188 TCG_REG_R20,
189 TCG_REG_R21,
190 TCG_REG_R22,
191 TCG_REG_R23,
192 TCG_REG_R24,
193 TCG_REG_R25,
194 TCG_REG_R26,
195 TCG_REG_R27, /* currently used for the global env */
196 TCG_REG_R28,
197 TCG_REG_R29,
198 TCG_REG_R30,
199 TCG_REG_R31
200 };
201
202 static inline bool in_range_b(tcg_target_long target)
203 {
204 return target == sextract64(target, 0, 26);
205 }
206
207 static uint32_t reloc_pc24_val(tcg_insn_unit *pc, tcg_insn_unit *target)
208 {
209 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
210 tcg_debug_assert(in_range_b(disp));
211 return disp & 0x3fffffc;
212 }
213
214 static void reloc_pc24(tcg_insn_unit *pc, tcg_insn_unit *target)
215 {
216 *pc = (*pc & ~0x3fffffc) | reloc_pc24_val(pc, target);
217 }
218
219 static uint16_t reloc_pc14_val(tcg_insn_unit *pc, tcg_insn_unit *target)
220 {
221 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
222 tcg_debug_assert(disp == (int16_t) disp);
223 return disp & 0xfffc;
224 }
225
226 static void reloc_pc14(tcg_insn_unit *pc, tcg_insn_unit *target)
227 {
228 *pc = (*pc & ~0xfffc) | reloc_pc14_val(pc, target);
229 }
230
231 static inline void tcg_out_b_noaddr(TCGContext *s, int insn)
232 {
233 unsigned retrans = *s->code_ptr & 0x3fffffc;
234 tcg_out32(s, insn | retrans);
235 }
236
237 static inline void tcg_out_bc_noaddr(TCGContext *s, int insn)
238 {
239 unsigned retrans = *s->code_ptr & 0xfffc;
240 tcg_out32(s, insn | retrans);
241 }
242
243 static void patch_reloc(tcg_insn_unit *code_ptr, int type,
244 intptr_t value, intptr_t addend)
245 {
246 tcg_insn_unit *target = (tcg_insn_unit *)value;
247
248 tcg_debug_assert(addend == 0);
249 switch (type) {
250 case R_PPC_REL14:
251 reloc_pc14(code_ptr, target);
252 break;
253 case R_PPC_REL24:
254 reloc_pc24(code_ptr, target);
255 break;
256 default:
257 tcg_abort();
258 }
259 }
260
261 /* parse target specific constraints */
262 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
263 {
264 const char *ct_str;
265
266 ct_str = *pct_str;
267 switch (ct_str[0]) {
268 case 'A': case 'B': case 'C': case 'D':
269 ct->ct |= TCG_CT_REG;
270 tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');
271 break;
272 case 'r':
273 ct->ct |= TCG_CT_REG;
274 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
275 break;
276 case 'L': /* qemu_ld constraint */
277 ct->ct |= TCG_CT_REG;
278 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
279 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
280 #ifdef CONFIG_SOFTMMU
281 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
282 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
283 #endif
284 break;
285 case 'S': /* qemu_st constraint */
286 ct->ct |= TCG_CT_REG;
287 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
288 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
289 #ifdef CONFIG_SOFTMMU
290 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
291 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
292 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
293 #endif
294 break;
295 case 'I':
296 ct->ct |= TCG_CT_CONST_S16;
297 break;
298 case 'J':
299 ct->ct |= TCG_CT_CONST_U16;
300 break;
301 case 'M':
302 ct->ct |= TCG_CT_CONST_MONE;
303 break;
304 case 'T':
305 ct->ct |= TCG_CT_CONST_S32;
306 break;
307 case 'U':
308 ct->ct |= TCG_CT_CONST_U32;
309 break;
310 case 'Z':
311 ct->ct |= TCG_CT_CONST_ZERO;
312 break;
313 default:
314 return -1;
315 }
316 ct_str++;
317 *pct_str = ct_str;
318 return 0;
319 }
320
321 /* test if a constant matches the constraint */
322 static int tcg_target_const_match(tcg_target_long val, TCGType type,
323 const TCGArgConstraint *arg_ct)
324 {
325 int ct = arg_ct->ct;
326 if (ct & TCG_CT_CONST) {
327 return 1;
328 }
329
330 /* The only 32-bit constraint we use aside from
331 TCG_CT_CONST is TCG_CT_CONST_S16. */
332 if (type == TCG_TYPE_I32) {
333 val = (int32_t)val;
334 }
335
336 if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) {
337 return 1;
338 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) {
339 return 1;
340 } else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
341 return 1;
342 } else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) {
343 return 1;
344 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
345 return 1;
346 } else if ((ct & TCG_CT_CONST_MONE) && val == -1) {
347 return 1;
348 }
349 return 0;
350 }
351
352 #define OPCD(opc) ((opc)<<26)
353 #define XO19(opc) (OPCD(19)|((opc)<<1))
354 #define MD30(opc) (OPCD(30)|((opc)<<2))
355 #define MDS30(opc) (OPCD(30)|((opc)<<1))
356 #define XO31(opc) (OPCD(31)|((opc)<<1))
357 #define XO58(opc) (OPCD(58)|(opc))
358 #define XO62(opc) (OPCD(62)|(opc))
359
360 #define B OPCD( 18)
361 #define BC OPCD( 16)
362 #define LBZ OPCD( 34)
363 #define LHZ OPCD( 40)
364 #define LHA OPCD( 42)
365 #define LWZ OPCD( 32)
366 #define STB OPCD( 38)
367 #define STH OPCD( 44)
368 #define STW OPCD( 36)
369
370 #define STD XO62( 0)
371 #define STDU XO62( 1)
372 #define STDX XO31(149)
373
374 #define LD XO58( 0)
375 #define LDX XO31( 21)
376 #define LDU XO58( 1)
377 #define LWA XO58( 2)
378 #define LWAX XO31(341)
379
380 #define ADDIC OPCD( 12)
381 #define ADDI OPCD( 14)
382 #define ADDIS OPCD( 15)
383 #define ORI OPCD( 24)
384 #define ORIS OPCD( 25)
385 #define XORI OPCD( 26)
386 #define XORIS OPCD( 27)
387 #define ANDI OPCD( 28)
388 #define ANDIS OPCD( 29)
389 #define MULLI OPCD( 7)
390 #define CMPLI OPCD( 10)
391 #define CMPI OPCD( 11)
392 #define SUBFIC OPCD( 8)
393
394 #define LWZU OPCD( 33)
395 #define STWU OPCD( 37)
396
397 #define RLWIMI OPCD( 20)
398 #define RLWINM OPCD( 21)
399 #define RLWNM OPCD( 23)
400
401 #define RLDICL MD30( 0)
402 #define RLDICR MD30( 1)
403 #define RLDIMI MD30( 3)
404 #define RLDCL MDS30( 8)
405
406 #define BCLR XO19( 16)
407 #define BCCTR XO19(528)
408 #define CRAND XO19(257)
409 #define CRANDC XO19(129)
410 #define CRNAND XO19(225)
411 #define CROR XO19(449)
412 #define CRNOR XO19( 33)
413
414 #define EXTSB XO31(954)
415 #define EXTSH XO31(922)
416 #define EXTSW XO31(986)
417 #define ADD XO31(266)
418 #define ADDE XO31(138)
419 #define ADDME XO31(234)
420 #define ADDZE XO31(202)
421 #define ADDC XO31( 10)
422 #define AND XO31( 28)
423 #define SUBF XO31( 40)
424 #define SUBFC XO31( 8)
425 #define SUBFE XO31(136)
426 #define SUBFME XO31(232)
427 #define SUBFZE XO31(200)
428 #define OR XO31(444)
429 #define XOR XO31(316)
430 #define MULLW XO31(235)
431 #define MULHW XO31( 75)
432 #define MULHWU XO31( 11)
433 #define DIVW XO31(491)
434 #define DIVWU XO31(459)
435 #define CMP XO31( 0)
436 #define CMPL XO31( 32)
437 #define LHBRX XO31(790)
438 #define LWBRX XO31(534)
439 #define LDBRX XO31(532)
440 #define STHBRX XO31(918)
441 #define STWBRX XO31(662)
442 #define STDBRX XO31(660)
443 #define MFSPR XO31(339)
444 #define MTSPR XO31(467)
445 #define SRAWI XO31(824)
446 #define NEG XO31(104)
447 #define MFCR XO31( 19)
448 #define MFOCRF (MFCR | (1u << 20))
449 #define NOR XO31(124)
450 #define CNTLZW XO31( 26)
451 #define CNTLZD XO31( 58)
452 #define ANDC XO31( 60)
453 #define ORC XO31(412)
454 #define EQV XO31(284)
455 #define NAND XO31(476)
456 #define ISEL XO31( 15)
457
458 #define MULLD XO31(233)
459 #define MULHD XO31( 73)
460 #define MULHDU XO31( 9)
461 #define DIVD XO31(489)
462 #define DIVDU XO31(457)
463
464 #define LBZX XO31( 87)
465 #define LHZX XO31(279)
466 #define LHAX XO31(343)
467 #define LWZX XO31( 23)
468 #define STBX XO31(215)
469 #define STHX XO31(407)
470 #define STWX XO31(151)
471
472 #define SPR(a, b) ((((a)<<5)|(b))<<11)
473 #define LR SPR(8, 0)
474 #define CTR SPR(9, 0)
475
476 #define SLW XO31( 24)
477 #define SRW XO31(536)
478 #define SRAW XO31(792)
479
480 #define SLD XO31( 27)
481 #define SRD XO31(539)
482 #define SRAD XO31(794)
483 #define SRADI XO31(413<<1)
484
485 #define TW XO31( 4)
486 #define TRAP (TW | TO(31))
487
488 #define NOP ORI /* ori 0,0,0 */
489
490 #define RT(r) ((r)<<21)
491 #define RS(r) ((r)<<21)
492 #define RA(r) ((r)<<16)
493 #define RB(r) ((r)<<11)
494 #define TO(t) ((t)<<21)
495 #define SH(s) ((s)<<11)
496 #define MB(b) ((b)<<6)
497 #define ME(e) ((e)<<1)
498 #define BO(o) ((o)<<21)
499 #define MB64(b) ((b)<<5)
500 #define FXM(b) (1 << (19 - (b)))
501
502 #define LK 1
503
504 #define TAB(t, a, b) (RT(t) | RA(a) | RB(b))
505 #define SAB(s, a, b) (RS(s) | RA(a) | RB(b))
506 #define TAI(s, a, i) (RT(s) | RA(a) | ((i) & 0xffff))
507 #define SAI(s, a, i) (RS(s) | RA(a) | ((i) & 0xffff))
508
509 #define BF(n) ((n)<<23)
510 #define BI(n, c) (((c)+((n)*4))<<16)
511 #define BT(n, c) (((c)+((n)*4))<<21)
512 #define BA(n, c) (((c)+((n)*4))<<16)
513 #define BB(n, c) (((c)+((n)*4))<<11)
514 #define BC_(n, c) (((c)+((n)*4))<<6)
515
516 #define BO_COND_TRUE BO(12)
517 #define BO_COND_FALSE BO( 4)
518 #define BO_ALWAYS BO(20)
519
520 enum {
521 CR_LT,
522 CR_GT,
523 CR_EQ,
524 CR_SO
525 };
526
527 static const uint32_t tcg_to_bc[] = {
528 [TCG_COND_EQ] = BC | BI(7, CR_EQ) | BO_COND_TRUE,
529 [TCG_COND_NE] = BC | BI(7, CR_EQ) | BO_COND_FALSE,
530 [TCG_COND_LT] = BC | BI(7, CR_LT) | BO_COND_TRUE,
531 [TCG_COND_GE] = BC | BI(7, CR_LT) | BO_COND_FALSE,
532 [TCG_COND_LE] = BC | BI(7, CR_GT) | BO_COND_FALSE,
533 [TCG_COND_GT] = BC | BI(7, CR_GT) | BO_COND_TRUE,
534 [TCG_COND_LTU] = BC | BI(7, CR_LT) | BO_COND_TRUE,
535 [TCG_COND_GEU] = BC | BI(7, CR_LT) | BO_COND_FALSE,
536 [TCG_COND_LEU] = BC | BI(7, CR_GT) | BO_COND_FALSE,
537 [TCG_COND_GTU] = BC | BI(7, CR_GT) | BO_COND_TRUE,
538 };
539
540 /* The low bit here is set if the RA and RB fields must be inverted. */
541 static const uint32_t tcg_to_isel[] = {
542 [TCG_COND_EQ] = ISEL | BC_(7, CR_EQ),
543 [TCG_COND_NE] = ISEL | BC_(7, CR_EQ) | 1,
544 [TCG_COND_LT] = ISEL | BC_(7, CR_LT),
545 [TCG_COND_GE] = ISEL | BC_(7, CR_LT) | 1,
546 [TCG_COND_LE] = ISEL | BC_(7, CR_GT) | 1,
547 [TCG_COND_GT] = ISEL | BC_(7, CR_GT),
548 [TCG_COND_LTU] = ISEL | BC_(7, CR_LT),
549 [TCG_COND_GEU] = ISEL | BC_(7, CR_LT) | 1,
550 [TCG_COND_LEU] = ISEL | BC_(7, CR_GT) | 1,
551 [TCG_COND_GTU] = ISEL | BC_(7, CR_GT),
552 };
553
554 static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
555 TCGReg base, tcg_target_long offset);
556
557 static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
558 {
559 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
560 if (ret != arg) {
561 tcg_out32(s, OR | SAB(arg, ret, arg));
562 }
563 }
564
565 static inline void tcg_out_rld(TCGContext *s, int op, TCGReg ra, TCGReg rs,
566 int sh, int mb)
567 {
568 tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
569 sh = SH(sh & 0x1f) | (((sh >> 5) & 1) << 1);
570 mb = MB64((mb >> 5) | ((mb << 1) & 0x3f));
571 tcg_out32(s, op | RA(ra) | RS(rs) | sh | mb);
572 }
573
574 static inline void tcg_out_rlw(TCGContext *s, int op, TCGReg ra, TCGReg rs,
575 int sh, int mb, int me)
576 {
577 tcg_out32(s, op | RA(ra) | RS(rs) | SH(sh) | MB(mb) | ME(me));
578 }
579
580 static inline void tcg_out_ext32u(TCGContext *s, TCGReg dst, TCGReg src)
581 {
582 tcg_out_rld(s, RLDICL, dst, src, 0, 32);
583 }
584
585 static inline void tcg_out_shli32(TCGContext *s, TCGReg dst, TCGReg src, int c)
586 {
587 tcg_out_rlw(s, RLWINM, dst, src, c, 0, 31 - c);
588 }
589
590 static inline void tcg_out_shli64(TCGContext *s, TCGReg dst, TCGReg src, int c)
591 {
592 tcg_out_rld(s, RLDICR, dst, src, c, 63 - c);
593 }
594
595 static inline void tcg_out_shri32(TCGContext *s, TCGReg dst, TCGReg src, int c)
596 {
597 tcg_out_rlw(s, RLWINM, dst, src, 32 - c, c, 31);
598 }
599
600 static inline void tcg_out_shri64(TCGContext *s, TCGReg dst, TCGReg src, int c)
601 {
602 tcg_out_rld(s, RLDICL, dst, src, 64 - c, c);
603 }
604
605 static void tcg_out_movi32(TCGContext *s, TCGReg ret, int32_t arg)
606 {
607 if (arg == (int16_t) arg) {
608 tcg_out32(s, ADDI | TAI(ret, 0, arg));
609 } else {
610 tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16));
611 if (arg & 0xffff) {
612 tcg_out32(s, ORI | SAI(ret, ret, arg));
613 }
614 }
615 }
616
617 static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret,
618 tcg_target_long arg)
619 {
620 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
621 if (type == TCG_TYPE_I32 || arg == (int32_t)arg) {
622 tcg_out_movi32(s, ret, arg);
623 } else if (arg == (uint32_t)arg && !(arg & 0x8000)) {
624 tcg_out32(s, ADDI | TAI(ret, 0, arg));
625 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
626 } else {
627 int32_t high;
628
629 if (USE_REG_RA) {
630 intptr_t diff = arg - (intptr_t)tb_ret_addr;
631 if (diff == (int32_t)diff) {
632 tcg_out_mem_long(s, ADDI, ADD, ret, TCG_REG_RA, diff);
633 return;
634 }
635 }
636
637 high = arg >> 31 >> 1;
638 tcg_out_movi32(s, ret, high);
639 if (high) {
640 tcg_out_shli64(s, ret, ret, 32);
641 }
642 if (arg & 0xffff0000) {
643 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
644 }
645 if (arg & 0xffff) {
646 tcg_out32(s, ORI | SAI(ret, ret, arg));
647 }
648 }
649 }
650
651 static bool mask_operand(uint32_t c, int *mb, int *me)
652 {
653 uint32_t lsb, test;
654
655 /* Accept a bit pattern like:
656 0....01....1
657 1....10....0
658 0..01..10..0
659 Keep track of the transitions. */
660 if (c == 0 || c == -1) {
661 return false;
662 }
663 test = c;
664 lsb = test & -test;
665 test += lsb;
666 if (test & (test - 1)) {
667 return false;
668 }
669
670 *me = clz32(lsb);
671 *mb = test ? clz32(test & -test) + 1 : 0;
672 return true;
673 }
674
675 static bool mask64_operand(uint64_t c, int *mb, int *me)
676 {
677 uint64_t lsb;
678
679 if (c == 0) {
680 return false;
681 }
682
683 lsb = c & -c;
684 /* Accept 1..10..0. */
685 if (c == -lsb) {
686 *mb = 0;
687 *me = clz64(lsb);
688 return true;
689 }
690 /* Accept 0..01..1. */
691 if (lsb == 1 && (c & (c + 1)) == 0) {
692 *mb = clz64(c + 1) + 1;
693 *me = 63;
694 return true;
695 }
696 return false;
697 }
698
699 static void tcg_out_andi32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
700 {
701 int mb, me;
702
703 if (mask_operand(c, &mb, &me)) {
704 tcg_out_rlw(s, RLWINM, dst, src, 0, mb, me);
705 } else if ((c & 0xffff) == c) {
706 tcg_out32(s, ANDI | SAI(src, dst, c));
707 return;
708 } else if ((c & 0xffff0000) == c) {
709 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
710 return;
711 } else {
712 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R0, c);
713 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0));
714 }
715 }
716
717 static void tcg_out_andi64(TCGContext *s, TCGReg dst, TCGReg src, uint64_t c)
718 {
719 int mb, me;
720
721 tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
722 if (mask64_operand(c, &mb, &me)) {
723 if (mb == 0) {
724 tcg_out_rld(s, RLDICR, dst, src, 0, me);
725 } else {
726 tcg_out_rld(s, RLDICL, dst, src, 0, mb);
727 }
728 } else if ((c & 0xffff) == c) {
729 tcg_out32(s, ANDI | SAI(src, dst, c));
730 return;
731 } else if ((c & 0xffff0000) == c) {
732 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
733 return;
734 } else {
735 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, c);
736 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0));
737 }
738 }
739
740 static void tcg_out_zori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c,
741 int op_lo, int op_hi)
742 {
743 if (c >> 16) {
744 tcg_out32(s, op_hi | SAI(src, dst, c >> 16));
745 src = dst;
746 }
747 if (c & 0xffff) {
748 tcg_out32(s, op_lo | SAI(src, dst, c));
749 src = dst;
750 }
751 }
752
753 static void tcg_out_ori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
754 {
755 tcg_out_zori32(s, dst, src, c, ORI, ORIS);
756 }
757
758 static void tcg_out_xori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
759 {
760 tcg_out_zori32(s, dst, src, c, XORI, XORIS);
761 }
762
763 static void tcg_out_b(TCGContext *s, int mask, tcg_insn_unit *target)
764 {
765 ptrdiff_t disp = tcg_pcrel_diff(s, target);
766 if (in_range_b(disp)) {
767 tcg_out32(s, B | (disp & 0x3fffffc) | mask);
768 } else {
769 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, (uintptr_t)target);
770 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | CTR);
771 tcg_out32(s, BCCTR | BO_ALWAYS | mask);
772 }
773 }
774
775 static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
776 TCGReg base, tcg_target_long offset)
777 {
778 tcg_target_long orig = offset, l0, l1, extra = 0, align = 0;
779 bool is_store = false;
780 TCGReg rs = TCG_REG_TMP1;
781
782 switch (opi) {
783 case LD: case LWA:
784 align = 3;
785 /* FALLTHRU */
786 default:
787 if (rt != TCG_REG_R0) {
788 rs = rt;
789 break;
790 }
791 break;
792 case STD:
793 align = 3;
794 /* FALLTHRU */
795 case STB: case STH: case STW:
796 is_store = true;
797 break;
798 }
799
800 /* For unaligned, or very large offsets, use the indexed form. */
801 if (offset & align || offset != (int32_t)offset) {
802 if (rs == base) {
803 rs = TCG_REG_R0;
804 }
805 tcg_debug_assert(!is_store || rs != rt);
806 tcg_out_movi(s, TCG_TYPE_PTR, rs, orig);
807 tcg_out32(s, opx | TAB(rt, base, rs));
808 return;
809 }
810
811 l0 = (int16_t)offset;
812 offset = (offset - l0) >> 16;
813 l1 = (int16_t)offset;
814
815 if (l1 < 0 && orig >= 0) {
816 extra = 0x4000;
817 l1 = (int16_t)(offset - 0x4000);
818 }
819 if (l1) {
820 tcg_out32(s, ADDIS | TAI(rs, base, l1));
821 base = rs;
822 }
823 if (extra) {
824 tcg_out32(s, ADDIS | TAI(rs, base, extra));
825 base = rs;
826 }
827 if (opi != ADDI || base != rt || l0 != 0) {
828 tcg_out32(s, opi | TAI(rt, base, l0));
829 }
830 }
831
832 static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
833 TCGReg arg1, intptr_t arg2)
834 {
835 int opi, opx;
836
837 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
838 if (type == TCG_TYPE_I32) {
839 opi = LWZ, opx = LWZX;
840 } else {
841 opi = LD, opx = LDX;
842 }
843 tcg_out_mem_long(s, opi, opx, ret, arg1, arg2);
844 }
845
846 static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
847 TCGReg arg1, intptr_t arg2)
848 {
849 int opi, opx;
850
851 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
852 if (type == TCG_TYPE_I32) {
853 opi = STW, opx = STWX;
854 } else {
855 opi = STD, opx = STDX;
856 }
857 tcg_out_mem_long(s, opi, opx, arg, arg1, arg2);
858 }
859
860 static void tcg_out_cmp(TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
861 int const_arg2, int cr, TCGType type)
862 {
863 int imm;
864 uint32_t op;
865
866 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
867
868 /* Simplify the comparisons below wrt CMPI. */
869 if (type == TCG_TYPE_I32) {
870 arg2 = (int32_t)arg2;
871 }
872
873 switch (cond) {
874 case TCG_COND_EQ:
875 case TCG_COND_NE:
876 if (const_arg2) {
877 if ((int16_t) arg2 == arg2) {
878 op = CMPI;
879 imm = 1;
880 break;
881 } else if ((uint16_t) arg2 == arg2) {
882 op = CMPLI;
883 imm = 1;
884 break;
885 }
886 }
887 op = CMPL;
888 imm = 0;
889 break;
890
891 case TCG_COND_LT:
892 case TCG_COND_GE:
893 case TCG_COND_LE:
894 case TCG_COND_GT:
895 if (const_arg2) {
896 if ((int16_t) arg2 == arg2) {
897 op = CMPI;
898 imm = 1;
899 break;
900 }
901 }
902 op = CMP;
903 imm = 0;
904 break;
905
906 case TCG_COND_LTU:
907 case TCG_COND_GEU:
908 case TCG_COND_LEU:
909 case TCG_COND_GTU:
910 if (const_arg2) {
911 if ((uint16_t) arg2 == arg2) {
912 op = CMPLI;
913 imm = 1;
914 break;
915 }
916 }
917 op = CMPL;
918 imm = 0;
919 break;
920
921 default:
922 tcg_abort();
923 }
924 op |= BF(cr) | ((type == TCG_TYPE_I64) << 21);
925
926 if (imm) {
927 tcg_out32(s, op | RA(arg1) | (arg2 & 0xffff));
928 } else {
929 if (const_arg2) {
930 tcg_out_movi(s, type, TCG_REG_R0, arg2);
931 arg2 = TCG_REG_R0;
932 }
933 tcg_out32(s, op | RA(arg1) | RB(arg2));
934 }
935 }
936
937 static void tcg_out_setcond_eq0(TCGContext *s, TCGType type,
938 TCGReg dst, TCGReg src)
939 {
940 if (type == TCG_TYPE_I32) {
941 tcg_out32(s, CNTLZW | RS(src) | RA(dst));
942 tcg_out_shri32(s, dst, dst, 5);
943 } else {
944 tcg_out32(s, CNTLZD | RS(src) | RA(dst));
945 tcg_out_shri64(s, dst, dst, 6);
946 }
947 }
948
949 static void tcg_out_setcond_ne0(TCGContext *s, TCGReg dst, TCGReg src)
950 {
951 /* X != 0 implies X + -1 generates a carry. Extra addition
952 trickery means: R = X-1 + ~X + C = X-1 + (-X+1) + C = C. */
953 if (dst != src) {
954 tcg_out32(s, ADDIC | TAI(dst, src, -1));
955 tcg_out32(s, SUBFE | TAB(dst, dst, src));
956 } else {
957 tcg_out32(s, ADDIC | TAI(TCG_REG_R0, src, -1));
958 tcg_out32(s, SUBFE | TAB(dst, TCG_REG_R0, src));
959 }
960 }
961
962 static TCGReg tcg_gen_setcond_xor(TCGContext *s, TCGReg arg1, TCGArg arg2,
963 bool const_arg2)
964 {
965 if (const_arg2) {
966 if ((uint32_t)arg2 == arg2) {
967 tcg_out_xori32(s, TCG_REG_R0, arg1, arg2);
968 } else {
969 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, arg2);
970 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, TCG_REG_R0));
971 }
972 } else {
973 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, arg2));
974 }
975 return TCG_REG_R0;
976 }
977
978 static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond,
979 TCGArg arg0, TCGArg arg1, TCGArg arg2,
980 int const_arg2)
981 {
982 int crop, sh;
983
984 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
985
986 /* Ignore high bits of a potential constant arg2. */
987 if (type == TCG_TYPE_I32) {
988 arg2 = (uint32_t)arg2;
989 }
990
991 /* Handle common and trivial cases before handling anything else. */
992 if (arg2 == 0) {
993 switch (cond) {
994 case TCG_COND_EQ:
995 tcg_out_setcond_eq0(s, type, arg0, arg1);
996 return;
997 case TCG_COND_NE:
998 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
999 tcg_out_ext32u(s, TCG_REG_R0, arg1);
1000 arg1 = TCG_REG_R0;
1001 }
1002 tcg_out_setcond_ne0(s, arg0, arg1);
1003 return;
1004 case TCG_COND_GE:
1005 tcg_out32(s, NOR | SAB(arg1, arg0, arg1));
1006 arg1 = arg0;
1007 /* FALLTHRU */
1008 case TCG_COND_LT:
1009 /* Extract the sign bit. */
1010 if (type == TCG_TYPE_I32) {
1011 tcg_out_shri32(s, arg0, arg1, 31);
1012 } else {
1013 tcg_out_shri64(s, arg0, arg1, 63);
1014 }
1015 return;
1016 default:
1017 break;
1018 }
1019 }
1020
1021 /* If we have ISEL, we can implement everything with 3 or 4 insns.
1022 All other cases below are also at least 3 insns, so speed up the
1023 code generator by not considering them and always using ISEL. */
1024 if (HAVE_ISEL) {
1025 int isel, tab;
1026
1027 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1028
1029 isel = tcg_to_isel[cond];
1030
1031 tcg_out_movi(s, type, arg0, 1);
1032 if (isel & 1) {
1033 /* arg0 = (bc ? 0 : 1) */
1034 tab = TAB(arg0, 0, arg0);
1035 isel &= ~1;
1036 } else {
1037 /* arg0 = (bc ? 1 : 0) */
1038 tcg_out_movi(s, type, TCG_REG_R0, 0);
1039 tab = TAB(arg0, arg0, TCG_REG_R0);
1040 }
1041 tcg_out32(s, isel | tab);
1042 return;
1043 }
1044
1045 switch (cond) {
1046 case TCG_COND_EQ:
1047 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
1048 tcg_out_setcond_eq0(s, type, arg0, arg1);
1049 return;
1050
1051 case TCG_COND_NE:
1052 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
1053 /* Discard the high bits only once, rather than both inputs. */
1054 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
1055 tcg_out_ext32u(s, TCG_REG_R0, arg1);
1056 arg1 = TCG_REG_R0;
1057 }
1058 tcg_out_setcond_ne0(s, arg0, arg1);
1059 return;
1060
1061 case TCG_COND_GT:
1062 case TCG_COND_GTU:
1063 sh = 30;
1064 crop = 0;
1065 goto crtest;
1066
1067 case TCG_COND_LT:
1068 case TCG_COND_LTU:
1069 sh = 29;
1070 crop = 0;
1071 goto crtest;
1072
1073 case TCG_COND_GE:
1074 case TCG_COND_GEU:
1075 sh = 31;
1076 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_LT) | BB(7, CR_LT);
1077 goto crtest;
1078
1079 case TCG_COND_LE:
1080 case TCG_COND_LEU:
1081 sh = 31;
1082 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_GT) | BB(7, CR_GT);
1083 crtest:
1084 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1085 if (crop) {
1086 tcg_out32(s, crop);
1087 }
1088 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7));
1089 tcg_out_rlw(s, RLWINM, arg0, TCG_REG_R0, sh, 31, 31);
1090 break;
1091
1092 default:
1093 tcg_abort();
1094 }
1095 }
1096
1097 static void tcg_out_bc(TCGContext *s, int bc, TCGLabel *l)
1098 {
1099 if (l->has_value) {
1100 tcg_out32(s, bc | reloc_pc14_val(s->code_ptr, l->u.value_ptr));
1101 } else {
1102 tcg_out_reloc(s, s->code_ptr, R_PPC_REL14, l, 0);
1103 tcg_out_bc_noaddr(s, bc);
1104 }
1105 }
1106
1107 static void tcg_out_brcond(TCGContext *s, TCGCond cond,
1108 TCGArg arg1, TCGArg arg2, int const_arg2,
1109 TCGLabel *l, TCGType type)
1110 {
1111 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1112 tcg_out_bc(s, tcg_to_bc[cond], l);
1113 }
1114
1115 static void tcg_out_movcond(TCGContext *s, TCGType type, TCGCond cond,
1116 TCGArg dest, TCGArg c1, TCGArg c2, TCGArg v1,
1117 TCGArg v2, bool const_c2)
1118 {
1119 /* If for some reason both inputs are zero, don't produce bad code. */
1120 if (v1 == 0 && v2 == 0) {
1121 tcg_out_movi(s, type, dest, 0);
1122 return;
1123 }
1124
1125 tcg_out_cmp(s, cond, c1, c2, const_c2, 7, type);
1126
1127 if (HAVE_ISEL) {
1128 int isel = tcg_to_isel[cond];
1129
1130 /* Swap the V operands if the operation indicates inversion. */
1131 if (isel & 1) {
1132 int t = v1;
1133 v1 = v2;
1134 v2 = t;
1135 isel &= ~1;
1136 }
1137 /* V1 == 0 is handled by isel; V2 == 0 must be handled by hand. */
1138 if (v2 == 0) {
1139 tcg_out_movi(s, type, TCG_REG_R0, 0);
1140 }
1141 tcg_out32(s, isel | TAB(dest, v1, v2));
1142 } else {
1143 if (dest == v2) {
1144 cond = tcg_invert_cond(cond);
1145 v2 = v1;
1146 } else if (dest != v1) {
1147 if (v1 == 0) {
1148 tcg_out_movi(s, type, dest, 0);
1149 } else {
1150 tcg_out_mov(s, type, dest, v1);
1151 }
1152 }
1153 /* Branch forward over one insn */
1154 tcg_out32(s, tcg_to_bc[cond] | 8);
1155 if (v2 == 0) {
1156 tcg_out_movi(s, type, dest, 0);
1157 } else {
1158 tcg_out_mov(s, type, dest, v2);
1159 }
1160 }
1161 }
1162
1163 static void tcg_out_cmp2(TCGContext *s, const TCGArg *args,
1164 const int *const_args)
1165 {
1166 static const struct { uint8_t bit1, bit2; } bits[] = {
1167 [TCG_COND_LT ] = { CR_LT, CR_LT },
1168 [TCG_COND_LE ] = { CR_LT, CR_GT },
1169 [TCG_COND_GT ] = { CR_GT, CR_GT },
1170 [TCG_COND_GE ] = { CR_GT, CR_LT },
1171 [TCG_COND_LTU] = { CR_LT, CR_LT },
1172 [TCG_COND_LEU] = { CR_LT, CR_GT },
1173 [TCG_COND_GTU] = { CR_GT, CR_GT },
1174 [TCG_COND_GEU] = { CR_GT, CR_LT },
1175 };
1176
1177 TCGCond cond = args[4], cond2;
1178 TCGArg al, ah, bl, bh;
1179 int blconst, bhconst;
1180 int op, bit1, bit2;
1181
1182 al = args[0];
1183 ah = args[1];
1184 bl = args[2];
1185 bh = args[3];
1186 blconst = const_args[2];
1187 bhconst = const_args[3];
1188
1189 switch (cond) {
1190 case TCG_COND_EQ:
1191 op = CRAND;
1192 goto do_equality;
1193 case TCG_COND_NE:
1194 op = CRNAND;
1195 do_equality:
1196 tcg_out_cmp(s, cond, al, bl, blconst, 6, TCG_TYPE_I32);
1197 tcg_out_cmp(s, cond, ah, bh, bhconst, 7, TCG_TYPE_I32);
1198 tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
1199 break;
1200
1201 case TCG_COND_LT:
1202 case TCG_COND_LE:
1203 case TCG_COND_GT:
1204 case TCG_COND_GE:
1205 case TCG_COND_LTU:
1206 case TCG_COND_LEU:
1207 case TCG_COND_GTU:
1208 case TCG_COND_GEU:
1209 bit1 = bits[cond].bit1;
1210 bit2 = bits[cond].bit2;
1211 op = (bit1 != bit2 ? CRANDC : CRAND);
1212 cond2 = tcg_unsigned_cond(cond);
1213
1214 tcg_out_cmp(s, cond, ah, bh, bhconst, 6, TCG_TYPE_I32);
1215 tcg_out_cmp(s, cond2, al, bl, blconst, 7, TCG_TYPE_I32);
1216 tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, bit2));
1217 tcg_out32(s, CROR | BT(7, CR_EQ) | BA(6, bit1) | BB(7, CR_EQ));
1218 break;
1219
1220 default:
1221 tcg_abort();
1222 }
1223 }
1224
1225 static void tcg_out_setcond2(TCGContext *s, const TCGArg *args,
1226 const int *const_args)
1227 {
1228 tcg_out_cmp2(s, args + 1, const_args + 1);
1229 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7));
1230 tcg_out_rlw(s, RLWINM, args[0], TCG_REG_R0, 31, 31, 31);
1231 }
1232
1233 static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args,
1234 const int *const_args)
1235 {
1236 tcg_out_cmp2(s, args, const_args);
1237 tcg_out_bc(s, BC | BI(7, CR_EQ) | BO_COND_TRUE, arg_label(args[5]));
1238 }
1239
1240 #ifdef __powerpc64__
1241 void ppc_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr)
1242 {
1243 tcg_insn_unit i1, i2;
1244 uint64_t pair;
1245 intptr_t diff = addr - jmp_addr;
1246
1247 if (in_range_b(diff)) {
1248 i1 = B | (diff & 0x3fffffc);
1249 i2 = NOP;
1250 } else if (USE_REG_RA) {
1251 intptr_t lo, hi;
1252 diff = addr - (uintptr_t)tb_ret_addr;
1253 lo = (int16_t)diff;
1254 hi = (int32_t)(diff - lo);
1255 tcg_debug_assert(diff == hi + lo);
1256 i1 = ADDIS | TAI(TCG_REG_TMP1, TCG_REG_RA, hi >> 16);
1257 i2 = ADDI | TAI(TCG_REG_TMP1, TCG_REG_TMP1, lo);
1258 } else {
1259 tcg_debug_assert(TCG_TARGET_REG_BITS == 32 || addr == (int32_t)addr);
1260 i1 = ADDIS | TAI(TCG_REG_TMP1, 0, addr >> 16);
1261 i2 = ORI | SAI(TCG_REG_TMP1, TCG_REG_TMP1, addr);
1262 }
1263 #ifdef HOST_WORDS_BIGENDIAN
1264 pair = (uint64_t)i1 << 32 | i2;
1265 #else
1266 pair = (uint64_t)i2 << 32 | i1;
1267 #endif
1268
1269 atomic_set((uint64_t *)jmp_addr, pair);
1270 flush_icache_range(jmp_addr, jmp_addr + 8);
1271 }
1272 #else
1273 void ppc_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr)
1274 {
1275 intptr_t diff = addr - jmp_addr;
1276 tcg_debug_assert(in_range_b(diff));
1277 atomic_set((uint32_t *)jmp_addr, B | (diff & 0x3fffffc));
1278 flush_icache_range(jmp_addr, jmp_addr + 4);
1279 }
1280 #endif
1281
1282 static void tcg_out_call(TCGContext *s, tcg_insn_unit *target)
1283 {
1284 #ifdef _CALL_AIX
1285 /* Look through the descriptor. If the branch is in range, and we
1286 don't have to spend too much effort on building the toc. */
1287 void *tgt = ((void **)target)[0];
1288 uintptr_t toc = ((uintptr_t *)target)[1];
1289 intptr_t diff = tcg_pcrel_diff(s, tgt);
1290
1291 if (in_range_b(diff) && toc == (uint32_t)toc) {
1292 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, toc);
1293 tcg_out_b(s, LK, tgt);
1294 } else {
1295 /* Fold the low bits of the constant into the addresses below. */
1296 intptr_t arg = (intptr_t)target;
1297 int ofs = (int16_t)arg;
1298
1299 if (ofs + 8 < 0x8000) {
1300 arg -= ofs;
1301 } else {
1302 ofs = 0;
1303 }
1304 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, arg);
1305 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_TMP1, ofs);
1306 tcg_out32(s, MTSPR | RA(TCG_REG_R0) | CTR);
1307 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_REG_TMP1, ofs + SZP);
1308 tcg_out32(s, BCCTR | BO_ALWAYS | LK);
1309 }
1310 #elif defined(_CALL_ELF) && _CALL_ELF == 2
1311 intptr_t diff;
1312
1313 /* In the ELFv2 ABI, we have to set up r12 to contain the destination
1314 address, which the callee uses to compute its TOC address. */
1315 /* FIXME: when the branch is in range, we could avoid r12 load if we
1316 knew that the destination uses the same TOC, and what its local
1317 entry point offset is. */
1318 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R12, (intptr_t)target);
1319
1320 diff = tcg_pcrel_diff(s, target);
1321 if (in_range_b(diff)) {
1322 tcg_out_b(s, LK, target);
1323 } else {
1324 tcg_out32(s, MTSPR | RS(TCG_REG_R12) | CTR);
1325 tcg_out32(s, BCCTR | BO_ALWAYS | LK);
1326 }
1327 #else
1328 tcg_out_b(s, LK, target);
1329 #endif
1330 }
1331
1332 static const uint32_t qemu_ldx_opc[16] = {
1333 [MO_UB] = LBZX,
1334 [MO_UW] = LHZX,
1335 [MO_UL] = LWZX,
1336 [MO_Q] = LDX,
1337 [MO_SW] = LHAX,
1338 [MO_SL] = LWAX,
1339 [MO_BSWAP | MO_UB] = LBZX,
1340 [MO_BSWAP | MO_UW] = LHBRX,
1341 [MO_BSWAP | MO_UL] = LWBRX,
1342 [MO_BSWAP | MO_Q] = LDBRX,
1343 };
1344
1345 static const uint32_t qemu_stx_opc[16] = {
1346 [MO_UB] = STBX,
1347 [MO_UW] = STHX,
1348 [MO_UL] = STWX,
1349 [MO_Q] = STDX,
1350 [MO_BSWAP | MO_UB] = STBX,
1351 [MO_BSWAP | MO_UW] = STHBRX,
1352 [MO_BSWAP | MO_UL] = STWBRX,
1353 [MO_BSWAP | MO_Q] = STDBRX,
1354 };
1355
1356 static const uint32_t qemu_exts_opc[4] = {
1357 EXTSB, EXTSH, EXTSW, 0
1358 };
1359
1360 #if defined (CONFIG_SOFTMMU)
1361 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
1362 * int mmu_idx, uintptr_t ra)
1363 */
1364 static void * const qemu_ld_helpers[16] = {
1365 [MO_UB] = helper_ret_ldub_mmu,
1366 [MO_LEUW] = helper_le_lduw_mmu,
1367 [MO_LEUL] = helper_le_ldul_mmu,
1368 [MO_LEQ] = helper_le_ldq_mmu,
1369 [MO_BEUW] = helper_be_lduw_mmu,
1370 [MO_BEUL] = helper_be_ldul_mmu,
1371 [MO_BEQ] = helper_be_ldq_mmu,
1372 };
1373
1374 /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
1375 * uintxx_t val, int mmu_idx, uintptr_t ra)
1376 */
1377 static void * const qemu_st_helpers[16] = {
1378 [MO_UB] = helper_ret_stb_mmu,
1379 [MO_LEUW] = helper_le_stw_mmu,
1380 [MO_LEUL] = helper_le_stl_mmu,
1381 [MO_LEQ] = helper_le_stq_mmu,
1382 [MO_BEUW] = helper_be_stw_mmu,
1383 [MO_BEUL] = helper_be_stl_mmu,
1384 [MO_BEQ] = helper_be_stq_mmu,
1385 };
1386
1387 /* Perform the TLB load and compare. Places the result of the comparison
1388 in CR7, loads the addend of the TLB into R3, and returns the register
1389 containing the guest address (zero-extended into R4). Clobbers R0 and R2. */
1390
1391 static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp opc,
1392 TCGReg addrlo, TCGReg addrhi,
1393 int mem_index, bool is_read)
1394 {
1395 int cmp_off
1396 = (is_read
1397 ? offsetof(CPUArchState, tlb_table[mem_index][0].addr_read)
1398 : offsetof(CPUArchState, tlb_table[mem_index][0].addr_write));
1399 int add_off = offsetof(CPUArchState, tlb_table[mem_index][0].addend);
1400 TCGReg base = TCG_AREG0;
1401 TCGMemOp s_bits = opc & MO_SIZE;
1402
1403 /* Extract the page index, shifted into place for tlb index. */
1404 if (TCG_TARGET_REG_BITS == 64) {
1405 if (TARGET_LONG_BITS == 32) {
1406 /* Zero-extend the address into a place helpful for further use. */
1407 tcg_out_ext32u(s, TCG_REG_R4, addrlo);
1408 addrlo = TCG_REG_R4;
1409 } else {
1410 tcg_out_rld(s, RLDICL, TCG_REG_R3, addrlo,
1411 64 - TARGET_PAGE_BITS, 64 - CPU_TLB_BITS);
1412 }
1413 }
1414
1415 /* Compensate for very large offsets. */
1416 if (add_off >= 0x8000) {
1417 /* Most target env are smaller than 32k; none are larger than 64k.
1418 Simplify the logic here merely to offset by 0x7ff0, giving us a
1419 range just shy of 64k. Check this assumption. */
1420 QEMU_BUILD_BUG_ON(offsetof(CPUArchState,
1421 tlb_table[NB_MMU_MODES - 1][1])
1422 > 0x7ff0 + 0x7fff);
1423 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, base, 0x7ff0));
1424 base = TCG_REG_TMP1;
1425 cmp_off -= 0x7ff0;
1426 add_off -= 0x7ff0;
1427 }
1428
1429 /* Extraction and shifting, part 2. */
1430 if (TCG_TARGET_REG_BITS == 32 || TARGET_LONG_BITS == 32) {
1431 tcg_out_rlw(s, RLWINM, TCG_REG_R3, addrlo,
1432 32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
1433 32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS),
1434 31 - CPU_TLB_ENTRY_BITS);
1435 } else {
1436 tcg_out_shli64(s, TCG_REG_R3, TCG_REG_R3, CPU_TLB_ENTRY_BITS);
1437 }
1438
1439 tcg_out32(s, ADD | TAB(TCG_REG_R3, TCG_REG_R3, base));
1440
1441 /* Load the tlb comparator. */
1442 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1443 tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R4, TCG_REG_R3, cmp_off);
1444 tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP1, TCG_REG_R3, cmp_off + 4);
1445 } else {
1446 tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP1, TCG_REG_R3, cmp_off);
1447 }
1448
1449 /* Load the TLB addend for use on the fast path. Do this asap
1450 to minimize any load use delay. */
1451 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_REG_R3, add_off);
1452
1453 /* Clear the non-page, non-alignment bits from the address */
1454 if (TCG_TARGET_REG_BITS == 32 || TARGET_LONG_BITS == 32) {
1455 /* We don't support unaligned accesses on 32-bits, preserve
1456 * the bottom bits and thus trigger a comparison failure on
1457 * unaligned accesses
1458 */
1459 tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0,
1460 (32 - s_bits) & 31, 31 - TARGET_PAGE_BITS);
1461 } else if (s_bits) {
1462 /* > byte access, we need to handle alignment */
1463 if ((opc & MO_AMASK) == MO_ALIGN) {
1464 /* Alignment required by the front-end, same as 32-bits */
1465 tcg_out_rld(s, RLDICL, TCG_REG_R0, addrlo,
1466 64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - s_bits);
1467 tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BITS, 0);
1468 } else {
1469 /* We support unaligned accesses, we need to make sure we fail
1470 * if we cross a page boundary. The trick is to add the
1471 * access_size-1 to the address before masking the low bits.
1472 * That will make the address overflow to the next page if we
1473 * cross a page boundary which will then force a mismatch of
1474 * the TLB compare since the next page cannot possibly be in
1475 * the same TLB index.
1476 */
1477 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, (1 << s_bits) - 1));
1478 tcg_out_rld(s, RLDICR, TCG_REG_R0, TCG_REG_R0,
1479 0, 63 - TARGET_PAGE_BITS);
1480 }
1481 } else {
1482 /* Byte access, just chop off the bits below the page index */
1483 tcg_out_rld(s, RLDICR, TCG_REG_R0, addrlo, 0, 63 - TARGET_PAGE_BITS);
1484 }
1485
1486 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1487 tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1,
1488 0, 7, TCG_TYPE_I32);
1489 tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_R4, 0, 6, TCG_TYPE_I32);
1490 tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
1491 } else {
1492 tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1,
1493 0, 7, TCG_TYPE_TL);
1494 }
1495
1496 return addrlo;
1497 }
1498
1499 /* Record the context of a call to the out of line helper code for the slow
1500 path for a load or store, so that we can later generate the correct
1501 helper code. */
1502 static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
1503 TCGReg datalo_reg, TCGReg datahi_reg,
1504 TCGReg addrlo_reg, TCGReg addrhi_reg,
1505 tcg_insn_unit *raddr, tcg_insn_unit *lptr)
1506 {
1507 TCGLabelQemuLdst *label = new_ldst_label(s);
1508
1509 label->is_ld = is_ld;
1510 label->oi = oi;
1511 label->datalo_reg = datalo_reg;
1512 label->datahi_reg = datahi_reg;
1513 label->addrlo_reg = addrlo_reg;
1514 label->addrhi_reg = addrhi_reg;
1515 label->raddr = raddr;
1516 label->label_ptr[0] = lptr;
1517 }
1518
1519 static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
1520 {
1521 TCGMemOpIdx oi = lb->oi;
1522 TCGMemOp opc = get_memop(oi);
1523 TCGReg hi, lo, arg = TCG_REG_R3;
1524
1525 reloc_pc14(lb->label_ptr[0], s->code_ptr);
1526
1527 tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0);
1528
1529 lo = lb->addrlo_reg;
1530 hi = lb->addrhi_reg;
1531 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1532 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
1533 arg |= 1;
1534 #endif
1535 tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
1536 tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
1537 } else {
1538 /* If the address needed to be zero-extended, we'll have already
1539 placed it in R4. The only remaining case is 64-bit guest. */
1540 tcg_out_mov(s, TCG_TYPE_TL, arg++, lo);
1541 }
1542
1543 tcg_out_movi(s, TCG_TYPE_I32, arg++, oi);
1544 tcg_out32(s, MFSPR | RT(arg) | LR);
1545
1546 tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]);
1547
1548 lo = lb->datalo_reg;
1549 hi = lb->datahi_reg;
1550 if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) {
1551 tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_REG_R4);
1552 tcg_out_mov(s, TCG_TYPE_I32, hi, TCG_REG_R3);
1553 } else if (opc & MO_SIGN) {
1554 uint32_t insn = qemu_exts_opc[opc & MO_SIZE];
1555 tcg_out32(s, insn | RA(lo) | RS(TCG_REG_R3));
1556 } else {
1557 tcg_out_mov(s, TCG_TYPE_REG, lo, TCG_REG_R3);
1558 }
1559
1560 tcg_out_b(s, 0, lb->raddr);
1561 }
1562
1563 static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
1564 {
1565 TCGMemOpIdx oi = lb->oi;
1566 TCGMemOp opc = get_memop(oi);
1567 TCGMemOp s_bits = opc & MO_SIZE;
1568 TCGReg hi, lo, arg = TCG_REG_R3;
1569
1570 reloc_pc14(lb->label_ptr[0], s->code_ptr);
1571
1572 tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0);
1573
1574 lo = lb->addrlo_reg;
1575 hi = lb->addrhi_reg;
1576 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1577 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
1578 arg |= 1;
1579 #endif
1580 tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
1581 tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
1582 } else {
1583 /* If the address needed to be zero-extended, we'll have already
1584 placed it in R4. The only remaining case is 64-bit guest. */
1585 tcg_out_mov(s, TCG_TYPE_TL, arg++, lo);
1586 }
1587
1588 lo = lb->datalo_reg;
1589 hi = lb->datahi_reg;
1590 if (TCG_TARGET_REG_BITS == 32) {
1591 switch (s_bits) {
1592 case MO_64:
1593 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
1594 arg |= 1;
1595 #endif
1596 tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
1597 /* FALLTHRU */
1598 case MO_32:
1599 tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
1600 break;
1601 default:
1602 tcg_out_rlw(s, RLWINM, arg++, lo, 0, 32 - (8 << s_bits), 31);
1603 break;
1604 }
1605 } else {
1606 if (s_bits == MO_64) {
1607 tcg_out_mov(s, TCG_TYPE_I64, arg++, lo);
1608 } else {
1609 tcg_out_rld(s, RLDICL, arg++, lo, 0, 64 - (8 << s_bits));
1610 }
1611 }
1612
1613 tcg_out_movi(s, TCG_TYPE_I32, arg++, oi);
1614 tcg_out32(s, MFSPR | RT(arg) | LR);
1615
1616 tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
1617
1618 tcg_out_b(s, 0, lb->raddr);
1619 }
1620 #endif /* SOFTMMU */
1621
1622 static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
1623 {
1624 TCGReg datalo, datahi, addrlo, rbase;
1625 TCGReg addrhi __attribute__((unused));
1626 TCGMemOpIdx oi;
1627 TCGMemOp opc, s_bits;
1628 #ifdef CONFIG_SOFTMMU
1629 int mem_index;
1630 tcg_insn_unit *label_ptr;
1631 #endif
1632
1633 datalo = *args++;
1634 datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
1635 addrlo = *args++;
1636 addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
1637 oi = *args++;
1638 opc = get_memop(oi);
1639 s_bits = opc & MO_SIZE;
1640
1641 #ifdef CONFIG_SOFTMMU
1642 mem_index = get_mmuidx(oi);
1643 addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, true);
1644
1645 /* Load a pointer into the current opcode w/conditional branch-link. */
1646 label_ptr = s->code_ptr;
1647 tcg_out_bc_noaddr(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
1648
1649 rbase = TCG_REG_R3;
1650 #else /* !CONFIG_SOFTMMU */
1651 rbase = guest_base ? TCG_GUEST_BASE_REG : 0;
1652 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1653 tcg_out_ext32u(s, TCG_REG_TMP1, addrlo);
1654 addrlo = TCG_REG_TMP1;
1655 }
1656 #endif
1657
1658 if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {
1659 if (opc & MO_BSWAP) {
1660 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
1661 tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo));
1662 tcg_out32(s, LWBRX | TAB(datahi, rbase, TCG_REG_R0));
1663 } else if (rbase != 0) {
1664 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
1665 tcg_out32(s, LWZX | TAB(datahi, rbase, addrlo));
1666 tcg_out32(s, LWZX | TAB(datalo, rbase, TCG_REG_R0));
1667 } else if (addrlo == datahi) {
1668 tcg_out32(s, LWZ | TAI(datalo, addrlo, 4));
1669 tcg_out32(s, LWZ | TAI(datahi, addrlo, 0));
1670 } else {
1671 tcg_out32(s, LWZ | TAI(datahi, addrlo, 0));
1672 tcg_out32(s, LWZ | TAI(datalo, addrlo, 4));
1673 }
1674 } else {
1675 uint32_t insn = qemu_ldx_opc[opc & (MO_BSWAP | MO_SSIZE)];
1676 if (!HAVE_ISA_2_06 && insn == LDBRX) {
1677 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
1678 tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo));
1679 tcg_out32(s, LWBRX | TAB(TCG_REG_R0, rbase, TCG_REG_R0));
1680 tcg_out_rld(s, RLDIMI, datalo, TCG_REG_R0, 32, 0);
1681 } else if (insn) {
1682 tcg_out32(s, insn | TAB(datalo, rbase, addrlo));
1683 } else {
1684 insn = qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)];
1685 tcg_out32(s, insn | TAB(datalo, rbase, addrlo));
1686 insn = qemu_exts_opc[s_bits];
1687 tcg_out32(s, insn | RA(datalo) | RS(datalo));
1688 }
1689 }
1690
1691 #ifdef CONFIG_SOFTMMU
1692 add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi,
1693 s->code_ptr, label_ptr);
1694 #endif
1695 }
1696
1697 static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
1698 {
1699 TCGReg datalo, datahi, addrlo, rbase;
1700 TCGReg addrhi __attribute__((unused));
1701 TCGMemOpIdx oi;
1702 TCGMemOp opc, s_bits;
1703 #ifdef CONFIG_SOFTMMU
1704 int mem_index;
1705 tcg_insn_unit *label_ptr;
1706 #endif
1707
1708 datalo = *args++;
1709 datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
1710 addrlo = *args++;
1711 addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
1712 oi = *args++;
1713 opc = get_memop(oi);
1714 s_bits = opc & MO_SIZE;
1715
1716 #ifdef CONFIG_SOFTMMU
1717 mem_index = get_mmuidx(oi);
1718 addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, false);
1719
1720 /* Load a pointer into the current opcode w/conditional branch-link. */
1721 label_ptr = s->code_ptr;
1722 tcg_out_bc_noaddr(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
1723
1724 rbase = TCG_REG_R3;
1725 #else /* !CONFIG_SOFTMMU */
1726 rbase = guest_base ? TCG_GUEST_BASE_REG : 0;
1727 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1728 tcg_out_ext32u(s, TCG_REG_TMP1, addrlo);
1729 addrlo = TCG_REG_TMP1;
1730 }
1731 #endif
1732
1733 if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {
1734 if (opc & MO_BSWAP) {
1735 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
1736 tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo));
1737 tcg_out32(s, STWBRX | SAB(datahi, rbase, TCG_REG_R0));
1738 } else if (rbase != 0) {
1739 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
1740 tcg_out32(s, STWX | SAB(datahi, rbase, addrlo));
1741 tcg_out32(s, STWX | SAB(datalo, rbase, TCG_REG_R0));
1742 } else {
1743 tcg_out32(s, STW | TAI(datahi, addrlo, 0));
1744 tcg_out32(s, STW | TAI(datalo, addrlo, 4));
1745 }
1746 } else {
1747 uint32_t insn = qemu_stx_opc[opc & (MO_BSWAP | MO_SIZE)];
1748 if (!HAVE_ISA_2_06 && insn == STDBRX) {
1749 tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo));
1750 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, addrlo, 4));
1751 tcg_out_shri64(s, TCG_REG_R0, datalo, 32);
1752 tcg_out32(s, STWBRX | SAB(TCG_REG_R0, rbase, TCG_REG_TMP1));
1753 } else {
1754 tcg_out32(s, insn | SAB(datalo, rbase, addrlo));
1755 }
1756 }
1757
1758 #ifdef CONFIG_SOFTMMU
1759 add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi,
1760 s->code_ptr, label_ptr);
1761 #endif
1762 }
1763
1764 /* Parameters for function call generation, used in tcg.c. */
1765 #define TCG_TARGET_STACK_ALIGN 16
1766 #define TCG_TARGET_EXTEND_ARGS 1
1767
1768 #ifdef _CALL_AIX
1769 # define LINK_AREA_SIZE (6 * SZR)
1770 # define LR_OFFSET (1 * SZR)
1771 # define TCG_TARGET_CALL_STACK_OFFSET (LINK_AREA_SIZE + 8 * SZR)
1772 #elif defined(TCG_TARGET_CALL_DARWIN)
1773 # define LINK_AREA_SIZE (6 * SZR)
1774 # define LR_OFFSET (2 * SZR)
1775 #elif TCG_TARGET_REG_BITS == 64
1776 # if defined(_CALL_ELF) && _CALL_ELF == 2
1777 # define LINK_AREA_SIZE (4 * SZR)
1778 # define LR_OFFSET (1 * SZR)
1779 # endif
1780 #else /* TCG_TARGET_REG_BITS == 32 */
1781 # if defined(_CALL_SYSV)
1782 # define LINK_AREA_SIZE (2 * SZR)
1783 # define LR_OFFSET (1 * SZR)
1784 # endif
1785 #endif
1786 #ifndef LR_OFFSET
1787 # error "Unhandled abi"
1788 #endif
1789 #ifndef TCG_TARGET_CALL_STACK_OFFSET
1790 # define TCG_TARGET_CALL_STACK_OFFSET LINK_AREA_SIZE
1791 #endif
1792
1793 #define CPU_TEMP_BUF_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
1794 #define REG_SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * SZR)
1795
1796 #define FRAME_SIZE ((TCG_TARGET_CALL_STACK_OFFSET \
1797 + TCG_STATIC_CALL_ARGS_SIZE \
1798 + CPU_TEMP_BUF_SIZE \
1799 + REG_SAVE_SIZE \
1800 + TCG_TARGET_STACK_ALIGN - 1) \
1801 & -TCG_TARGET_STACK_ALIGN)
1802
1803 #define REG_SAVE_BOT (FRAME_SIZE - REG_SAVE_SIZE)
1804
1805 static void tcg_target_qemu_prologue(TCGContext *s)
1806 {
1807 int i;
1808
1809 #ifdef _CALL_AIX
1810 void **desc = (void **)s->code_ptr;
1811 desc[0] = desc + 2; /* entry point */
1812 desc[1] = 0; /* environment pointer */
1813 s->code_ptr = (void *)(desc + 2); /* skip over descriptor */
1814 #endif
1815
1816 tcg_set_frame(s, TCG_REG_CALL_STACK, REG_SAVE_BOT - CPU_TEMP_BUF_SIZE,
1817 CPU_TEMP_BUF_SIZE);
1818
1819 /* Prologue */
1820 tcg_out32(s, MFSPR | RT(TCG_REG_R0) | LR);
1821 tcg_out32(s, (SZR == 8 ? STDU : STWU)
1822 | SAI(TCG_REG_R1, TCG_REG_R1, -FRAME_SIZE));
1823
1824 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
1825 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
1826 TCG_REG_R1, REG_SAVE_BOT + i * SZR);
1827 }
1828 tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET);
1829
1830 #ifndef CONFIG_SOFTMMU
1831 if (guest_base) {
1832 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
1833 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
1834 }
1835 #endif
1836
1837 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
1838 tcg_out32(s, MTSPR | RS(tcg_target_call_iarg_regs[1]) | CTR);
1839
1840 if (USE_REG_RA) {
1841 #ifdef _CALL_AIX
1842 /* Make the caller load the value as the TOC into R2. */
1843 tb_ret_addr = s->code_ptr + 2;
1844 desc[1] = tb_ret_addr;
1845 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_RA, TCG_REG_R2);
1846 tcg_out32(s, BCCTR | BO_ALWAYS);
1847 #elif defined(_CALL_ELF) && _CALL_ELF == 2
1848 /* Compute from the incoming R12 value. */
1849 tb_ret_addr = s->code_ptr + 2;
1850 tcg_out32(s, ADDI | TAI(TCG_REG_RA, TCG_REG_R12,
1851 tcg_ptr_byte_diff(tb_ret_addr, s->code_buf)));
1852 tcg_out32(s, BCCTR | BO_ALWAYS);
1853 #else
1854 /* Reserve max 5 insns for the constant load. */
1855 tb_ret_addr = s->code_ptr + 6;
1856 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (intptr_t)tb_ret_addr);
1857 tcg_out32(s, BCCTR | BO_ALWAYS);
1858 while (s->code_ptr < tb_ret_addr) {
1859 tcg_out32(s, NOP);
1860 }
1861 #endif
1862 } else {
1863 tcg_out32(s, BCCTR | BO_ALWAYS);
1864 tb_ret_addr = s->code_ptr;
1865 }
1866
1867 /* Epilogue */
1868 tcg_debug_assert(tb_ret_addr == s->code_ptr);
1869
1870 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET);
1871 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
1872 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
1873 TCG_REG_R1, REG_SAVE_BOT + i * SZR);
1874 }
1875 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | LR);
1876 tcg_out32(s, ADDI | TAI(TCG_REG_R1, TCG_REG_R1, FRAME_SIZE));
1877 tcg_out32(s, BCLR | BO_ALWAYS);
1878 }
1879
1880 static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
1881 const int *const_args)
1882 {
1883 TCGArg a0, a1, a2;
1884 int c;
1885
1886 switch (opc) {
1887 case INDEX_op_exit_tb:
1888 if (USE_REG_RA) {
1889 ptrdiff_t disp = tcg_pcrel_diff(s, tb_ret_addr);
1890
1891 /* Use a direct branch if we can, otherwise use the value in RA.
1892 Note that the direct branch is always backward, thus we need
1893 to account for the possibility of 5 insns from the movi. */
1894 if (!in_range_b(disp - 20)) {
1895 tcg_out32(s, MTSPR | RS(TCG_REG_RA) | CTR);
1896 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, args[0]);
1897 tcg_out32(s, BCCTR | BO_ALWAYS);
1898 break;
1899 }
1900 }
1901 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, args[0]);
1902 tcg_out_b(s, 0, tb_ret_addr);
1903 break;
1904 case INDEX_op_goto_tb:
1905 tcg_debug_assert(s->tb_jmp_insn_offset);
1906 /* Direct jump. */
1907 #ifdef __powerpc64__
1908 /* Ensure the next insns are 8-byte aligned. */
1909 if ((uintptr_t)s->code_ptr & 7) {
1910 tcg_out32(s, NOP);
1911 }
1912 s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s);
1913 /* To be replaced by either a branch+nop or a load into TMP1. */
1914 s->code_ptr += 2;
1915 tcg_out32(s, MTSPR | RS(TCG_REG_TMP1) | CTR);
1916 tcg_out32(s, BCCTR | BO_ALWAYS);
1917 #else
1918 /* To be replaced by a branch. */
1919 s->code_ptr++;
1920 #endif
1921 s->tb_jmp_reset_offset[args[0]] = tcg_current_code_size(s);
1922 break;
1923 case INDEX_op_br:
1924 {
1925 TCGLabel *l = arg_label(args[0]);
1926
1927 if (l->has_value) {
1928 tcg_out_b(s, 0, l->u.value_ptr);
1929 } else {
1930 tcg_out_reloc(s, s->code_ptr, R_PPC_REL24, l, 0);
1931 tcg_out_b_noaddr(s, B);
1932 }
1933 }
1934 break;
1935 case INDEX_op_ld8u_i32:
1936 case INDEX_op_ld8u_i64:
1937 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
1938 break;
1939 case INDEX_op_ld8s_i32:
1940 case INDEX_op_ld8s_i64:
1941 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
1942 tcg_out32(s, EXTSB | RS(args[0]) | RA(args[0]));
1943 break;
1944 case INDEX_op_ld16u_i32:
1945 case INDEX_op_ld16u_i64:
1946 tcg_out_mem_long(s, LHZ, LHZX, args[0], args[1], args[2]);
1947 break;
1948 case INDEX_op_ld16s_i32:
1949 case INDEX_op_ld16s_i64:
1950 tcg_out_mem_long(s, LHA, LHAX, args[0], args[1], args[2]);
1951 break;
1952 case INDEX_op_ld_i32:
1953 case INDEX_op_ld32u_i64:
1954 tcg_out_mem_long(s, LWZ, LWZX, args[0], args[1], args[2]);
1955 break;
1956 case INDEX_op_ld32s_i64:
1957 tcg_out_mem_long(s, LWA, LWAX, args[0], args[1], args[2]);
1958 break;
1959 case INDEX_op_ld_i64:
1960 tcg_out_mem_long(s, LD, LDX, args[0], args[1], args[2]);
1961 break;
1962 case INDEX_op_st8_i32:
1963 case INDEX_op_st8_i64:
1964 tcg_out_mem_long(s, STB, STBX, args[0], args[1], args[2]);
1965 break;
1966 case INDEX_op_st16_i32:
1967 case INDEX_op_st16_i64:
1968 tcg_out_mem_long(s, STH, STHX, args[0], args[1], args[2]);
1969 break;
1970 case INDEX_op_st_i32:
1971 case INDEX_op_st32_i64:
1972 tcg_out_mem_long(s, STW, STWX, args[0], args[1], args[2]);
1973 break;
1974 case INDEX_op_st_i64:
1975 tcg_out_mem_long(s, STD, STDX, args[0], args[1], args[2]);
1976 break;
1977
1978 case INDEX_op_add_i32:
1979 a0 = args[0], a1 = args[1], a2 = args[2];
1980 if (const_args[2]) {
1981 do_addi_32:
1982 tcg_out_mem_long(s, ADDI, ADD, a0, a1, (int32_t)a2);
1983 } else {
1984 tcg_out32(s, ADD | TAB(a0, a1, a2));
1985 }
1986 break;
1987 case INDEX_op_sub_i32:
1988 a0 = args[0], a1 = args[1], a2 = args[2];
1989 if (const_args[1]) {
1990 if (const_args[2]) {
1991 tcg_out_movi(s, TCG_TYPE_I32, a0, a1 - a2);
1992 } else {
1993 tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
1994 }
1995 } else if (const_args[2]) {
1996 a2 = -a2;
1997 goto do_addi_32;
1998 } else {
1999 tcg_out32(s, SUBF | TAB(a0, a2, a1));
2000 }
2001 break;
2002
2003 case INDEX_op_and_i32:
2004 a0 = args[0], a1 = args[1], a2 = args[2];
2005 if (const_args[2]) {
2006 tcg_out_andi32(s, a0, a1, a2);
2007 } else {
2008 tcg_out32(s, AND | SAB(a1, a0, a2));
2009 }
2010 break;
2011 case INDEX_op_and_i64:
2012 a0 = args[0], a1 = args[1], a2 = args[2];
2013 if (const_args[2]) {
2014 tcg_out_andi64(s, a0, a1, a2);
2015 } else {
2016 tcg_out32(s, AND | SAB(a1, a0, a2));
2017 }
2018 break;
2019 case INDEX_op_or_i64:
2020 case INDEX_op_or_i32:
2021 a0 = args[0], a1 = args[1], a2 = args[2];
2022 if (const_args[2]) {
2023 tcg_out_ori32(s, a0, a1, a2);
2024 } else {
2025 tcg_out32(s, OR | SAB(a1, a0, a2));
2026 }
2027 break;
2028 case INDEX_op_xor_i64:
2029 case INDEX_op_xor_i32:
2030 a0 = args[0], a1 = args[1], a2 = args[2];
2031 if (const_args[2]) {
2032 tcg_out_xori32(s, a0, a1, a2);
2033 } else {
2034 tcg_out32(s, XOR | SAB(a1, a0, a2));
2035 }
2036 break;
2037 case INDEX_op_andc_i32:
2038 a0 = args[0], a1 = args[1], a2 = args[2];
2039 if (const_args[2]) {
2040 tcg_out_andi32(s, a0, a1, ~a2);
2041 } else {
2042 tcg_out32(s, ANDC | SAB(a1, a0, a2));
2043 }
2044 break;
2045 case INDEX_op_andc_i64:
2046 a0 = args[0], a1 = args[1], a2 = args[2];
2047 if (const_args[2]) {
2048 tcg_out_andi64(s, a0, a1, ~a2);
2049 } else {
2050 tcg_out32(s, ANDC | SAB(a1, a0, a2));
2051 }
2052 break;
2053 case INDEX_op_orc_i32:
2054 if (const_args[2]) {
2055 tcg_out_ori32(s, args[0], args[1], ~args[2]);
2056 break;
2057 }
2058 /* FALLTHRU */
2059 case INDEX_op_orc_i64:
2060 tcg_out32(s, ORC | SAB(args[1], args[0], args[2]));
2061 break;
2062 case INDEX_op_eqv_i32:
2063 if (const_args[2]) {
2064 tcg_out_xori32(s, args[0], args[1], ~args[2]);
2065 break;
2066 }
2067 /* FALLTHRU */
2068 case INDEX_op_eqv_i64:
2069 tcg_out32(s, EQV | SAB(args[1], args[0], args[2]));
2070 break;
2071 case INDEX_op_nand_i32:
2072 case INDEX_op_nand_i64:
2073 tcg_out32(s, NAND | SAB(args[1], args[0], args[2]));
2074 break;
2075 case INDEX_op_nor_i32:
2076 case INDEX_op_nor_i64:
2077 tcg_out32(s, NOR | SAB(args[1], args[0], args[2]));
2078 break;
2079
2080 case INDEX_op_mul_i32:
2081 a0 = args[0], a1 = args[1], a2 = args[2];
2082 if (const_args[2]) {
2083 tcg_out32(s, MULLI | TAI(a0, a1, a2));
2084 } else {
2085 tcg_out32(s, MULLW | TAB(a0, a1, a2));
2086 }
2087 break;
2088
2089 case INDEX_op_div_i32:
2090 tcg_out32(s, DIVW | TAB(args[0], args[1], args[2]));
2091 break;
2092
2093 case INDEX_op_divu_i32:
2094 tcg_out32(s, DIVWU | TAB(args[0], args[1], args[2]));
2095 break;
2096
2097 case INDEX_op_shl_i32:
2098 if (const_args[2]) {
2099 tcg_out_shli32(s, args[0], args[1], args[2]);
2100 } else {
2101 tcg_out32(s, SLW | SAB(args[1], args[0], args[2]));
2102 }
2103 break;
2104 case INDEX_op_shr_i32:
2105 if (const_args[2]) {
2106 tcg_out_shri32(s, args[0], args[1], args[2]);
2107 } else {
2108 tcg_out32(s, SRW | SAB(args[1], args[0], args[2]));
2109 }
2110 break;
2111 case INDEX_op_sar_i32:
2112 if (const_args[2]) {
2113 tcg_out32(s, SRAWI | RS(args[1]) | RA(args[0]) | SH(args[2]));
2114 } else {
2115 tcg_out32(s, SRAW | SAB(args[1], args[0], args[2]));
2116 }
2117 break;
2118 case INDEX_op_rotl_i32:
2119 if (const_args[2]) {
2120 tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31);
2121 } else {
2122 tcg_out32(s, RLWNM | SAB(args[1], args[0], args[2])
2123 | MB(0) | ME(31));
2124 }
2125 break;
2126 case INDEX_op_rotr_i32:
2127 if (const_args[2]) {
2128 tcg_out_rlw(s, RLWINM, args[0], args[1], 32 - args[2], 0, 31);
2129 } else {
2130 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 32));
2131 tcg_out32(s, RLWNM | SAB(args[1], args[0], TCG_REG_R0)
2132 | MB(0) | ME(31));
2133 }
2134 break;
2135
2136 case INDEX_op_brcond_i32:
2137 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
2138 arg_label(args[3]), TCG_TYPE_I32);
2139 break;
2140 case INDEX_op_brcond_i64:
2141 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
2142 arg_label(args[3]), TCG_TYPE_I64);
2143 break;
2144 case INDEX_op_brcond2_i32:
2145 tcg_out_brcond2(s, args, const_args);
2146 break;
2147
2148 case INDEX_op_neg_i32:
2149 case INDEX_op_neg_i64:
2150 tcg_out32(s, NEG | RT(args[0]) | RA(args[1]));
2151 break;
2152
2153 case INDEX_op_not_i32:
2154 case INDEX_op_not_i64:
2155 tcg_out32(s, NOR | SAB(args[1], args[0], args[1]));
2156 break;
2157
2158 case INDEX_op_add_i64:
2159 a0 = args[0], a1 = args[1], a2 = args[2];
2160 if (const_args[2]) {
2161 do_addi_64:
2162 tcg_out_mem_long(s, ADDI, ADD, a0, a1, a2);
2163 } else {
2164 tcg_out32(s, ADD | TAB(a0, a1, a2));
2165 }
2166 break;
2167 case INDEX_op_sub_i64:
2168 a0 = args[0], a1 = args[1], a2 = args[2];
2169 if (const_args[1]) {
2170 if (const_args[2]) {
2171 tcg_out_movi(s, TCG_TYPE_I64, a0, a1 - a2);
2172 } else {
2173 tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
2174 }
2175 } else if (const_args[2]) {
2176 a2 = -a2;
2177 goto do_addi_64;
2178 } else {
2179 tcg_out32(s, SUBF | TAB(a0, a2, a1));
2180 }
2181 break;
2182
2183 case INDEX_op_shl_i64:
2184 if (const_args[2]) {
2185 tcg_out_shli64(s, args[0], args[1], args[2]);
2186 } else {
2187 tcg_out32(s, SLD | SAB(args[1], args[0], args[2]));
2188 }
2189 break;
2190 case INDEX_op_shr_i64:
2191 if (const_args[2]) {
2192 tcg_out_shri64(s, args[0], args[1], args[2]);
2193 } else {
2194 tcg_out32(s, SRD | SAB(args[1], args[0], args[2]));
2195 }
2196 break;
2197 case INDEX_op_sar_i64:
2198 if (const_args[2]) {
2199 int sh = SH(args[2] & 0x1f) | (((args[2] >> 5) & 1) << 1);
2200 tcg_out32(s, SRADI | RA(args[0]) | RS(args[1]) | sh);
2201 } else {
2202 tcg_out32(s, SRAD | SAB(args[1], args[0], args[2]));
2203 }
2204 break;
2205 case INDEX_op_rotl_i64:
2206 if (const_args[2]) {
2207 tcg_out_rld(s, RLDICL, args[0], args[1], args[2], 0);
2208 } else {
2209 tcg_out32(s, RLDCL | SAB(args[1], args[0], args[2]) | MB64(0));
2210 }
2211 break;
2212 case INDEX_op_rotr_i64:
2213 if (const_args[2]) {
2214 tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 0);
2215 } else {
2216 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 64));
2217 tcg_out32(s, RLDCL | SAB(args[1], args[0], TCG_REG_R0) | MB64(0));
2218 }
2219 break;
2220
2221 case INDEX_op_mul_i64:
2222 a0 = args[0], a1 = args[1], a2 = args[2];
2223 if (const_args[2]) {
2224 tcg_out32(s, MULLI | TAI(a0, a1, a2));
2225 } else {
2226 tcg_out32(s, MULLD | TAB(a0, a1, a2));
2227 }
2228 break;
2229 case INDEX_op_div_i64:
2230 tcg_out32(s, DIVD | TAB(args[0], args[1], args[2]));
2231 break;
2232 case INDEX_op_divu_i64:
2233 tcg_out32(s, DIVDU | TAB(args[0], args[1], args[2]));
2234 break;
2235
2236 case INDEX_op_qemu_ld_i32:
2237 tcg_out_qemu_ld(s, args, false);
2238 break;
2239 case INDEX_op_qemu_ld_i64:
2240 tcg_out_qemu_ld(s, args, true);
2241 break;
2242 case INDEX_op_qemu_st_i32:
2243 tcg_out_qemu_st(s, args, false);
2244 break;
2245 case INDEX_op_qemu_st_i64:
2246 tcg_out_qemu_st(s, args, true);
2247 break;
2248
2249 case INDEX_op_ext8s_i32:
2250 case INDEX_op_ext8s_i64:
2251 c = EXTSB;
2252 goto gen_ext;
2253 case INDEX_op_ext16s_i32:
2254 case INDEX_op_ext16s_i64:
2255 c = EXTSH;
2256 goto gen_ext;
2257 case INDEX_op_ext_i32_i64:
2258 case INDEX_op_ext32s_i64:
2259 c = EXTSW;
2260 goto gen_ext;
2261 gen_ext:
2262 tcg_out32(s, c | RS(args[1]) | RA(args[0]));
2263 break;
2264 case INDEX_op_extu_i32_i64:
2265 tcg_out_ext32u(s, args[0], args[1]);
2266 break;
2267
2268 case INDEX_op_setcond_i32:
2269 tcg_out_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], args[2],
2270 const_args[2]);
2271 break;
2272 case INDEX_op_setcond_i64:
2273 tcg_out_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], args[2],
2274 const_args[2]);
2275 break;
2276 case INDEX_op_setcond2_i32:
2277 tcg_out_setcond2(s, args, const_args);
2278 break;
2279
2280 case INDEX_op_bswap16_i32:
2281 case INDEX_op_bswap16_i64:
2282 a0 = args[0], a1 = args[1];
2283 /* a1 = abcd */
2284 if (a0 != a1) {
2285 /* a0 = (a1 r<< 24) & 0xff # 000c */
2286 tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
2287 /* a0 = (a0 & ~0xff00) | (a1 r<< 8) & 0xff00 # 00dc */
2288 tcg_out_rlw(s, RLWIMI, a0, a1, 8, 16, 23);
2289 } else {
2290 /* r0 = (a1 r<< 8) & 0xff00 # 00d0 */
2291 tcg_out_rlw(s, RLWINM, TCG_REG_R0, a1, 8, 16, 23);
2292 /* a0 = (a1 r<< 24) & 0xff # 000c */
2293 tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
2294 /* a0 = a0 | r0 # 00dc */
2295 tcg_out32(s, OR | SAB(TCG_REG_R0, a0, a0));
2296 }
2297 break;
2298
2299 case INDEX_op_bswap32_i32:
2300 case INDEX_op_bswap32_i64:
2301 /* Stolen from gcc's builtin_bswap32 */
2302 a1 = args[1];
2303 a0 = args[0] == a1 ? TCG_REG_R0 : args[0];
2304
2305 /* a1 = args[1] # abcd */
2306 /* a0 = rotate_left (a1, 8) # bcda */
2307 tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
2308 /* a0 = (a0 & ~0xff000000) | ((a1 r<< 24) & 0xff000000) # dcda */
2309 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
2310 /* a0 = (a0 & ~0x0000ff00) | ((a1 r<< 24) & 0x0000ff00) # dcba */
2311 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
2312
2313 if (a0 == TCG_REG_R0) {
2314 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
2315 }
2316 break;
2317
2318 case INDEX_op_bswap64_i64:
2319 a0 = args[0], a1 = args[1], a2 = TCG_REG_R0;
2320 if (a0 == a1) {
2321 a0 = TCG_REG_R0;
2322 a2 = a1;
2323 }
2324
2325 /* a1 = # abcd efgh */
2326 /* a0 = rl32(a1, 8) # 0000 fghe */
2327 tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
2328 /* a0 = dep(a0, rl32(a1, 24), 0xff000000) # 0000 hghe */
2329 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
2330 /* a0 = dep(a0, rl32(a1, 24), 0x0000ff00) # 0000 hgfe */
2331 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
2332
2333 /* a0 = rl64(a0, 32) # hgfe 0000 */
2334 /* a2 = rl64(a1, 32) # efgh abcd */
2335 tcg_out_rld(s, RLDICL, a0, a0, 32, 0);
2336 tcg_out_rld(s, RLDICL, a2, a1, 32, 0);
2337
2338 /* a0 = dep(a0, rl32(a2, 8), 0xffffffff) # hgfe bcda */
2339 tcg_out_rlw(s, RLWIMI, a0, a2, 8, 0, 31);
2340 /* a0 = dep(a0, rl32(a2, 24), 0xff000000) # hgfe dcda */
2341 tcg_out_rlw(s, RLWIMI, a0, a2, 24, 0, 7);
2342 /* a0 = dep(a0, rl32(a2, 24), 0x0000ff00) # hgfe dcba */
2343 tcg_out_rlw(s, RLWIMI, a0, a2, 24, 16, 23);
2344
2345 if (a0 == 0) {
2346 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
2347 }
2348 break;
2349
2350 case INDEX_op_deposit_i32:
2351 if (const_args[2]) {
2352 uint32_t mask = ((2u << (args[4] - 1)) - 1) << args[3];
2353 tcg_out_andi32(s, args[0], args[0], ~mask);
2354 } else {
2355 tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3],
2356 32 - args[3] - args[4], 31 - args[3]);
2357 }
2358 break;
2359 case INDEX_op_deposit_i64:
2360 if (const_args[2]) {
2361 uint64_t mask = ((2ull << (args[4] - 1)) - 1) << args[3];
2362 tcg_out_andi64(s, args[0], args[0], ~mask);
2363 } else {
2364 tcg_out_rld(s, RLDIMI, args[0], args[2], args[3],
2365 64 - args[3] - args[4]);
2366 }
2367 break;
2368
2369 case INDEX_op_movcond_i32:
2370 tcg_out_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], args[2],
2371 args[3], args[4], const_args[2]);
2372 break;
2373 case INDEX_op_movcond_i64:
2374 tcg_out_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], args[2],
2375 args[3], args[4], const_args[2]);
2376 break;
2377
2378 #if TCG_TARGET_REG_BITS == 64
2379 case INDEX_op_add2_i64:
2380 #else
2381 case INDEX_op_add2_i32:
2382 #endif
2383 /* Note that the CA bit is defined based on the word size of the
2384 environment. So in 64-bit mode it's always carry-out of bit 63.
2385 The fallback code using deposit works just as well for 32-bit. */
2386 a0 = args[0], a1 = args[1];
2387 if (a0 == args[3] || (!const_args[5] && a0 == args[5])) {
2388 a0 = TCG_REG_R0;
2389 }
2390 if (const_args[4]) {
2391 tcg_out32(s, ADDIC | TAI(a0, args[2], args[4]));
2392 } else {
2393 tcg_out32(s, ADDC | TAB(a0, args[2], args[4]));
2394 }
2395 if (const_args[5]) {
2396 tcg_out32(s, (args[5] ? ADDME : ADDZE) | RT(a1) | RA(args[3]));
2397 } else {
2398 tcg_out32(s, ADDE | TAB(a1, args[3], args[5]));
2399 }
2400 if (a0 != args[0]) {
2401 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
2402 }
2403 break;
2404
2405 #if TCG_TARGET_REG_BITS == 64
2406 case INDEX_op_sub2_i64:
2407 #else
2408 case INDEX_op_sub2_i32:
2409 #endif
2410 a0 = args[0], a1 = args[1];
2411 if (a0 == args[5] || (!const_args[3] && a0 == args[3])) {
2412 a0 = TCG_REG_R0;
2413 }
2414 if (const_args[2]) {
2415 tcg_out32(s, SUBFIC | TAI(a0, args[4], args[2]));
2416 } else {
2417 tcg_out32(s, SUBFC | TAB(a0, args[4], args[2]));
2418 }
2419 if (const_args[3]) {
2420 tcg_out32(s, (args[3] ? SUBFME : SUBFZE) | RT(a1) | RA(args[5]));
2421 } else {
2422 tcg_out32(s, SUBFE | TAB(a1, args[5], args[3]));
2423 }
2424 if (a0 != args[0]) {
2425 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
2426 }
2427 break;
2428
2429 case INDEX_op_muluh_i32:
2430 tcg_out32(s, MULHWU | TAB(args[0], args[1], args[2]));
2431 break;
2432 case INDEX_op_mulsh_i32:
2433 tcg_out32(s, MULHW | TAB(args[0], args[1], args[2]));
2434 break;
2435 case INDEX_op_muluh_i64:
2436 tcg_out32(s, MULHDU | TAB(args[0], args[1], args[2]));
2437 break;
2438 case INDEX_op_mulsh_i64:
2439 tcg_out32(s, MULHD | TAB(args[0], args[1], args[2]));
2440 break;
2441
2442 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
2443 case INDEX_op_mov_i64:
2444 case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
2445 case INDEX_op_movi_i64:
2446 case INDEX_op_call: /* Always emitted via tcg_out_call. */
2447 default:
2448 tcg_abort();
2449 }
2450 }
2451
2452 static const TCGTargetOpDef ppc_op_defs[] = {
2453 { INDEX_op_exit_tb, { } },
2454 { INDEX_op_goto_tb, { } },
2455 { INDEX_op_br, { } },
2456
2457 { INDEX_op_ld8u_i32, { "r", "r" } },
2458 { INDEX_op_ld8s_i32, { "r", "r" } },
2459 { INDEX_op_ld16u_i32, { "r", "r" } },
2460 { INDEX_op_ld16s_i32, { "r", "r" } },
2461 { INDEX_op_ld_i32, { "r", "r" } },
2462
2463 { INDEX_op_st8_i32, { "r", "r" } },
2464 { INDEX_op_st16_i32, { "r", "r" } },
2465 { INDEX_op_st_i32, { "r", "r" } },
2466
2467 { INDEX_op_add_i32, { "r", "r", "ri" } },
2468 { INDEX_op_mul_i32, { "r", "r", "rI" } },
2469 { INDEX_op_div_i32, { "r", "r", "r" } },
2470 { INDEX_op_divu_i32, { "r", "r", "r" } },
2471 { INDEX_op_sub_i32, { "r", "rI", "ri" } },
2472 { INDEX_op_and_i32, { "r", "r", "ri" } },
2473 { INDEX_op_or_i32, { "r", "r", "ri" } },
2474 { INDEX_op_xor_i32, { "r", "r", "ri" } },
2475 { INDEX_op_andc_i32, { "r", "r", "ri" } },
2476 { INDEX_op_orc_i32, { "r", "r", "ri" } },
2477 { INDEX_op_eqv_i32, { "r", "r", "ri" } },
2478 { INDEX_op_nand_i32, { "r", "r", "r" } },
2479 { INDEX_op_nor_i32, { "r", "r", "r" } },
2480
2481 { INDEX_op_shl_i32, { "r", "r", "ri" } },
2482 { INDEX_op_shr_i32, { "r", "r", "ri" } },
2483 { INDEX_op_sar_i32, { "r", "r", "ri" } },
2484 { INDEX_op_rotl_i32, { "r", "r", "ri" } },
2485 { INDEX_op_rotr_i32, { "r", "r", "ri" } },
2486
2487 { INDEX_op_neg_i32, { "r", "r" } },
2488 { INDEX_op_not_i32, { "r", "r" } },
2489 { INDEX_op_ext8s_i32, { "r", "r" } },
2490 { INDEX_op_ext16s_i32, { "r", "r" } },
2491 { INDEX_op_bswap16_i32, { "r", "r" } },
2492 { INDEX_op_bswap32_i32, { "r", "r" } },
2493
2494 { INDEX_op_brcond_i32, { "r", "ri" } },
2495 { INDEX_op_setcond_i32, { "r", "r", "ri" } },
2496 { INDEX_op_movcond_i32, { "r", "r", "ri", "rZ", "rZ" } },
2497
2498 { INDEX_op_deposit_i32, { "r", "0", "rZ" } },
2499
2500 { INDEX_op_muluh_i32, { "r", "r", "r" } },
2501 { INDEX_op_mulsh_i32, { "r", "r", "r" } },
2502
2503 #if TCG_TARGET_REG_BITS == 64
2504 { INDEX_op_ld8u_i64, { "r", "r" } },
2505 { INDEX_op_ld8s_i64, { "r", "r" } },
2506 { INDEX_op_ld16u_i64, { "r", "r" } },
2507 { INDEX_op_ld16s_i64, { "r", "r" } },
2508 { INDEX_op_ld32u_i64, { "r", "r" } },
2509 { INDEX_op_ld32s_i64, { "r", "r" } },
2510 { INDEX_op_ld_i64, { "r", "r" } },
2511
2512 { INDEX_op_st8_i64, { "r", "r" } },
2513 { INDEX_op_st16_i64, { "r", "r" } },
2514 { INDEX_op_st32_i64, { "r", "r" } },
2515 { INDEX_op_st_i64, { "r", "r" } },
2516
2517 { INDEX_op_add_i64, { "r", "r", "rT" } },
2518 { INDEX_op_sub_i64, { "r", "rI", "rT" } },
2519 { INDEX_op_and_i64, { "r", "r", "ri" } },
2520 { INDEX_op_or_i64, { "r", "r", "rU" } },
2521 { INDEX_op_xor_i64, { "r", "r", "rU" } },
2522 { INDEX_op_andc_i64, { "r", "r", "ri" } },
2523 { INDEX_op_orc_i64, { "r", "r", "r" } },
2524 { INDEX_op_eqv_i64, { "r", "r", "r" } },
2525 { INDEX_op_nand_i64, { "r", "r", "r" } },
2526 { INDEX_op_nor_i64, { "r", "r", "r" } },
2527
2528 { INDEX_op_shl_i64, { "r", "r", "ri" } },
2529 { INDEX_op_shr_i64, { "r", "r", "ri" } },
2530 { INDEX_op_sar_i64, { "r", "r", "ri" } },
2531 { INDEX_op_rotl_i64, { "r", "r", "ri" } },
2532 { INDEX_op_rotr_i64, { "r", "r", "ri" } },
2533
2534 { INDEX_op_mul_i64, { "r", "r", "rI" } },
2535 { INDEX_op_div_i64, { "r", "r", "r" } },
2536 { INDEX_op_divu_i64, { "r", "r", "r" } },
2537
2538 { INDEX_op_neg_i64, { "r", "r" } },
2539 { INDEX_op_not_i64, { "r", "r" } },
2540 { INDEX_op_ext8s_i64, { "r", "r" } },
2541 { INDEX_op_ext16s_i64, { "r", "r" } },
2542 { INDEX_op_ext32s_i64, { "r", "r" } },
2543 { INDEX_op_ext_i32_i64, { "r", "r" } },
2544 { INDEX_op_extu_i32_i64, { "r", "r" } },
2545 { INDEX_op_bswap16_i64, { "r", "r" } },
2546 { INDEX_op_bswap32_i64, { "r", "r" } },
2547 { INDEX_op_bswap64_i64, { "r", "r" } },
2548
2549 { INDEX_op_brcond_i64, { "r", "ri" } },
2550 { INDEX_op_setcond_i64, { "r", "r", "ri" } },
2551 { INDEX_op_movcond_i64, { "r", "r", "ri", "rZ", "rZ" } },
2552
2553 { INDEX_op_deposit_i64, { "r", "0", "rZ" } },
2554
2555 { INDEX_op_mulsh_i64, { "r", "r", "r" } },
2556 { INDEX_op_muluh_i64, { "r", "r", "r" } },
2557 #endif
2558
2559 #if TCG_TARGET_REG_BITS == 32
2560 { INDEX_op_brcond2_i32, { "r", "r", "ri", "ri" } },
2561 { INDEX_op_setcond2_i32, { "r", "r", "r", "ri", "ri" } },
2562 #endif
2563
2564 #if TCG_TARGET_REG_BITS == 64
2565 { INDEX_op_add2_i64, { "r", "r", "r", "r", "rI", "rZM" } },
2566 { INDEX_op_sub2_i64, { "r", "r", "rI", "rZM", "r", "r" } },
2567 #else
2568 { INDEX_op_add2_i32, { "r", "r", "r", "r", "rI", "rZM" } },
2569 { INDEX_op_sub2_i32, { "r", "r", "rI", "rZM", "r", "r" } },
2570 #endif
2571
2572 #if TCG_TARGET_REG_BITS == 64
2573 { INDEX_op_qemu_ld_i32, { "r", "L" } },
2574 { INDEX_op_qemu_st_i32, { "S", "S" } },
2575 { INDEX_op_qemu_ld_i64, { "r", "L" } },
2576 { INDEX_op_qemu_st_i64, { "S", "S" } },
2577 #elif TARGET_LONG_BITS == 32
2578 { INDEX_op_qemu_ld_i32, { "r", "L" } },
2579 { INDEX_op_qemu_st_i32, { "S", "S" } },
2580 { INDEX_op_qemu_ld_i64, { "L", "L", "L" } },
2581 { INDEX_op_qemu_st_i64, { "S", "S", "S" } },
2582 #else
2583 { INDEX_op_qemu_ld_i32, { "r", "L", "L" } },
2584 { INDEX_op_qemu_st_i32, { "S", "S", "S" } },
2585 { INDEX_op_qemu_ld_i64, { "L", "L", "L", "L" } },
2586 { INDEX_op_qemu_st_i64, { "S", "S", "S", "S" } },
2587 #endif
2588
2589 { -1 },
2590 };
2591
2592 static void tcg_target_init(TCGContext *s)
2593 {
2594 unsigned long hwcap = qemu_getauxval(AT_HWCAP);
2595 if (hwcap & PPC_FEATURE_ARCH_2_06) {
2596 have_isa_2_06 = true;
2597 }
2598
2599 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
2600 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);
2601 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
2602 (1 << TCG_REG_R0) |
2603 (1 << TCG_REG_R2) |
2604 (1 << TCG_REG_R3) |
2605 (1 << TCG_REG_R4) |
2606 (1 << TCG_REG_R5) |
2607 (1 << TCG_REG_R6) |
2608 (1 << TCG_REG_R7) |
2609 (1 << TCG_REG_R8) |
2610 (1 << TCG_REG_R9) |
2611 (1 << TCG_REG_R10) |
2612 (1 << TCG_REG_R11) |
2613 (1 << TCG_REG_R12));
2614
2615 tcg_regset_clear(s->reserved_regs);
2616 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */
2617 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* stack pointer */
2618 #if defined(_CALL_SYSV)
2619 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* toc pointer */
2620 #endif
2621 #if defined(_CALL_SYSV) || TCG_TARGET_REG_BITS == 64
2622 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */
2623 #endif
2624 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); /* mem temp */
2625 if (USE_REG_RA) {
2626 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return addr */
2627 }
2628
2629 tcg_add_target_add_op_defs(ppc_op_defs);
2630 }
2631
2632 #ifdef __ELF__
2633 typedef struct {
2634 DebugFrameCIE cie;
2635 DebugFrameFDEHeader fde;
2636 uint8_t fde_def_cfa[4];
2637 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2 + 3];
2638 } DebugFrame;
2639
2640 /* We're expecting a 2 byte uleb128 encoded value. */
2641 QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14));
2642
2643 #if TCG_TARGET_REG_BITS == 64
2644 # define ELF_HOST_MACHINE EM_PPC64
2645 #else
2646 # define ELF_HOST_MACHINE EM_PPC
2647 #endif
2648
2649 static DebugFrame debug_frame = {
2650 .cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
2651 .cie.id = -1,
2652 .cie.version = 1,
2653 .cie.code_align = 1,
2654 .cie.data_align = (-SZR & 0x7f), /* sleb128 -SZR */
2655 .cie.return_column = 65,
2656
2657 /* Total FDE size does not include the "len" member. */
2658 .fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, fde.cie_offset),
2659
2660 .fde_def_cfa = {
2661 12, TCG_REG_R1, /* DW_CFA_def_cfa r1, ... */
2662 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2663 (FRAME_SIZE >> 7)
2664 },
2665 .fde_reg_ofs = {
2666 /* DW_CFA_offset_extended_sf, lr, LR_OFFSET */
2667 0x11, 65, (LR_OFFSET / -SZR) & 0x7f,
2668 }
2669 };
2670
2671 void tcg_register_jit(void *buf, size_t buf_size)
2672 {
2673 uint8_t *p = &debug_frame.fde_reg_ofs[3];
2674 int i;
2675
2676 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i, p += 2) {
2677 p[0] = 0x80 + tcg_target_callee_save_regs[i];
2678 p[1] = (FRAME_SIZE - (REG_SAVE_BOT + i * SZR)) / SZR;
2679 }
2680
2681 debug_frame.fde.func_start = (uintptr_t)buf;
2682 debug_frame.fde.func_len = buf_size;
2683
2684 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
2685 }
2686 #endif /* __ELF__ */
2687
2688 static size_t dcache_bsize = 16;
2689 static size_t icache_bsize = 16;
2690
2691 void flush_icache_range(uintptr_t start, uintptr_t stop)
2692 {
2693 uintptr_t p, start1, stop1;
2694 size_t dsize = dcache_bsize;
2695 size_t isize = icache_bsize;
2696
2697 start1 = start & ~(dsize - 1);
2698 stop1 = (stop + dsize - 1) & ~(dsize - 1);
2699 for (p = start1; p < stop1; p += dsize) {
2700 asm volatile ("dcbst 0,%0" : : "r"(p) : "memory");
2701 }
2702 asm volatile ("sync" : : : "memory");
2703
2704 start &= start & ~(isize - 1);
2705 stop1 = (stop + isize - 1) & ~(isize - 1);
2706 for (p = start1; p < stop1; p += isize) {
2707 asm volatile ("icbi 0,%0" : : "r"(p) : "memory");
2708 }
2709 asm volatile ("sync" : : : "memory");
2710 asm volatile ("isync" : : : "memory");
2711 }
2712
2713 #if defined _AIX
2714 #include <sys/systemcfg.h>
2715
2716 static void __attribute__((constructor)) tcg_cache_init(void)
2717 {
2718 icache_bsize = _system_configuration.icache_line;
2719 dcache_bsize = _system_configuration.dcache_line;
2720 }
2721
2722 #elif defined __linux__
2723 static void __attribute__((constructor)) tcg_cache_init(void)
2724 {
2725 unsigned long dsize = qemu_getauxval(AT_DCACHEBSIZE);
2726 unsigned long isize = qemu_getauxval(AT_ICACHEBSIZE);
2727
2728 if (dsize == 0 || isize == 0) {
2729 if (dsize == 0) {
2730 fprintf(stderr, "getauxval AT_DCACHEBSIZE failed\n");
2731 }
2732 if (isize == 0) {
2733 fprintf(stderr, "getauxval AT_ICACHEBSIZE failed\n");
2734 }
2735 exit(1);
2736 }
2737 dcache_bsize = dsize;
2738 icache_bsize = isize;
2739 }
2740
2741 #elif defined __APPLE__
2742 #include <sys/sysctl.h>
2743
2744 static void __attribute__((constructor)) tcg_cache_init(void)
2745 {
2746 size_t len;
2747 unsigned cacheline;
2748 int name[2] = { CTL_HW, HW_CACHELINE };
2749
2750 len = sizeof(cacheline);
2751 if (sysctl(name, 2, &cacheline, &len, NULL, 0)) {
2752 perror("sysctl CTL_HW HW_CACHELINE failed");
2753 exit(1);
2754 }
2755 dcache_bsize = cacheline;
2756 icache_bsize = cacheline;
2757 }
2758
2759 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
2760 #include <sys/sysctl.h>
2761
2762 static void __attribute__((constructor)) tcg_cache_init(void)
2763 {
2764 size_t len = 4;
2765 unsigned cacheline;
2766
2767 if (sysctlbyname ("machdep.cacheline_size", &cacheline, &len, NULL, 0)) {
2768 fprintf(stderr, "sysctlbyname machdep.cacheline_size failed: %s\n",
2769 strerror(errno));
2770 exit(1);
2771 }
2772 dcache_bsize = cacheline;
2773 icache_bsize = cacheline;
2774 }
2775 #endif
AR7 emulation for QEMU