2 * Tiny Code Interpreter for QEMU
4 * Copyright (c) 2009, 2011, 2016 Stefan Weil
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
22 /* Enable TCI assertions only when debugging TCG (and without NDEBUG defined).
23 * Without assertions, the interpreter runs much faster. */
24 #if defined(CONFIG_DEBUG_TCG)
25 # define tci_assert(cond) assert(cond)
27 # define tci_assert(cond) ((void)0)
30 #include "qemu-common.h"
31 #include "tcg/tcg.h" /* MAX_OPC_PARAM_IARGS */
32 #include "exec/cpu_ldst.h"
35 /* Marker for missing code. */
38 fprintf(stderr, "TODO %s:%u: %s()\n", \
39 __FILE__, __LINE__, __func__); \
43 #if MAX_OPC_PARAM_IARGS != 6
44 # error Fix needed, number of supported input arguments changed!
46 #if TCG_TARGET_REG_BITS == 32
47 typedef uint64_t (*helper_function
)(tcg_target_ulong
, tcg_target_ulong
,
48 tcg_target_ulong
, tcg_target_ulong
,
49 tcg_target_ulong
, tcg_target_ulong
,
50 tcg_target_ulong
, tcg_target_ulong
,
51 tcg_target_ulong
, tcg_target_ulong
,
52 tcg_target_ulong
, tcg_target_ulong
);
54 typedef uint64_t (*helper_function
)(tcg_target_ulong
, tcg_target_ulong
,
55 tcg_target_ulong
, tcg_target_ulong
,
56 tcg_target_ulong
, tcg_target_ulong
);
59 static tcg_target_ulong
tci_read_reg(const tcg_target_ulong
*regs
, TCGReg index
)
61 tci_assert(index
< TCG_TARGET_NB_REGS
);
65 #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
66 static int8_t tci_read_reg8s(const tcg_target_ulong
*regs
, TCGReg index
)
68 return (int8_t)tci_read_reg(regs
, index
);
72 #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
73 static int16_t tci_read_reg16s(const tcg_target_ulong
*regs
, TCGReg index
)
75 return (int16_t)tci_read_reg(regs
, index
);
79 #if TCG_TARGET_REG_BITS == 64
80 static int32_t tci_read_reg32s(const tcg_target_ulong
*regs
, TCGReg index
)
82 return (int32_t)tci_read_reg(regs
, index
);
86 static uint8_t tci_read_reg8(const tcg_target_ulong
*regs
, TCGReg index
)
88 return (uint8_t)tci_read_reg(regs
, index
);
91 static uint16_t tci_read_reg16(const tcg_target_ulong
*regs
, TCGReg index
)
93 return (uint16_t)tci_read_reg(regs
, index
);
96 static uint32_t tci_read_reg32(const tcg_target_ulong
*regs
, TCGReg index
)
98 return (uint32_t)tci_read_reg(regs
, index
);
101 #if TCG_TARGET_REG_BITS == 64
102 static uint64_t tci_read_reg64(const tcg_target_ulong
*regs
, TCGReg index
)
104 return tci_read_reg(regs
, index
);
109 tci_write_reg(tcg_target_ulong
*regs
, TCGReg index
, tcg_target_ulong value
)
111 tci_assert(index
< TCG_TARGET_NB_REGS
);
112 tci_assert(index
!= TCG_AREG0
);
113 tci_assert(index
!= TCG_REG_CALL_STACK
);
117 #if TCG_TARGET_REG_BITS == 64
119 tci_write_reg32s(tcg_target_ulong
*regs
, TCGReg index
, int32_t value
)
121 tci_write_reg(regs
, index
, value
);
125 static void tci_write_reg8(tcg_target_ulong
*regs
, TCGReg index
, uint8_t value
)
127 tci_write_reg(regs
, index
, value
);
131 tci_write_reg32(tcg_target_ulong
*regs
, TCGReg index
, uint32_t value
)
133 tci_write_reg(regs
, index
, value
);
136 #if TCG_TARGET_REG_BITS == 32
137 static void tci_write_reg64(tcg_target_ulong
*regs
, uint32_t high_index
,
138 uint32_t low_index
, uint64_t value
)
140 tci_write_reg(regs
, low_index
, value
);
141 tci_write_reg(regs
, high_index
, value
>> 32);
143 #elif TCG_TARGET_REG_BITS == 64
145 tci_write_reg64(tcg_target_ulong
*regs
, TCGReg index
, uint64_t value
)
147 tci_write_reg(regs
, index
, value
);
151 #if TCG_TARGET_REG_BITS == 32
152 /* Create a 64 bit value from two 32 bit values. */
153 static uint64_t tci_uint64(uint32_t high
, uint32_t low
)
155 return ((uint64_t)high
<< 32) + low
;
159 /* Read constant (native size) from bytecode. */
160 static tcg_target_ulong
tci_read_i(uint8_t **tb_ptr
)
162 tcg_target_ulong value
= *(tcg_target_ulong
*)(*tb_ptr
);
163 *tb_ptr
+= sizeof(value
);
167 /* Read unsigned constant (32 bit) from bytecode. */
168 static uint32_t tci_read_i32(uint8_t **tb_ptr
)
170 uint32_t value
= *(uint32_t *)(*tb_ptr
);
171 *tb_ptr
+= sizeof(value
);
175 /* Read signed constant (32 bit) from bytecode. */
176 static int32_t tci_read_s32(uint8_t **tb_ptr
)
178 int32_t value
= *(int32_t *)(*tb_ptr
);
179 *tb_ptr
+= sizeof(value
);
183 #if TCG_TARGET_REG_BITS == 64
184 /* Read constant (64 bit) from bytecode. */
185 static uint64_t tci_read_i64(uint8_t **tb_ptr
)
187 uint64_t value
= *(uint64_t *)(*tb_ptr
);
188 *tb_ptr
+= sizeof(value
);
193 /* Read indexed register (native size) from bytecode. */
194 static tcg_target_ulong
195 tci_read_r(const tcg_target_ulong
*regs
, uint8_t **tb_ptr
)
197 tcg_target_ulong value
= tci_read_reg(regs
, **tb_ptr
);
202 /* Read indexed register (8 bit) from bytecode. */
203 static uint8_t tci_read_r8(const tcg_target_ulong
*regs
, uint8_t **tb_ptr
)
205 uint8_t value
= tci_read_reg8(regs
, **tb_ptr
);
210 #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
211 /* Read indexed register (8 bit signed) from bytecode. */
212 static int8_t tci_read_r8s(const tcg_target_ulong
*regs
, uint8_t **tb_ptr
)
214 int8_t value
= tci_read_reg8s(regs
, **tb_ptr
);
220 /* Read indexed register (16 bit) from bytecode. */
221 static uint16_t tci_read_r16(const tcg_target_ulong
*regs
, uint8_t **tb_ptr
)
223 uint16_t value
= tci_read_reg16(regs
, **tb_ptr
);
228 #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
229 /* Read indexed register (16 bit signed) from bytecode. */
230 static int16_t tci_read_r16s(const tcg_target_ulong
*regs
, uint8_t **tb_ptr
)
232 int16_t value
= tci_read_reg16s(regs
, **tb_ptr
);
238 /* Read indexed register (32 bit) from bytecode. */
239 static uint32_t tci_read_r32(const tcg_target_ulong
*regs
, uint8_t **tb_ptr
)
241 uint32_t value
= tci_read_reg32(regs
, **tb_ptr
);
246 #if TCG_TARGET_REG_BITS == 32
247 /* Read two indexed registers (2 * 32 bit) from bytecode. */
248 static uint64_t tci_read_r64(const tcg_target_ulong
*regs
, uint8_t **tb_ptr
)
250 uint32_t low
= tci_read_r32(regs
, tb_ptr
);
251 return tci_uint64(tci_read_r32(regs
, tb_ptr
), low
);
253 #elif TCG_TARGET_REG_BITS == 64
254 /* Read indexed register (32 bit signed) from bytecode. */
255 static int32_t tci_read_r32s(const tcg_target_ulong
*regs
, uint8_t **tb_ptr
)
257 int32_t value
= tci_read_reg32s(regs
, **tb_ptr
);
262 /* Read indexed register (64 bit) from bytecode. */
263 static uint64_t tci_read_r64(const tcg_target_ulong
*regs
, uint8_t **tb_ptr
)
265 uint64_t value
= tci_read_reg64(regs
, **tb_ptr
);
271 /* Read indexed register(s) with target address from bytecode. */
273 tci_read_ulong(const tcg_target_ulong
*regs
, uint8_t **tb_ptr
)
275 target_ulong taddr
= tci_read_r(regs
, tb_ptr
);
276 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
277 taddr
+= (uint64_t)tci_read_r(regs
, tb_ptr
) << 32;
282 /* Read indexed register or constant (native size) from bytecode. */
283 static tcg_target_ulong
284 tci_read_ri(const tcg_target_ulong
*regs
, uint8_t **tb_ptr
)
286 tcg_target_ulong value
;
289 if (r
== TCG_CONST
) {
290 value
= tci_read_i(tb_ptr
);
292 value
= tci_read_reg(regs
, r
);
297 /* Read indexed register or constant (32 bit) from bytecode. */
298 static uint32_t tci_read_ri32(const tcg_target_ulong
*regs
, uint8_t **tb_ptr
)
303 if (r
== TCG_CONST
) {
304 value
= tci_read_i32(tb_ptr
);
306 value
= tci_read_reg32(regs
, r
);
311 #if TCG_TARGET_REG_BITS == 32
312 /* Read two indexed registers or constants (2 * 32 bit) from bytecode. */
313 static uint64_t tci_read_ri64(const tcg_target_ulong
*regs
, uint8_t **tb_ptr
)
315 uint32_t low
= tci_read_ri32(regs
, tb_ptr
);
316 return tci_uint64(tci_read_ri32(regs
, tb_ptr
), low
);
318 #elif TCG_TARGET_REG_BITS == 64
319 /* Read indexed register or constant (64 bit) from bytecode. */
320 static uint64_t tci_read_ri64(const tcg_target_ulong
*regs
, uint8_t **tb_ptr
)
325 if (r
== TCG_CONST
) {
326 value
= tci_read_i64(tb_ptr
);
328 value
= tci_read_reg64(regs
, r
);
334 static tcg_target_ulong
tci_read_label(uint8_t **tb_ptr
)
336 tcg_target_ulong label
= tci_read_i(tb_ptr
);
337 tci_assert(label
!= 0);
341 static bool tci_compare32(uint32_t u0
, uint32_t u1
, TCGCond condition
)
383 static bool tci_compare64(uint64_t u0
, uint64_t u1
, TCGCond condition
)
425 #ifdef CONFIG_SOFTMMU
426 # define qemu_ld_ub \
427 helper_ret_ldub_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
428 # define qemu_ld_leuw \
429 helper_le_lduw_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
430 # define qemu_ld_leul \
431 helper_le_ldul_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
432 # define qemu_ld_leq \
433 helper_le_ldq_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
434 # define qemu_ld_beuw \
435 helper_be_lduw_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
436 # define qemu_ld_beul \
437 helper_be_ldul_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
438 # define qemu_ld_beq \
439 helper_be_ldq_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
440 # define qemu_st_b(X) \
441 helper_ret_stb_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
442 # define qemu_st_lew(X) \
443 helper_le_stw_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
444 # define qemu_st_lel(X) \
445 helper_le_stl_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
446 # define qemu_st_leq(X) \
447 helper_le_stq_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
448 # define qemu_st_bew(X) \
449 helper_be_stw_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
450 # define qemu_st_bel(X) \
451 helper_be_stl_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
452 # define qemu_st_beq(X) \
453 helper_be_stq_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
455 # define qemu_ld_ub ldub_p(g2h(taddr))
456 # define qemu_ld_leuw lduw_le_p(g2h(taddr))
457 # define qemu_ld_leul (uint32_t)ldl_le_p(g2h(taddr))
458 # define qemu_ld_leq ldq_le_p(g2h(taddr))
459 # define qemu_ld_beuw lduw_be_p(g2h(taddr))
460 # define qemu_ld_beul (uint32_t)ldl_be_p(g2h(taddr))
461 # define qemu_ld_beq ldq_be_p(g2h(taddr))
462 # define qemu_st_b(X) stb_p(g2h(taddr), X)
463 # define qemu_st_lew(X) stw_le_p(g2h(taddr), X)
464 # define qemu_st_lel(X) stl_le_p(g2h(taddr), X)
465 # define qemu_st_leq(X) stq_le_p(g2h(taddr), X)
466 # define qemu_st_bew(X) stw_be_p(g2h(taddr), X)
467 # define qemu_st_bel(X) stl_be_p(g2h(taddr), X)
468 # define qemu_st_beq(X) stq_be_p(g2h(taddr), X)
471 /* Interpret pseudo code in tb. */
472 uintptr_t tcg_qemu_tb_exec(CPUArchState
*env
, uint8_t *tb_ptr
)
474 tcg_target_ulong regs
[TCG_TARGET_NB_REGS
];
475 long tcg_temps
[CPU_TEMP_BUF_NLONGS
];
476 uintptr_t sp_value
= (uintptr_t)(tcg_temps
+ CPU_TEMP_BUF_NLONGS
);
479 regs
[TCG_AREG0
] = (tcg_target_ulong
)env
;
480 regs
[TCG_REG_CALL_STACK
] = sp_value
;
484 TCGOpcode opc
= tb_ptr
[0];
485 #if defined(CONFIG_DEBUG_TCG) && !defined(NDEBUG)
486 uint8_t op_size
= tb_ptr
[1];
487 uint8_t *old_code_ptr
= tb_ptr
;
492 tcg_target_ulong label
;
499 #if TCG_TARGET_REG_BITS == 32
505 tci_tb_ptr
= (uintptr_t)tb_ptr
;
508 /* Skip opcode and size entry. */
513 t0
= tci_read_ri(regs
, &tb_ptr
);
514 #if TCG_TARGET_REG_BITS == 32
515 tmp64
= ((helper_function
)t0
)(tci_read_reg(regs
, TCG_REG_R0
),
516 tci_read_reg(regs
, TCG_REG_R1
),
517 tci_read_reg(regs
, TCG_REG_R2
),
518 tci_read_reg(regs
, TCG_REG_R3
),
519 tci_read_reg(regs
, TCG_REG_R5
),
520 tci_read_reg(regs
, TCG_REG_R6
),
521 tci_read_reg(regs
, TCG_REG_R7
),
522 tci_read_reg(regs
, TCG_REG_R8
),
523 tci_read_reg(regs
, TCG_REG_R9
),
524 tci_read_reg(regs
, TCG_REG_R10
),
525 tci_read_reg(regs
, TCG_REG_R11
),
526 tci_read_reg(regs
, TCG_REG_R12
));
527 tci_write_reg(regs
, TCG_REG_R0
, tmp64
);
528 tci_write_reg(regs
, TCG_REG_R1
, tmp64
>> 32);
530 tmp64
= ((helper_function
)t0
)(tci_read_reg(regs
, TCG_REG_R0
),
531 tci_read_reg(regs
, TCG_REG_R1
),
532 tci_read_reg(regs
, TCG_REG_R2
),
533 tci_read_reg(regs
, TCG_REG_R3
),
534 tci_read_reg(regs
, TCG_REG_R5
),
535 tci_read_reg(regs
, TCG_REG_R6
));
536 tci_write_reg(regs
, TCG_REG_R0
, tmp64
);
540 label
= tci_read_label(&tb_ptr
);
541 tci_assert(tb_ptr
== old_code_ptr
+ op_size
);
542 tb_ptr
= (uint8_t *)label
;
544 case INDEX_op_setcond_i32
:
546 t1
= tci_read_r32(regs
, &tb_ptr
);
547 t2
= tci_read_ri32(regs
, &tb_ptr
);
548 condition
= *tb_ptr
++;
549 tci_write_reg32(regs
, t0
, tci_compare32(t1
, t2
, condition
));
551 #if TCG_TARGET_REG_BITS == 32
552 case INDEX_op_setcond2_i32
:
554 tmp64
= tci_read_r64(regs
, &tb_ptr
);
555 v64
= tci_read_ri64(regs
, &tb_ptr
);
556 condition
= *tb_ptr
++;
557 tci_write_reg32(regs
, t0
, tci_compare64(tmp64
, v64
, condition
));
559 #elif TCG_TARGET_REG_BITS == 64
560 case INDEX_op_setcond_i64
:
562 t1
= tci_read_r64(regs
, &tb_ptr
);
563 t2
= tci_read_ri64(regs
, &tb_ptr
);
564 condition
= *tb_ptr
++;
565 tci_write_reg64(regs
, t0
, tci_compare64(t1
, t2
, condition
));
568 case INDEX_op_mov_i32
:
570 t1
= tci_read_r32(regs
, &tb_ptr
);
571 tci_write_reg32(regs
, t0
, t1
);
573 case INDEX_op_movi_i32
:
575 t1
= tci_read_i32(&tb_ptr
);
576 tci_write_reg32(regs
, t0
, t1
);
579 /* Load/store operations (32 bit). */
581 case INDEX_op_ld8u_i32
:
583 t1
= tci_read_r(regs
, &tb_ptr
);
584 t2
= tci_read_s32(&tb_ptr
);
585 tci_write_reg8(regs
, t0
, *(uint8_t *)(t1
+ t2
));
587 case INDEX_op_ld8s_i32
:
588 case INDEX_op_ld16u_i32
:
591 case INDEX_op_ld16s_i32
:
594 case INDEX_op_ld_i32
:
596 t1
= tci_read_r(regs
, &tb_ptr
);
597 t2
= tci_read_s32(&tb_ptr
);
598 tci_write_reg32(regs
, t0
, *(uint32_t *)(t1
+ t2
));
600 case INDEX_op_st8_i32
:
601 t0
= tci_read_r8(regs
, &tb_ptr
);
602 t1
= tci_read_r(regs
, &tb_ptr
);
603 t2
= tci_read_s32(&tb_ptr
);
604 *(uint8_t *)(t1
+ t2
) = t0
;
606 case INDEX_op_st16_i32
:
607 t0
= tci_read_r16(regs
, &tb_ptr
);
608 t1
= tci_read_r(regs
, &tb_ptr
);
609 t2
= tci_read_s32(&tb_ptr
);
610 *(uint16_t *)(t1
+ t2
) = t0
;
612 case INDEX_op_st_i32
:
613 t0
= tci_read_r32(regs
, &tb_ptr
);
614 t1
= tci_read_r(regs
, &tb_ptr
);
615 t2
= tci_read_s32(&tb_ptr
);
616 tci_assert(t1
!= sp_value
|| (int32_t)t2
< 0);
617 *(uint32_t *)(t1
+ t2
) = t0
;
620 /* Arithmetic operations (32 bit). */
622 case INDEX_op_add_i32
:
624 t1
= tci_read_ri32(regs
, &tb_ptr
);
625 t2
= tci_read_ri32(regs
, &tb_ptr
);
626 tci_write_reg32(regs
, t0
, t1
+ t2
);
628 case INDEX_op_sub_i32
:
630 t1
= tci_read_ri32(regs
, &tb_ptr
);
631 t2
= tci_read_ri32(regs
, &tb_ptr
);
632 tci_write_reg32(regs
, t0
, t1
- t2
);
634 case INDEX_op_mul_i32
:
636 t1
= tci_read_ri32(regs
, &tb_ptr
);
637 t2
= tci_read_ri32(regs
, &tb_ptr
);
638 tci_write_reg32(regs
, t0
, t1
* t2
);
640 #if TCG_TARGET_HAS_div_i32
641 case INDEX_op_div_i32
:
643 t1
= tci_read_ri32(regs
, &tb_ptr
);
644 t2
= tci_read_ri32(regs
, &tb_ptr
);
645 tci_write_reg32(regs
, t0
, (int32_t)t1
/ (int32_t)t2
);
647 case INDEX_op_divu_i32
:
649 t1
= tci_read_ri32(regs
, &tb_ptr
);
650 t2
= tci_read_ri32(regs
, &tb_ptr
);
651 tci_write_reg32(regs
, t0
, t1
/ t2
);
653 case INDEX_op_rem_i32
:
655 t1
= tci_read_ri32(regs
, &tb_ptr
);
656 t2
= tci_read_ri32(regs
, &tb_ptr
);
657 tci_write_reg32(regs
, t0
, (int32_t)t1
% (int32_t)t2
);
659 case INDEX_op_remu_i32
:
661 t1
= tci_read_ri32(regs
, &tb_ptr
);
662 t2
= tci_read_ri32(regs
, &tb_ptr
);
663 tci_write_reg32(regs
, t0
, t1
% t2
);
665 #elif TCG_TARGET_HAS_div2_i32
666 case INDEX_op_div2_i32
:
667 case INDEX_op_divu2_i32
:
671 case INDEX_op_and_i32
:
673 t1
= tci_read_ri32(regs
, &tb_ptr
);
674 t2
= tci_read_ri32(regs
, &tb_ptr
);
675 tci_write_reg32(regs
, t0
, t1
& t2
);
677 case INDEX_op_or_i32
:
679 t1
= tci_read_ri32(regs
, &tb_ptr
);
680 t2
= tci_read_ri32(regs
, &tb_ptr
);
681 tci_write_reg32(regs
, t0
, t1
| t2
);
683 case INDEX_op_xor_i32
:
685 t1
= tci_read_ri32(regs
, &tb_ptr
);
686 t2
= tci_read_ri32(regs
, &tb_ptr
);
687 tci_write_reg32(regs
, t0
, t1
^ t2
);
690 /* Shift/rotate operations (32 bit). */
692 case INDEX_op_shl_i32
:
694 t1
= tci_read_ri32(regs
, &tb_ptr
);
695 t2
= tci_read_ri32(regs
, &tb_ptr
);
696 tci_write_reg32(regs
, t0
, t1
<< (t2
& 31));
698 case INDEX_op_shr_i32
:
700 t1
= tci_read_ri32(regs
, &tb_ptr
);
701 t2
= tci_read_ri32(regs
, &tb_ptr
);
702 tci_write_reg32(regs
, t0
, t1
>> (t2
& 31));
704 case INDEX_op_sar_i32
:
706 t1
= tci_read_ri32(regs
, &tb_ptr
);
707 t2
= tci_read_ri32(regs
, &tb_ptr
);
708 tci_write_reg32(regs
, t0
, ((int32_t)t1
>> (t2
& 31)));
710 #if TCG_TARGET_HAS_rot_i32
711 case INDEX_op_rotl_i32
:
713 t1
= tci_read_ri32(regs
, &tb_ptr
);
714 t2
= tci_read_ri32(regs
, &tb_ptr
);
715 tci_write_reg32(regs
, t0
, rol32(t1
, t2
& 31));
717 case INDEX_op_rotr_i32
:
719 t1
= tci_read_ri32(regs
, &tb_ptr
);
720 t2
= tci_read_ri32(regs
, &tb_ptr
);
721 tci_write_reg32(regs
, t0
, ror32(t1
, t2
& 31));
724 #if TCG_TARGET_HAS_deposit_i32
725 case INDEX_op_deposit_i32
:
727 t1
= tci_read_r32(regs
, &tb_ptr
);
728 t2
= tci_read_r32(regs
, &tb_ptr
);
731 tmp32
= (((1 << tmp8
) - 1) << tmp16
);
732 tci_write_reg32(regs
, t0
, (t1
& ~tmp32
) | ((t2
<< tmp16
) & tmp32
));
735 case INDEX_op_brcond_i32
:
736 t0
= tci_read_r32(regs
, &tb_ptr
);
737 t1
= tci_read_ri32(regs
, &tb_ptr
);
738 condition
= *tb_ptr
++;
739 label
= tci_read_label(&tb_ptr
);
740 if (tci_compare32(t0
, t1
, condition
)) {
741 tci_assert(tb_ptr
== old_code_ptr
+ op_size
);
742 tb_ptr
= (uint8_t *)label
;
746 #if TCG_TARGET_REG_BITS == 32
747 case INDEX_op_add2_i32
:
750 tmp64
= tci_read_r64(regs
, &tb_ptr
);
751 tmp64
+= tci_read_r64(regs
, &tb_ptr
);
752 tci_write_reg64(regs
, t1
, t0
, tmp64
);
754 case INDEX_op_sub2_i32
:
757 tmp64
= tci_read_r64(regs
, &tb_ptr
);
758 tmp64
-= tci_read_r64(regs
, &tb_ptr
);
759 tci_write_reg64(regs
, t1
, t0
, tmp64
);
761 case INDEX_op_brcond2_i32
:
762 tmp64
= tci_read_r64(regs
, &tb_ptr
);
763 v64
= tci_read_ri64(regs
, &tb_ptr
);
764 condition
= *tb_ptr
++;
765 label
= tci_read_label(&tb_ptr
);
766 if (tci_compare64(tmp64
, v64
, condition
)) {
767 tci_assert(tb_ptr
== old_code_ptr
+ op_size
);
768 tb_ptr
= (uint8_t *)label
;
772 case INDEX_op_mulu2_i32
:
775 t2
= tci_read_r32(regs
, &tb_ptr
);
776 tmp64
= tci_read_r32(regs
, &tb_ptr
);
777 tci_write_reg64(regs
, t1
, t0
, t2
* tmp64
);
779 #endif /* TCG_TARGET_REG_BITS == 32 */
780 #if TCG_TARGET_HAS_ext8s_i32
781 case INDEX_op_ext8s_i32
:
783 t1
= tci_read_r8s(regs
, &tb_ptr
);
784 tci_write_reg32(regs
, t0
, t1
);
787 #if TCG_TARGET_HAS_ext16s_i32
788 case INDEX_op_ext16s_i32
:
790 t1
= tci_read_r16s(regs
, &tb_ptr
);
791 tci_write_reg32(regs
, t0
, t1
);
794 #if TCG_TARGET_HAS_ext8u_i32
795 case INDEX_op_ext8u_i32
:
797 t1
= tci_read_r8(regs
, &tb_ptr
);
798 tci_write_reg32(regs
, t0
, t1
);
801 #if TCG_TARGET_HAS_ext16u_i32
802 case INDEX_op_ext16u_i32
:
804 t1
= tci_read_r16(regs
, &tb_ptr
);
805 tci_write_reg32(regs
, t0
, t1
);
808 #if TCG_TARGET_HAS_bswap16_i32
809 case INDEX_op_bswap16_i32
:
811 t1
= tci_read_r16(regs
, &tb_ptr
);
812 tci_write_reg32(regs
, t0
, bswap16(t1
));
815 #if TCG_TARGET_HAS_bswap32_i32
816 case INDEX_op_bswap32_i32
:
818 t1
= tci_read_r32(regs
, &tb_ptr
);
819 tci_write_reg32(regs
, t0
, bswap32(t1
));
822 #if TCG_TARGET_HAS_not_i32
823 case INDEX_op_not_i32
:
825 t1
= tci_read_r32(regs
, &tb_ptr
);
826 tci_write_reg32(regs
, t0
, ~t1
);
829 #if TCG_TARGET_HAS_neg_i32
830 case INDEX_op_neg_i32
:
832 t1
= tci_read_r32(regs
, &tb_ptr
);
833 tci_write_reg32(regs
, t0
, -t1
);
836 #if TCG_TARGET_REG_BITS == 64
837 case INDEX_op_mov_i64
:
839 t1
= tci_read_r64(regs
, &tb_ptr
);
840 tci_write_reg64(regs
, t0
, t1
);
842 case INDEX_op_movi_i64
:
844 t1
= tci_read_i64(&tb_ptr
);
845 tci_write_reg64(regs
, t0
, t1
);
848 /* Load/store operations (64 bit). */
850 case INDEX_op_ld8u_i64
:
852 t1
= tci_read_r(regs
, &tb_ptr
);
853 t2
= tci_read_s32(&tb_ptr
);
854 tci_write_reg8(regs
, t0
, *(uint8_t *)(t1
+ t2
));
856 case INDEX_op_ld8s_i64
:
857 case INDEX_op_ld16u_i64
:
858 case INDEX_op_ld16s_i64
:
861 case INDEX_op_ld32u_i64
:
863 t1
= tci_read_r(regs
, &tb_ptr
);
864 t2
= tci_read_s32(&tb_ptr
);
865 tci_write_reg32(regs
, t0
, *(uint32_t *)(t1
+ t2
));
867 case INDEX_op_ld32s_i64
:
869 t1
= tci_read_r(regs
, &tb_ptr
);
870 t2
= tci_read_s32(&tb_ptr
);
871 tci_write_reg32s(regs
, t0
, *(int32_t *)(t1
+ t2
));
873 case INDEX_op_ld_i64
:
875 t1
= tci_read_r(regs
, &tb_ptr
);
876 t2
= tci_read_s32(&tb_ptr
);
877 tci_write_reg64(regs
, t0
, *(uint64_t *)(t1
+ t2
));
879 case INDEX_op_st8_i64
:
880 t0
= tci_read_r8(regs
, &tb_ptr
);
881 t1
= tci_read_r(regs
, &tb_ptr
);
882 t2
= tci_read_s32(&tb_ptr
);
883 *(uint8_t *)(t1
+ t2
) = t0
;
885 case INDEX_op_st16_i64
:
886 t0
= tci_read_r16(regs
, &tb_ptr
);
887 t1
= tci_read_r(regs
, &tb_ptr
);
888 t2
= tci_read_s32(&tb_ptr
);
889 *(uint16_t *)(t1
+ t2
) = t0
;
891 case INDEX_op_st32_i64
:
892 t0
= tci_read_r32(regs
, &tb_ptr
);
893 t1
= tci_read_r(regs
, &tb_ptr
);
894 t2
= tci_read_s32(&tb_ptr
);
895 *(uint32_t *)(t1
+ t2
) = t0
;
897 case INDEX_op_st_i64
:
898 t0
= tci_read_r64(regs
, &tb_ptr
);
899 t1
= tci_read_r(regs
, &tb_ptr
);
900 t2
= tci_read_s32(&tb_ptr
);
901 tci_assert(t1
!= sp_value
|| (int32_t)t2
< 0);
902 *(uint64_t *)(t1
+ t2
) = t0
;
905 /* Arithmetic operations (64 bit). */
907 case INDEX_op_add_i64
:
909 t1
= tci_read_ri64(regs
, &tb_ptr
);
910 t2
= tci_read_ri64(regs
, &tb_ptr
);
911 tci_write_reg64(regs
, t0
, t1
+ t2
);
913 case INDEX_op_sub_i64
:
915 t1
= tci_read_ri64(regs
, &tb_ptr
);
916 t2
= tci_read_ri64(regs
, &tb_ptr
);
917 tci_write_reg64(regs
, t0
, t1
- t2
);
919 case INDEX_op_mul_i64
:
921 t1
= tci_read_ri64(regs
, &tb_ptr
);
922 t2
= tci_read_ri64(regs
, &tb_ptr
);
923 tci_write_reg64(regs
, t0
, t1
* t2
);
925 #if TCG_TARGET_HAS_div_i64
926 case INDEX_op_div_i64
:
927 case INDEX_op_divu_i64
:
928 case INDEX_op_rem_i64
:
929 case INDEX_op_remu_i64
:
932 #elif TCG_TARGET_HAS_div2_i64
933 case INDEX_op_div2_i64
:
934 case INDEX_op_divu2_i64
:
938 case INDEX_op_and_i64
:
940 t1
= tci_read_ri64(regs
, &tb_ptr
);
941 t2
= tci_read_ri64(regs
, &tb_ptr
);
942 tci_write_reg64(regs
, t0
, t1
& t2
);
944 case INDEX_op_or_i64
:
946 t1
= tci_read_ri64(regs
, &tb_ptr
);
947 t2
= tci_read_ri64(regs
, &tb_ptr
);
948 tci_write_reg64(regs
, t0
, t1
| t2
);
950 case INDEX_op_xor_i64
:
952 t1
= tci_read_ri64(regs
, &tb_ptr
);
953 t2
= tci_read_ri64(regs
, &tb_ptr
);
954 tci_write_reg64(regs
, t0
, t1
^ t2
);
957 /* Shift/rotate operations (64 bit). */
959 case INDEX_op_shl_i64
:
961 t1
= tci_read_ri64(regs
, &tb_ptr
);
962 t2
= tci_read_ri64(regs
, &tb_ptr
);
963 tci_write_reg64(regs
, t0
, t1
<< (t2
& 63));
965 case INDEX_op_shr_i64
:
967 t1
= tci_read_ri64(regs
, &tb_ptr
);
968 t2
= tci_read_ri64(regs
, &tb_ptr
);
969 tci_write_reg64(regs
, t0
, t1
>> (t2
& 63));
971 case INDEX_op_sar_i64
:
973 t1
= tci_read_ri64(regs
, &tb_ptr
);
974 t2
= tci_read_ri64(regs
, &tb_ptr
);
975 tci_write_reg64(regs
, t0
, ((int64_t)t1
>> (t2
& 63)));
977 #if TCG_TARGET_HAS_rot_i64
978 case INDEX_op_rotl_i64
:
980 t1
= tci_read_ri64(regs
, &tb_ptr
);
981 t2
= tci_read_ri64(regs
, &tb_ptr
);
982 tci_write_reg64(regs
, t0
, rol64(t1
, t2
& 63));
984 case INDEX_op_rotr_i64
:
986 t1
= tci_read_ri64(regs
, &tb_ptr
);
987 t2
= tci_read_ri64(regs
, &tb_ptr
);
988 tci_write_reg64(regs
, t0
, ror64(t1
, t2
& 63));
991 #if TCG_TARGET_HAS_deposit_i64
992 case INDEX_op_deposit_i64
:
994 t1
= tci_read_r64(regs
, &tb_ptr
);
995 t2
= tci_read_r64(regs
, &tb_ptr
);
998 tmp64
= (((1ULL << tmp8
) - 1) << tmp16
);
999 tci_write_reg64(regs
, t0
, (t1
& ~tmp64
) | ((t2
<< tmp16
) & tmp64
));
1002 case INDEX_op_brcond_i64
:
1003 t0
= tci_read_r64(regs
, &tb_ptr
);
1004 t1
= tci_read_ri64(regs
, &tb_ptr
);
1005 condition
= *tb_ptr
++;
1006 label
= tci_read_label(&tb_ptr
);
1007 if (tci_compare64(t0
, t1
, condition
)) {
1008 tci_assert(tb_ptr
== old_code_ptr
+ op_size
);
1009 tb_ptr
= (uint8_t *)label
;
1013 #if TCG_TARGET_HAS_ext8u_i64
1014 case INDEX_op_ext8u_i64
:
1016 t1
= tci_read_r8(regs
, &tb_ptr
);
1017 tci_write_reg64(regs
, t0
, t1
);
1020 #if TCG_TARGET_HAS_ext8s_i64
1021 case INDEX_op_ext8s_i64
:
1023 t1
= tci_read_r8s(regs
, &tb_ptr
);
1024 tci_write_reg64(regs
, t0
, t1
);
1027 #if TCG_TARGET_HAS_ext16s_i64
1028 case INDEX_op_ext16s_i64
:
1030 t1
= tci_read_r16s(regs
, &tb_ptr
);
1031 tci_write_reg64(regs
, t0
, t1
);
1034 #if TCG_TARGET_HAS_ext16u_i64
1035 case INDEX_op_ext16u_i64
:
1037 t1
= tci_read_r16(regs
, &tb_ptr
);
1038 tci_write_reg64(regs
, t0
, t1
);
1041 #if TCG_TARGET_HAS_ext32s_i64
1042 case INDEX_op_ext32s_i64
:
1044 case INDEX_op_ext_i32_i64
:
1046 t1
= tci_read_r32s(regs
, &tb_ptr
);
1047 tci_write_reg64(regs
, t0
, t1
);
1049 #if TCG_TARGET_HAS_ext32u_i64
1050 case INDEX_op_ext32u_i64
:
1052 case INDEX_op_extu_i32_i64
:
1054 t1
= tci_read_r32(regs
, &tb_ptr
);
1055 tci_write_reg64(regs
, t0
, t1
);
1057 #if TCG_TARGET_HAS_bswap16_i64
1058 case INDEX_op_bswap16_i64
:
1060 t1
= tci_read_r16(regs
, &tb_ptr
);
1061 tci_write_reg64(regs
, t0
, bswap16(t1
));
1064 #if TCG_TARGET_HAS_bswap32_i64
1065 case INDEX_op_bswap32_i64
:
1067 t1
= tci_read_r32(regs
, &tb_ptr
);
1068 tci_write_reg64(regs
, t0
, bswap32(t1
));
1071 #if TCG_TARGET_HAS_bswap64_i64
1072 case INDEX_op_bswap64_i64
:
1074 t1
= tci_read_r64(regs
, &tb_ptr
);
1075 tci_write_reg64(regs
, t0
, bswap64(t1
));
1078 #if TCG_TARGET_HAS_not_i64
1079 case INDEX_op_not_i64
:
1081 t1
= tci_read_r64(regs
, &tb_ptr
);
1082 tci_write_reg64(regs
, t0
, ~t1
);
1085 #if TCG_TARGET_HAS_neg_i64
1086 case INDEX_op_neg_i64
:
1088 t1
= tci_read_r64(regs
, &tb_ptr
);
1089 tci_write_reg64(regs
, t0
, -t1
);
1092 #endif /* TCG_TARGET_REG_BITS == 64 */
1094 /* QEMU specific operations. */
1096 case INDEX_op_exit_tb
:
1097 ret
= *(uint64_t *)tb_ptr
;
1100 case INDEX_op_goto_tb
:
1101 /* Jump address is aligned */
1102 tb_ptr
= QEMU_ALIGN_PTR_UP(tb_ptr
, 4);
1103 t0
= atomic_read((int32_t *)tb_ptr
);
1104 tb_ptr
+= sizeof(int32_t);
1105 tci_assert(tb_ptr
== old_code_ptr
+ op_size
);
1106 tb_ptr
+= (int32_t)t0
;
1108 case INDEX_op_qemu_ld_i32
:
1110 taddr
= tci_read_ulong(regs
, &tb_ptr
);
1111 oi
= tci_read_i(&tb_ptr
);
1112 switch (get_memop(oi
) & (MO_BSWAP
| MO_SSIZE
)) {
1117 tmp32
= (int8_t)qemu_ld_ub
;
1120 tmp32
= qemu_ld_leuw
;
1123 tmp32
= (int16_t)qemu_ld_leuw
;
1126 tmp32
= qemu_ld_leul
;
1129 tmp32
= qemu_ld_beuw
;
1132 tmp32
= (int16_t)qemu_ld_beuw
;
1135 tmp32
= qemu_ld_beul
;
1140 tci_write_reg(regs
, t0
, tmp32
);
1142 case INDEX_op_qemu_ld_i64
:
1144 if (TCG_TARGET_REG_BITS
== 32) {
1147 taddr
= tci_read_ulong(regs
, &tb_ptr
);
1148 oi
= tci_read_i(&tb_ptr
);
1149 switch (get_memop(oi
) & (MO_BSWAP
| MO_SSIZE
)) {
1154 tmp64
= (int8_t)qemu_ld_ub
;
1157 tmp64
= qemu_ld_leuw
;
1160 tmp64
= (int16_t)qemu_ld_leuw
;
1163 tmp64
= qemu_ld_leul
;
1166 tmp64
= (int32_t)qemu_ld_leul
;
1169 tmp64
= qemu_ld_leq
;
1172 tmp64
= qemu_ld_beuw
;
1175 tmp64
= (int16_t)qemu_ld_beuw
;
1178 tmp64
= qemu_ld_beul
;
1181 tmp64
= (int32_t)qemu_ld_beul
;
1184 tmp64
= qemu_ld_beq
;
1189 tci_write_reg(regs
, t0
, tmp64
);
1190 if (TCG_TARGET_REG_BITS
== 32) {
1191 tci_write_reg(regs
, t1
, tmp64
>> 32);
1194 case INDEX_op_qemu_st_i32
:
1195 t0
= tci_read_r(regs
, &tb_ptr
);
1196 taddr
= tci_read_ulong(regs
, &tb_ptr
);
1197 oi
= tci_read_i(&tb_ptr
);
1198 switch (get_memop(oi
) & (MO_BSWAP
| MO_SIZE
)) {
1218 case INDEX_op_qemu_st_i64
:
1219 tmp64
= tci_read_r64(regs
, &tb_ptr
);
1220 taddr
= tci_read_ulong(regs
, &tb_ptr
);
1221 oi
= tci_read_i(&tb_ptr
);
1222 switch (get_memop(oi
) & (MO_BSWAP
| MO_SIZE
)) {
1249 /* Ensure ordering for all kinds */
1256 tci_assert(tb_ptr
== old_code_ptr
+ op_size
);